3
;==========================================================================
4
; MPASM PIC18F6628 processor include
6
; (c) Copyright 1999-2007 Microchip Technology, All rights reserved
7
;==========================================================================
11
;==========================================================================
12
; This header file defines configurations, registers, and other useful
13
; bits of information for the PIC18F6628 microcontroller. These names
14
; are taken to match the data sheets as closely as possible.
16
; Note that the processor must be selected before this file is included.
17
; The processor may be selected the following ways:
19
; 1. Command line switch:
20
; C:\MPASM MYFILE.ASM /PIC18F6628
21
; 2. LIST directive in the source file
23
; 3. Processor Type entry in the MPASM full-screen interface
24
; 4. Setting the processor in the MPLAB Project Dialog
25
;==========================================================================
27
;==========================================================================
31
;==========================================================================
33
MESSG "Processor-header file mismatch. Verify selected processor."
36
;==========================================================================
37
; 18xxxx Family EQUates
38
;==========================================================================
49
;==========================================================================
51
;==========================================================================
52
; 16Cxxx/17Cxxx Substitutions
53
;==========================================================================
54
#define DDRA TRISA ; PIC17Cxxx SFR substitution
55
#define DDRB TRISB ; PIC17Cxxx SFR substitution
56
#define DDRC TRISC ; PIC17Cxxx SFR substitution
57
#define DDRD TRISD ; PIC17Cxxx SFR substitution
58
#define DDRE TRISE ; PIC17Cxxx SFR substitution
60
;==========================================================================
62
; Register Definitions
64
;==========================================================================
66
;----- Register Files -----------------------------------------------------
249
;----- SSP2CON2 Bits -----------------------------------------------------
260
;----- SSP2CON1 Bits -----------------------------------------------------
271
;----- SSP2STAT Bits -----------------------------------------------------
282
I2C_START EQU H'0003'
289
NOT_WRITE EQU H'0002'
290
NOT_ADDRESS EQU H'0005'
292
READ_WRITE EQU H'0002'
293
DATA_ADDRESS EQU H'0005'
299
;----- ECCP2DEL Bits -----------------------------------------------------
319
;----- ECCP2AS Bits -----------------------------------------------------
339
;----- ECCP3DEL Bits -----------------------------------------------------
359
;----- ECCP3AS Bits -----------------------------------------------------
379
;----- RCSTA2 Bits -----------------------------------------------------
397
;----- TXSTA2 Bits -----------------------------------------------------
413
;----- CCP5CON Bits -----------------------------------------------------
425
;----- CCP4CON Bits -----------------------------------------------------
437
;----- T4CON Bits -----------------------------------------------------
447
;----- ECCP1DEL Bits -----------------------------------------------------
467
;----- BAUDCON2 Bits -----------------------------------------------------
478
;----- BAUDCON Bits -----------------------------------------------------
489
;----- BAUDCON1 Bits -----------------------------------------------------
500
;----- PORTA Bits -----------------------------------------------------
524
;----- PORTB Bits -----------------------------------------------------
546
;----- PORTC Bits -----------------------------------------------------
566
ECCP2_PORTC EQU H'0001'
570
; DT is a reserved word
573
CCP2_PORTC EQU H'0001'
580
P2A_PORTC EQU H'0001'
589
;----- PORTD Bits -----------------------------------------------------
618
;----- PORTE Bits -----------------------------------------------------
631
ECCP2_PORTE EQU H'0007'
644
P2A_PORTE EQU H'0007'
646
CCP2_PORTE EQU H'0007'
649
;----- PORTF Bits -----------------------------------------------------
668
C2OUT_PORTF EQU H'0001'
669
C1OUT_PORTF EQU H'0002'
674
;----- PORTG Bits -----------------------------------------------------
699
;----- LATA Bits -----------------------------------------------------
710
;----- LATB Bits -----------------------------------------------------
721
;----- LATC Bits -----------------------------------------------------
732
;----- LATD Bits -----------------------------------------------------
743
;----- LATE Bits -----------------------------------------------------
754
;----- LATF Bits -----------------------------------------------------
765
;----- LATG Bits -----------------------------------------------------
774
;----- DDRA Bits -----------------------------------------------------
785
;----- TRISA Bits -----------------------------------------------------
796
;----- DDRB Bits -----------------------------------------------------
807
;----- TRISB Bits -----------------------------------------------------
818
;----- DDRC Bits -----------------------------------------------------
829
;----- TRISC Bits -----------------------------------------------------
840
;----- DDRD Bits -----------------------------------------------------
851
;----- TRISD Bits -----------------------------------------------------
862
;----- DDRE Bits -----------------------------------------------------
873
;----- TRISE Bits -----------------------------------------------------
884
;----- DDRF Bits -----------------------------------------------------
895
;----- TRISF Bits -----------------------------------------------------
906
;----- DDRG Bits -----------------------------------------------------
914
;----- TRISG Bits -----------------------------------------------------
922
;----- OSCTUNE Bits -----------------------------------------------------
932
;----- PIE1 Bits -----------------------------------------------------
947
;----- PIR1 Bits -----------------------------------------------------
962
;----- IPR1 Bits -----------------------------------------------------
977
;----- PIE2 Bits -----------------------------------------------------
990
;----- PIR2 Bits -----------------------------------------------------
1003
;----- IPR2 Bits -----------------------------------------------------
1016
;----- PIE3 Bits -----------------------------------------------------
1027
;----- PIR3 Bits -----------------------------------------------------
1038
;----- IPR3 Bits -----------------------------------------------------
1049
;----- EECON1 Bits -----------------------------------------------------
1059
;----- RCSTA Bits -----------------------------------------------------
1077
;----- RCSTA1 Bits -----------------------------------------------------
1095
;----- TXSTA Bits -----------------------------------------------------
1111
;----- TXSTA1 Bits -----------------------------------------------------
1127
;----- PSPCON Bits -----------------------------------------------------
1134
;----- T3CON Bits -----------------------------------------------------
1144
T3INSYNC EQU H'0002'
1146
NOT_T3SYNC EQU H'0002'
1149
;----- CMCON Bits -----------------------------------------------------
1156
C1OUT_CMCON EQU H'0006'
1157
C2OUT_CMCON EQU H'0007'
1160
;----- CVRCON Bits -----------------------------------------------------
1171
;----- ECCP1AS Bits -----------------------------------------------------
1176
ECCP1AS0 EQU H'0004'
1177
ECCP1AS1 EQU H'0005'
1178
ECCP1AS2 EQU H'0006'
1179
ECCP1ASE EQU H'0007'
1191
;----- CCP3CON Bits -----------------------------------------------------
1205
;----- ECCP3CON Bits -----------------------------------------------------
1219
;----- CCP2CON Bits -----------------------------------------------------
1233
;----- ECCP2CON Bits -----------------------------------------------------
1247
;----- CCP1CON Bits -----------------------------------------------------
1261
;----- ECCP1CON Bits -----------------------------------------------------
1275
;----- ADCON2 Bits -----------------------------------------------------
1285
;----- ADCON1 Bits -----------------------------------------------------
1294
;----- ADCON0 Bits -----------------------------------------------------
1306
NOT_DONE EQU H'0001'
1309
;----- SSP1CON2 Bits -----------------------------------------------------
1320
;----- SSPCON2 Bits -----------------------------------------------------
1331
;----- SSP1CON1 Bits -----------------------------------------------------
1342
;----- SSPCON1 Bits -----------------------------------------------------
1353
;----- SSP1STAT Bits -----------------------------------------------------
1363
I2C_READ EQU H'0002'
1364
I2C_START EQU H'0003'
1365
I2C_STOP EQU H'0004'
1371
NOT_WRITE EQU H'0002'
1372
NOT_ADDRESS EQU H'0005'
1374
READ_WRITE EQU H'0002'
1375
DATA_ADDRESS EQU H'0005'
1381
;----- SSPSTAT Bits -----------------------------------------------------
1391
I2C_READ EQU H'0002'
1392
I2C_START EQU H'0003'
1393
I2C_STOP EQU H'0004'
1399
NOT_WRITE EQU H'0002'
1400
NOT_ADDRESS EQU H'0005'
1402
READ_WRITE EQU H'0002'
1403
DATA_ADDRESS EQU H'0005'
1409
;----- T2CON Bits -----------------------------------------------------
1413
T2OUTPS0 EQU H'0003'
1414
T2OUTPS1 EQU H'0004'
1415
T2OUTPS2 EQU H'0005'
1416
T2OUTPS3 EQU H'0006'
1419
;----- T1CON Bits -----------------------------------------------------
1429
T1INSYNC EQU H'0002'
1431
NOT_T1SYNC EQU H'0002'
1434
;----- RCON Bits -----------------------------------------------------
1450
;----- WDTCON Bits -----------------------------------------------------
1456
;----- HLVDCON Bits -----------------------------------------------------
1480
;----- LVDCON Bits -----------------------------------------------------
1504
;----- OSCCON Bits -----------------------------------------------------
1517
;----- T0CON Bits -----------------------------------------------------
1530
;----- STATUS Bits -----------------------------------------------------
1538
;----- INTCON3 Bits -----------------------------------------------------
1558
;----- INTCON2 Bits -----------------------------------------------------
1566
NOT_RBPU EQU H'0007'
1573
;----- INTCON Bits -----------------------------------------------------
1591
;----- STKPTR Bits -----------------------------------------------------
1609
;==========================================================================
1613
;==========================================================================
1615
__BADRAM H'0F7A'-H'0F7B'
1616
__BADRAM H'0F87'-H'0F88'
1617
__BADRAM H'0F90'-H'0F91'
1618
__BADRAM H'0F99'-H'0F9A'
1622
;==========================================================================
1624
; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
1625
; superseded by the CONFIG directive. The following settings
1626
; are available for this device.
1628
; Oscillator Selection bits:
1629
; OSC = LP LP oscillator
1630
; OSC = XT XT oscillator
1631
; OSC = HS HS oscillator
1632
; OSC = RC External RC oscillator, CLKO function on RA6
1633
; OSC = EC EC oscillator, CLKO function on RA6
1634
; OSC = ECIO6 EC oscillator, port function on RA6
1635
; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
1636
; OSC = RCIO6 External RC oscillator, port function on RA6
1637
; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7
1638
; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7
1640
; Fail-Safe Clock Monitor Enable bit:
1641
; FCMEN = OFF Fail-Safe Clock Monitor disabled
1642
; FCMEN = ON Fail-Safe Clock Monitor enabled
1644
; Internal/External Oscillator Switchover bit:
1645
; IESO = OFF Two-Speed Start-up disabled
1646
; IESO = ON Two-Speed Start-up enabled
1648
; Power-up Timer Enable bit:
1649
; PWRT = ON PWRT enabled
1650
; PWRT = OFF PWRT disabled
1652
; Brown-out Reset Enable bits:
1653
; BOREN = OFF Brown-out Reset disabled in hardware and software
1654
; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
1655
; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
1656
; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
1658
; Brown-out Voltage bits:
1659
; BORV = 0 Maximum setting
1662
; BORV = 3 Minimum setting
1664
; Watchdog Timer Enable bit:
1665
; WDT = OFF WDT disabled (control is placed on the SWDTEN bit)
1666
; WDT = ON WDT enabled
1668
; Watchdog Timer Postscale Select bits:
1679
; WDTPS = 1024 1:1024
1680
; WDTPS = 2048 1:2048
1681
; WDTPS = 4096 1:4096
1682
; WDTPS = 8192 1:8192
1683
; WDTPS = 16384 1:16384
1684
; WDTPS = 32768 1:32768
1686
; MCLR Pin Enable bit:
1687
; MCLRE = OFF RG5 input pin enabled; MCLR disabled
1688
; MCLRE = ON MCLR pin enabled; RG5 input pin disabled
1690
; Low-Power Timer1 Oscillator Enable bit:
1691
; LPT1OSC = OFF Timer1 configured for higher power operation
1692
; LPT1OSC = ON Timer1 configured for low-power operation
1695
; CCP2MX = PORTE ECCP2 input/output is multiplexed with RE7
1696
; CCP2MX = PORTC ECCP2 input/output is multiplexed with RC1
1698
; Stack Full/Underflow Reset Enable bit:
1699
; STVREN = OFF Stack full/underflow will not cause Reset
1700
; STVREN = ON Stack full/underflow will cause Reset
1702
; Single-Supply ICSP Enable bit:
1703
; LVP = OFF Single-Supply ICSP disabled
1704
; LVP = ON Single-Supply ICSP enabled
1706
; Boot Block Size Select bits:
1707
; BBSIZ = BB2K 1K word (2 Kbytes) Boot Block size
1708
; BBSIZ = BB4K 2K words (4 Kbytes) Boot Block size
1709
; BBSIZ = BB8K 4K words (8 Kbytes) Boot Block size
1711
; Extended Instruction Set Enable bit:
1712
; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
1713
; XINST = ON Instruction set extension and Indexed Addressing mode enabled
1715
; Background Debugger Enable bit:
1716
; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
1717
; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
1719
; Code Protection bit Block 0:
1720
; CP0 = ON Block 0 (000800, 001000 or 002000-003FFFh) code-protected
1721
; CP0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not code-protected
1723
; Code Protection bit Block 1:
1724
; CP1 = ON Block 1 (004000-007FFFh) code-protected
1725
; CP1 = OFF Block 1 (004000-007FFFh) not code-protected
1727
; Code Protection bit Block 2:
1728
; CP2 = ON Block 2 (008000-00BFFFh) code-protected
1729
; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected
1731
; Code Protection bit Block 3:
1732
; CP3 = ON Block 3 (00C000-00FFFFh) code-protected
1733
; CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected
1735
; Code Protection bit Block 4:
1736
; CP4 = ON Block 4 (010000-013FFFh) code-protected
1737
; CP4 = OFF Block 4 (010000-013FFFh) not code-protected
1739
; Code Protection bit Block 5:
1740
; CP5 = ON Block 5 (014000-017FFFh) code-protected
1741
; CP5 = OFF Block 5 (014000-017FFFh) not code-protected
1743
; Boot Block Code Protection bit:
1744
; CPB = ON Boot Block (000000-0007FFh) code-protected
1745
; CPB = OFF Boot Block (000000-0007FFh) not code-protected
1747
; Data EEPROM Code Protection bit:
1748
; CPD = ON Data EEPROM code-protected
1749
; CPD = OFF Data EEPROM not code-protected
1751
; Write Protection bit Block 0:
1752
; WRT0 = ON Block 0 (000800, 001000 or 002000-003FFFh) write-protected
1753
; WRT0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not write-protected
1755
; Write Protection bit Block 1:
1756
; WRT1 = ON Block 1 (004000-007FFFh) write-protected
1757
; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected
1759
; Write Protection bit Block 2:
1760
; WRT2 = ON Block 2 (008000-00BFFFh) write-protected
1761
; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected
1763
; Write Protection bit Block 3:
1764
; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected
1765
; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected
1767
; Write Protection bit Block 4:
1768
; WRT4 = ON Block 4 (010000-013FFFh) write-protected
1769
; WRT4 = OFF Block 4 (010000-013FFFh) not write-protected
1771
; Write Protection bit Block 5:
1772
; WRT5 = ON Block 5 (014000-017FFFh) write-protected
1773
; WRT5 = OFF Block 5 (014000-017FFFh) not write-protected
1775
; Boot Block Write Protection bit:
1776
; WRTB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected
1777
; WRTB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected
1779
; Configuration Register Write Protection bit:
1780
; WRTC = ON Configuration registers (300000-3000FFh) write-protected
1781
; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected
1783
; Data EEPROM Write Protection bit:
1784
; WRTD = ON Data EEPROM write-protected
1785
; WRTD = OFF Data EEPROM not write-protected
1787
; Table Read Protection bit Block 0:
1788
; EBTR0 = ON Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks
1789
; EBTR0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks
1791
; Table Read Protection bit Block 1:
1792
; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks
1793
; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
1795
; Table Read Protection bit Block 2:
1796
; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks
1797
; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
1799
; Table Read Protection bit Block 3:
1800
; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks
1801
; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
1803
; Table Read Protection bit Block 4:
1804
; EBTR4 = ON Block 4 (010000-013FFFh) protected from table reads executed in other blocks
1805
; EBTR4 = OFF Block 4 (010000-013FFFh) not protected from table reads executed in other blocks
1807
; Table Read Protection bit Block 5:
1808
; EBTR5 = ON Block 5 (014000-017FFFh) protected from table reads executed in other blocks
1809
; EBTR5 = OFF Block 5 (014000-017FFFh) not protected from table reads executed in other blocks
1811
; Boot Block Table Read Protection bit:
1812
; EBTRB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks
1813
; EBTRB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks
1815
;==========================================================================
1816
;==========================================================================
1818
; Configuration Bits
1833
;==========================================================================
1835
; The following is an assignment of address values for all of the
1836
; configuration registers for the purpose of table reads
1837
_CONFIG1H EQU H'300001'
1838
_CONFIG2L EQU H'300002'
1839
_CONFIG2H EQU H'300003'
1840
_CONFIG3H EQU H'300005'
1841
_CONFIG4L EQU H'300006'
1842
_CONFIG5L EQU H'300008'
1843
_CONFIG5H EQU H'300009'
1844
_CONFIG6L EQU H'30000A'
1845
_CONFIG6H EQU H'30000B'
1846
_CONFIG7L EQU H'30000C'
1847
_CONFIG7H EQU H'30000D'
1849
;----- CONFIG1H Options --------------------------------------------------
1850
_OSC_LP_1H EQU H'F0' ; LP oscillator
1851
_OSC_XT_1H EQU H'F1' ; XT oscillator
1852
_OSC_HS_1H EQU H'F2' ; HS oscillator
1853
_OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6
1854
_OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6
1855
_OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6
1856
_OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
1857
_OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6
1858
_OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7
1859
_OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7
1861
_FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled
1862
_FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled
1864
_IESO_OFF_1H EQU H'7F' ; Two-Speed Start-up disabled
1865
_IESO_ON_1H EQU H'FF' ; Two-Speed Start-up enabled
1867
;----- CONFIG2L Options --------------------------------------------------
1868
_PWRT_ON_2L EQU H'FE' ; PWRT enabled
1869
_PWRT_OFF_2L EQU H'FF' ; PWRT disabled
1871
_BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software
1872
_BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled)
1873
_BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
1874
_BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
1876
_BORV_0_2L EQU H'E7' ; Maximum setting
1877
_BORV_1_2L EQU H'EF' ;
1878
_BORV_2_2L EQU H'F7' ;
1879
_BORV_3_2L EQU H'FF' ; Minimum setting
1881
;----- CONFIG2H Options --------------------------------------------------
1882
_WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit)
1883
_WDT_ON_2H EQU H'FF' ; WDT enabled
1885
_WDTPS_1_2H EQU H'E1' ; 1:1
1886
_WDTPS_2_2H EQU H'E3' ; 1:2
1887
_WDTPS_4_2H EQU H'E5' ; 1:4
1888
_WDTPS_8_2H EQU H'E7' ; 1:8
1889
_WDTPS_16_2H EQU H'E9' ; 1:16
1890
_WDTPS_32_2H EQU H'EB' ; 1:32
1891
_WDTPS_64_2H EQU H'ED' ; 1:64
1892
_WDTPS_128_2H EQU H'EF' ; 1:128
1893
_WDTPS_256_2H EQU H'F1' ; 1:256
1894
_WDTPS_512_2H EQU H'F3' ; 1:512
1895
_WDTPS_1024_2H EQU H'F5' ; 1:1024
1896
_WDTPS_2048_2H EQU H'F7' ; 1:2048
1897
_WDTPS_4096_2H EQU H'F9' ; 1:4096
1898
_WDTPS_8192_2H EQU H'FB' ; 1:8192
1899
_WDTPS_16384_2H EQU H'FD' ; 1:16384
1900
_WDTPS_32768_2H EQU H'FF' ; 1:32768
1902
;----- CONFIG3H Options --------------------------------------------------
1903
_MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled
1904
_MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled
1906
_LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation
1907
_LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation
1909
_CCP2MX_PORTE_3H EQU H'FE' ; ECCP2 input/output is multiplexed with RE7
1910
_CCP2MX_PORTC_3H EQU H'FF' ; ECCP2 input/output is multiplexed with RC1
1912
;----- CONFIG4L Options --------------------------------------------------
1913
_STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset
1914
_STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset
1916
_LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled
1917
_LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled
1919
_BBSIZ_BB2K_4L EQU H'CF' ; 1K word (2 Kbytes) Boot Block size
1920
_BBSIZ_BB4K_4L EQU H'DF' ; 2K words (4 Kbytes) Boot Block size
1921
_BBSIZ_BB8K_4L EQU H'FF' ; 4K words (8 Kbytes) Boot Block size
1923
_XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
1924
_XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled
1926
_DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
1927
_DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
1929
;----- CONFIG5L Options --------------------------------------------------
1930
_CP0_ON_5L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) code-protected
1931
_CP0_OFF_5L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not code-protected
1933
_CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected
1934
_CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected
1936
_CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected
1937
_CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected
1939
_CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected
1940
_CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFFh) not code-protected
1942
_CP4_ON_5L EQU H'EF' ; Block 4 (010000-013FFFh) code-protected
1943
_CP4_OFF_5L EQU H'FF' ; Block 4 (010000-013FFFh) not code-protected
1945
_CP5_ON_5L EQU H'DF' ; Block 5 (014000-017FFFh) code-protected
1946
_CP5_OFF_5L EQU H'FF' ; Block 5 (014000-017FFFh) not code-protected
1948
;----- CONFIG5H Options --------------------------------------------------
1949
_CPB_ON_5H EQU H'BF' ; Boot Block (000000-0007FFh) code-protected
1950
_CPB_OFF_5H EQU H'FF' ; Boot Block (000000-0007FFh) not code-protected
1952
_CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected
1953
_CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected
1955
;----- CONFIG6L Options --------------------------------------------------
1956
_WRT0_ON_6L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) write-protected
1957
_WRT0_OFF_6L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not write-protected
1959
_WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected
1960
_WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected
1962
_WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected
1963
_WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected
1965
_WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected
1966
_WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected
1968
_WRT4_ON_6L EQU H'EF' ; Block 4 (010000-013FFFh) write-protected
1969
_WRT4_OFF_6L EQU H'FF' ; Block 4 (010000-013FFFh) not write-protected
1971
_WRT5_ON_6L EQU H'DF' ; Block 5 (014000-017FFFh) write-protected
1972
_WRT5_OFF_6L EQU H'FF' ; Block 5 (014000-017FFFh) not write-protected
1974
;----- CONFIG6H Options --------------------------------------------------
1975
_WRTB_ON_6H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected
1976
_WRTB_OFF_6H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected
1978
_WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected
1979
_WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected
1981
_WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected
1982
_WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected
1984
;----- CONFIG7L Options --------------------------------------------------
1985
_EBTR0_ON_7L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks
1986
_EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks
1988
_EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks
1989
_EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
1991
_EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks
1992
_EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
1994
_EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks
1995
_EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
1997
_EBTR4_ON_7L EQU H'EF' ; Block 4 (010000-013FFFh) protected from table reads executed in other blocks
1998
_EBTR4_OFF_7L EQU H'FF' ; Block 4 (010000-013FFFh) not protected from table reads executed in other blocks
2000
_EBTR5_ON_7L EQU H'DF' ; Block 5 (014000-017FFFh) protected from table reads executed in other blocks
2001
_EBTR5_OFF_7L EQU H'FF' ; Block 5 (014000-017FFFh) not protected from table reads executed in other blocks
2003
;----- CONFIG7H Options --------------------------------------------------
2004
_EBTRB_ON_7H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks
2005
_EBTRB_OFF_7H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks
2008
_DEVID1 EQU H'3FFFFE'
2009
_DEVID2 EQU H'3FFFFF'
2011
_IDLOC0 EQU H'200000'
2012
_IDLOC1 EQU H'200001'
2013
_IDLOC2 EQU H'200002'
2014
_IDLOC3 EQU H'200003'
2015
_IDLOC4 EQU H'200004'
2016
_IDLOC5 EQU H'200005'
2017
_IDLOC6 EQU H'200006'
2018
_IDLOC7 EQU H'200007'