3
3
;==========================================================================
4
; $Id: p18f86j50.inc 448 2006-08-19 02:52:41Z craigfranklin $
5
4
; MPASM PIC18F86J50 processor include
7
; (c) Copyright 1999-2006 Microchip Technology, All rights reserved
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; (c) Copyright 1999-2007 Microchip Technology, All rights reserved
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7
;==========================================================================
333
;----- PMPENL Bits -----------------------------------------------------
344
;----- PMPENH Bits -----------------------------------------------------
355
;----- PMPMODEL Bits -----------------------------------------------------
337
;----- PMEL Bits -----------------------------------------------------
348
;----- PMEH Bits -----------------------------------------------------
359
;----- PMMODEL Bits -----------------------------------------------------
356
360
WAITE0 EQU H'0000'
357
361
WAITE1 EQU H'0001'
358
362
WAITM0 EQU H'0002'
617
620
PPBRST EQU H'0006'
620
;----- PMPADDRH Bits -----------------------------------------------------
623
;----- PMADDRH Bits -----------------------------------------------------
628
;----- CMSTAT Bits -----------------------------------------------------
625
633
;----- CMSTATUS Bits -----------------------------------------------------
626
634
COUT1 EQU H'0000'
627
635
COUT2 EQU H'0001'
2096
2256
; CP0 = OFF Program memory is not code-protected
2098
2258
; CPU System Clock Postscaler:
2099
; CPUDIV = OSC1_PLL2 [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2]
2100
; CPUDIV = OSC2_PLL3 [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3]
2101
; CPUDIV = OSC3_PLL4 [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4]
2102
; CPUDIV = OSC4_PLL6 [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6]
2259
; CPUDIV = OSC4_PLL6 [CPU System clock/6]
2260
; CPUDIV = OSC3_PLL3 [CPU System clock/3]
2261
; CPUDIV = OSC2_PLL2 [CPU System clock/2]
2262
; CPUDIV = OSC1 [No CPU System clock divide]
2104
2264
; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit:
2105
2265
; IESO = OFF Two-Speed Start-up disabled
2110
2270
; FCMEN = ON Fail-Safe Clock Monitor enabled
2112
2272
; Oscillator Selection bits:
2113
; FOSC = INTOSCIO Internal oscillator, port function on RA6 and RA7
2114
; FOSC = INTOSC Internal oscillator, CLKOUT on RA6 and port function on RA7
2115
; FOSC = INTOSCPLLIO_HSINTOSC with PLL enabled, port function on RA6 and RA7, HS used by USB
2116
; FOSC = INTOSCPLL_HS INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7, HS used by USB
2273
; FOSC = INTOSC Internal oscillator, port function on RA6 and RA7
2274
; FOSC = INTOSCO Internal oscillator, CLKOUT on RA6 and port function on RA7
2275
; FOSC = INTOSCPLL INTOSC with PLL enabled, port function on RA6 and RA7, INTOSCPLL used by USB
2276
; FOSC = INTOSCPLLO INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7, INTOSCPLL used by USB
2117
2277
; FOSC = HS HS oscillator, HS used by USB
2118
; FOSC = HSPLL_HS HS oscillator, PLL enabled, HS used by USB
2278
; FOSC = HSPLL HS oscillator, PLL enabled, HSPLL used by USB
2119
2279
; FOSC = EC EC Oscillator with clock out on RA6, EC used by USB
2120
; FOSC = ECPLL_EC EC Oscillator with PLL , CLKOUT on RA6, EC used by USB
2280
; FOSC = ECPLL EC Oscillator with PLL , CLKOUT on RA6, ECPLL used by USB
2122
2282
; Watchdog Timer Postscaler Select bits:
2123
2283
; WDTPS = 1 1:1
2155
2315
; EASHFT = OFF Address shifting disabled, address on external bus reflects the PC value
2156
2316
; EASHFT = ON Address shifting enabled, address on external bus is offset to start at 000000h
2158
; MSSP address select:
2159
; MSSPSEL = ALTERNATE 5 Bit address mode
2160
; MSSPSEL = MSSPPADDRX 7 Bit address mode
2318
; MSSP Address Mask:
2319
; MSSPMSK = MSK5 5 Bit address masking
2320
; MSSPMSK = MSK7 7 Bit address masking
2162
2322
; PMP pin select:
2163
2323
; PMPMX = ALTERNATE PMP port pins not connected to EMB