3
;==========================================================================
4
; MPASM PIC18LF14K22 processor include
6
; (c) Copyright 1999-2008 Microchip Technology, All rights reserved
7
;==========================================================================
11
;==========================================================================
12
; This header file defines configurations, registers, and other useful
13
; bits of information for the PIC18LF14K22 microcontroller. These names
14
; are taken to match the data sheets as closely as possible.
16
; Note that the processor must be selected before this file is included.
17
; The processor may be selected the following ways:
19
; 1. Command line switch:
20
; C:\MPASM MYFILE.ASM /PIC18LF14K22
21
; 2. LIST directive in the source file
23
; 3. Processor Type entry in the MPASM full-screen interface
24
; 4. Setting the processor in the MPLAB Project Dialog
25
;==========================================================================
27
;==========================================================================
31
;==========================================================================
33
MESSG "Processor-header file mismatch. Verify selected processor."
36
;==========================================================================
37
; 18xxxx Family EQUates
38
;==========================================================================
49
;==========================================================================
51
;==========================================================================
52
; 16Cxxx/17Cxxx Substitutions
53
;==========================================================================
54
#define DDRA TRISA ; PIC17Cxxx SFR substitution
55
#define DDRB TRISB ; PIC17Cxxx SFR substitution
56
#define DDRC TRISC ; PIC17Cxxx SFR substitution
57
#define DDRD TRISD ; PIC17Cxxx SFR substitution
58
#define DDRE TRISE ; PIC17Cxxx SFR substitution
60
;==========================================================================
62
; Register Definitions
64
;==========================================================================
66
;----- Register Files -----------------------------------------------------
195
;----- SRCON0 Bits -----------------------------------------------------
206
;----- SRCON1 Bits -----------------------------------------------------
217
;----- CM2CON0 Bits -----------------------------------------------------
228
;----- CM2CON1 Bits -----------------------------------------------------
239
;----- CM1CON0 Bits -----------------------------------------------------
250
;----- SSPMSK Bits -----------------------------------------------------
261
;----- APFCON Bits -----------------------------------------------------
268
;----- SLRCON Bits -----------------------------------------------------
274
;----- WPUA Bits -----------------------------------------------------
283
;----- WPUB Bits -----------------------------------------------------
290
;----- IOCA Bits -----------------------------------------------------
299
;----- IOCB Bits -----------------------------------------------------
306
;----- ANSEL Bits -----------------------------------------------------
317
;----- ANSELH Bits -----------------------------------------------------
324
;----- PORTA Bits -----------------------------------------------------
344
;----- PORTB Bits -----------------------------------------------------
356
; DT is a reserved word
365
;----- PORTC Bits -----------------------------------------------------
413
;----- LATA Bits -----------------------------------------------------
421
;----- LATB Bits -----------------------------------------------------
428
;----- LATC Bits -----------------------------------------------------
439
;----- DDRA Bits -----------------------------------------------------
447
;----- TRISA Bits -----------------------------------------------------
455
;----- DDRB Bits -----------------------------------------------------
462
;----- TRISB Bits -----------------------------------------------------
469
;----- DDRC Bits -----------------------------------------------------
480
;----- TRISC Bits -----------------------------------------------------
491
;----- OSCTUNE Bits -----------------------------------------------------
502
;----- PIE1 Bits -----------------------------------------------------
512
;----- PIR1 Bits -----------------------------------------------------
522
;----- IPR1 Bits -----------------------------------------------------
532
;----- PIE2 Bits -----------------------------------------------------
541
;----- PIR2 Bits -----------------------------------------------------
550
;----- IPR2 Bits -----------------------------------------------------
559
;----- EECON1 Bits -----------------------------------------------------
569
;----- EEADR Bits -----------------------------------------------------
580
;----- EEADRH Bits -----------------------------------------------------
585
;----- RCSTA Bits -----------------------------------------------------
598
;----- TXSTA Bits -----------------------------------------------------
609
;----- T3CON Bits -----------------------------------------------------
618
NOT_T3SYNC EQU H'0002'
621
;----- ECCP1AS Bits -----------------------------------------------------
632
;----- PWM1CON Bits -----------------------------------------------------
643
;----- BAUDCON Bits -----------------------------------------------------
655
;----- BAUDCTL Bits -----------------------------------------------------
667
;----- PSTRCON Bits -----------------------------------------------------
675
;----- VREFCON0 Bits -----------------------------------------------------
684
;----- VREFCON1 Bits -----------------------------------------------------
693
;----- VREFCON2 Bits -----------------------------------------------------
701
;----- CCP1CON Bits -----------------------------------------------------
712
;----- ADCON2 Bits -----------------------------------------------------
722
;----- ADCON1 Bits -----------------------------------------------------
729
;----- ADCON0 Bits -----------------------------------------------------
744
;----- SSPCON2 Bits -----------------------------------------------------
755
;----- SSPCON1 Bits -----------------------------------------------------
766
;----- SSPSTAT Bits -----------------------------------------------------
783
NOT_WRITE EQU H'0002'
784
NOT_ADDRESS EQU H'0005'
787
;----- T2CON Bits -----------------------------------------------------
797
;----- T1CON Bits -----------------------------------------------------
807
NOT_T1SYNC EQU H'0002'
810
;----- RCON Bits -----------------------------------------------------
826
;----- WDTCON Bits -----------------------------------------------------
832
;----- OSCCON2 Bits -----------------------------------------------------
838
;----- OSCCON Bits -----------------------------------------------------
849
;----- T0CON Bits -----------------------------------------------------
860
;----- STATUS Bits -----------------------------------------------------
868
;----- INTCON3 Bits -----------------------------------------------------
884
;----- INTCON2 Bits -----------------------------------------------------
892
NOT_RABPU EQU H'0007'
895
;----- INTCON Bits -----------------------------------------------------
913
;----- STKPTR Bits -----------------------------------------------------
926
;==========================================================================
930
;==========================================================================
932
__BADRAM H'0200'-H'0F3F'
935
__BADRAM H'0F70'-H'0F74'
936
__BADRAM H'0F7B'-H'0F7D'
937
__BADRAM H'0F83'-H'0F88'
938
__BADRAM H'0F8C'-H'0F91'
939
__BADRAM H'0F95'-H'0F9A'
941
__BADRAM H'0FA3'-H'0FA5'
942
__BADRAM H'0FB4'-H'0FB5'
945
;==========================================================================
947
; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
948
; superseded by the CONFIG directive. The following settings
949
; are available for this device.
951
; Oscillator Selection bits:
952
; FOSC = LP LP oscillator
953
; FOSC = XT XT oscillator
954
; FOSC = HS HS oscillator
955
; FOSC = ERCCLKOUT External RC oscillator, CLKOUT function on OSC2
956
; FOSC = ECCLKOUTH EC, CLKOUT function on OSC2 (high)
957
; FOSC = ECH EC (high)
958
; FOSC = ERC External RC oscillator
959
; FOSC = IRC Internal RC oscillator
960
; FOSC = IRCCLKOUT Internal RC oscillator, CLKOUT function on OSC2
961
; FOSC = ECCLKOUTM EC, CLKOUT function on OSC2 (medium)
962
; FOSC = ECM EC (medium)
963
; FOSC = ECCLKOUTL EC, CLKOUT function on OSC2 (low)
964
; FOSC = ECL EC (low)
966
; 4 X PLL Enable bit:
967
; PLLEN = OFF PLL is under software control
968
; PLLEN = ON Oscillator multiplied by 4
970
; Primary Clock Enable Bit:
971
; PCLKEN = OFF Primary clock is under software control
972
; PCLKEN = ON Primary clock enabled
974
; Fail-Safe Clock Monitor Enable bit:
975
; FCMEN = OFF Fail-Safe Clock Monitor disabled
976
; FCMEN = ON Fail-Safe Clock Monitor enabled
978
; Internal/External Oscillator Switchover bit:
979
; IESO = OFF Oscillator Switchover mode disabled
980
; IESO = ON Oscillator Switchover mode enabled
982
; Power-up Timer Enable bit:
983
; PWRTEN = ON PWRT enabled
984
; PWRTEN = OFF PWRT disabled
986
; Brown-out Reset Enable bits:
987
; BOREN = OFF Brown-out Reset disabled in hardware and software
988
; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)
989
; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
990
; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)
993
; BORV = 30 VBOR set to 3.0 V nominal
994
; BORV = 27 VBOR set to 2.7 V nominal
995
; BORV = 22 VBOR set to 2.2 V nominal
996
; BORV = 19 VBOR set to 1.9 V nominal
998
; Watchdog Timer Enable bit:
999
; WDTEN = OFF WDT is controlled by SWDTEN bit of the WDTCON register
1000
; WDTEN = ON WDT is always enabled. SWDTEN bit has no effect.
1002
; Watchdog Timer Postscale Select bits:
1013
; WDTPS = 1024 1:1024
1014
; WDTPS = 2048 1:2048
1015
; WDTPS = 4096 1:4096
1016
; WDTPS = 8192 1:8192
1017
; WDTPS = 16384 1:16384
1018
; WDTPS = 32768 1:32768
1020
; MCLR Pin Enable bit:
1021
; MCLRE = OFF RE3 input pin enabled; MCLR disabled
1022
; MCLRE = ON MCLR pin enabled, RE3 input pin disabled
1024
; HFINTOSC Fast Start-up bit:
1025
; HFOFST = OFF The system clock is held off until the HFINTOSC is stable.
1026
; HFOFST = ON HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.
1028
; Stack Full/Underflow Reset Enable bit:
1029
; STVREN = OFF Stack full/underflow will not cause Reset
1030
; STVREN = ON Stack full/underflow will cause Reset
1032
; Single-Supply ICSP Enable bit:
1033
; LVP = OFF Single-Supply ICSP disabled
1034
; LVP = ON Single-Supply ICSP enabled
1036
; Boot Block Size Select Bit:
1037
; BBSIZ = OFF 1kW boot block size
1038
; BBSIZ = ON 2kW boot block size
1040
; Extended Instruction Set Enable bit:
1041
; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
1042
; XINST = ON Instruction set extension and Indexed Addressing mode enabled
1044
; Code Protection bit:
1045
; CP0 = ON Block 0 code-protected
1046
; CP0 = OFF Block 0 not code-protected
1048
; Code Protection bit:
1049
; CP1 = ON Block 1 code-protected
1050
; CP1 = OFF Block 1 not code-protected
1052
; Boot Block Code Protection bit:
1053
; CPB = ON Boot block code-protected
1054
; CPB = OFF Boot block not code-protected
1056
; Data EEPROM Code Protection bit:
1057
; CPD = ON Data EEPROM code-protected
1058
; CPD = OFF Data EEPROM not code-protected
1060
; Write Protection bit:
1061
; WRT0 = ON Block 0 write-protected
1062
; WRT0 = OFF Block 0 not write-protected
1064
; Write Protection bit:
1065
; WRT1 = ON Block 1 write-protected
1066
; WRT1 = OFF Block 1 not write-protected
1068
; Boot Block Write Protection bit:
1069
; WRTB = ON Boot block write-protected
1070
; WRTB = OFF Boot block not write-protected
1072
; Configuration Register Write Protection bit:
1073
; WRTC = ON Configuration registers write-protected
1074
; WRTC = OFF Configuration registers not write-protected
1076
; Data EEPROM Write Protection bit:
1077
; WRTD = ON Data EEPROM write-protected
1078
; WRTD = OFF Data EEPROM not write-protected
1080
; Table Read Protection bit:
1081
; EBTR0 = ON Block 0 protected from table reads executed in other blocks
1082
; EBTR0 = OFF Block 0 not protected from table reads executed in other blocks
1084
; Table Read Protection bit:
1085
; EBTR1 = ON Block 1 protected from table reads executed in other blocks
1086
; EBTR1 = OFF Block 1 not protected from table reads executed in other blocks
1088
; Boot Block Table Read Protection bit:
1089
; EBTRB = ON Boot block protected from table reads executed in other blocks
1090
; EBTRB = OFF Boot block not protected from table reads executed in other blocks
1092
;==========================================================================
1093
;==========================================================================
1095
; Configuration Bits
1110
;==========================================================================
1112
; The following is an assignment of address values for all of the
1113
; configuration registers for the purpose of table reads
1114
_CONFIG1H EQU H'300001'
1115
_CONFIG2L EQU H'300002'
1116
_CONFIG2H EQU H'300003'
1117
_CONFIG3H EQU H'300005'
1118
_CONFIG4L EQU H'300006'
1119
_CONFIG5L EQU H'300008'
1120
_CONFIG5H EQU H'300009'
1121
_CONFIG6L EQU H'30000A'
1122
_CONFIG6H EQU H'30000B'
1123
_CONFIG7L EQU H'30000C'
1124
_CONFIG7H EQU H'30000D'
1126
;----- CONFIG1H Options --------------------------------------------------
1127
_FOSC_LP_1H EQU H'F0' ; LP oscillator
1128
_FOSC_XT_1H EQU H'F1' ; XT oscillator
1129
_FOSC_HS_1H EQU H'F2' ; HS oscillator
1130
_FOSC_ERCCLKOUT_1H EQU H'F3' ; External RC oscillator, CLKOUT function on OSC2
1131
_FOSC_ECCLKOUTH_1H EQU H'F4' ; EC, CLKOUT function on OSC2 (high)
1132
_FOSC_ECH_1H EQU H'F5' ; EC (high)
1133
_FOSC_ERC_1H EQU H'F7' ; External RC oscillator
1134
_FOSC_IRC_1H EQU H'F8' ; Internal RC oscillator
1135
_FOSC_IRCCLKOUT_1H EQU H'F9' ; Internal RC oscillator, CLKOUT function on OSC2
1136
_FOSC_ECCLKOUTM_1H EQU H'FA' ; EC, CLKOUT function on OSC2 (medium)
1137
_FOSC_ECM_1H EQU H'FB' ; EC (medium)
1138
_FOSC_ECCLKOUTL_1H EQU H'FC' ; EC, CLKOUT function on OSC2 (low)
1139
_FOSC_ECL_1H EQU H'FD' ; EC (low)
1141
_PLLEN_OFF_1H EQU H'EF' ; PLL is under software control
1142
_PLLEN_ON_1H EQU H'FF' ; Oscillator multiplied by 4
1144
_PCLKEN_OFF_1H EQU H'DF' ; Primary clock is under software control
1145
_PCLKEN_ON_1H EQU H'FF' ; Primary clock enabled
1147
_FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled
1148
_FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled
1150
_IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled
1151
_IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled
1153
;----- CONFIG2L Options --------------------------------------------------
1154
_PWRTEN_ON_2L EQU H'FE' ; PWRT enabled
1155
_PWRTEN_OFF_2L EQU H'FF' ; PWRT disabled
1157
_BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software
1158
_BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled)
1159
_BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
1160
_BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
1162
_BORV_30_2L EQU H'E7' ; VBOR set to 3.0 V nominal
1163
_BORV_27_2L EQU H'EF' ; VBOR set to 2.7 V nominal
1164
_BORV_22_2L EQU H'F7' ; VBOR set to 2.2 V nominal
1165
_BORV_19_2L EQU H'FF' ; VBOR set to 1.9 V nominal
1167
;----- CONFIG2H Options --------------------------------------------------
1168
_WDTEN_OFF_2H EQU H'FE' ; WDT is controlled by SWDTEN bit of the WDTCON register
1169
_WDTEN_ON_2H EQU H'FF' ; WDT is always enabled. SWDTEN bit has no effect.
1171
_WDTPS_1_2H EQU H'E1' ; 1:1
1172
_WDTPS_2_2H EQU H'E3' ; 1:2
1173
_WDTPS_4_2H EQU H'E5' ; 1:4
1174
_WDTPS_8_2H EQU H'E7' ; 1:8
1175
_WDTPS_16_2H EQU H'E9' ; 1:16
1176
_WDTPS_32_2H EQU H'EB' ; 1:32
1177
_WDTPS_64_2H EQU H'ED' ; 1:64
1178
_WDTPS_128_2H EQU H'EF' ; 1:128
1179
_WDTPS_256_2H EQU H'F1' ; 1:256
1180
_WDTPS_512_2H EQU H'F3' ; 1:512
1181
_WDTPS_1024_2H EQU H'F5' ; 1:1024
1182
_WDTPS_2048_2H EQU H'F7' ; 1:2048
1183
_WDTPS_4096_2H EQU H'F9' ; 1:4096
1184
_WDTPS_8192_2H EQU H'FB' ; 1:8192
1185
_WDTPS_16384_2H EQU H'FD' ; 1:16384
1186
_WDTPS_32768_2H EQU H'FF' ; 1:32768
1188
;----- CONFIG3H Options --------------------------------------------------
1189
_MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled
1190
_MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RE3 input pin disabled
1192
_HFOFST_OFF_3H EQU H'F7' ; The system clock is held off until the HFINTOSC is stable.
1193
_HFOFST_ON_3H EQU H'FF' ; HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.
1195
;----- CONFIG4L Options --------------------------------------------------
1196
_STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset
1197
_STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset
1199
_LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled
1200
_LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled
1202
_BBSIZ_OFF_4L EQU H'F7' ; 1kW boot block size
1203
_BBSIZ_ON_4L EQU H'FF' ; 2kW boot block size
1205
_XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
1206
_XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled
1208
;----- CONFIG5L Options --------------------------------------------------
1209
_CP0_ON_5L EQU H'FE' ; Block 0 code-protected
1210
_CP0_OFF_5L EQU H'FF' ; Block 0 not code-protected
1212
_CP1_ON_5L EQU H'FD' ; Block 1 code-protected
1213
_CP1_OFF_5L EQU H'FF' ; Block 1 not code-protected
1215
;----- CONFIG5H Options --------------------------------------------------
1216
_CPB_ON_5H EQU H'BF' ; Boot block code-protected
1217
_CPB_OFF_5H EQU H'FF' ; Boot block not code-protected
1219
_CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected
1220
_CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected
1222
;----- CONFIG6L Options --------------------------------------------------
1223
_WRT0_ON_6L EQU H'FE' ; Block 0 write-protected
1224
_WRT0_OFF_6L EQU H'FF' ; Block 0 not write-protected
1226
_WRT1_ON_6L EQU H'FD' ; Block 1 write-protected
1227
_WRT1_OFF_6L EQU H'FF' ; Block 1 not write-protected
1229
;----- CONFIG6H Options --------------------------------------------------
1230
_WRTB_ON_6H EQU H'BF' ; Boot block write-protected
1231
_WRTB_OFF_6H EQU H'FF' ; Boot block not write-protected
1233
_WRTC_ON_6H EQU H'DF' ; Configuration registers write-protected
1234
_WRTC_OFF_6H EQU H'FF' ; Configuration registers not write-protected
1236
_WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected
1237
_WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected
1239
;----- CONFIG7L Options --------------------------------------------------
1240
_EBTR0_ON_7L EQU H'FE' ; Block 0 protected from table reads executed in other blocks
1241
_EBTR0_OFF_7L EQU H'FF' ; Block 0 not protected from table reads executed in other blocks
1243
_EBTR1_ON_7L EQU H'FD' ; Block 1 protected from table reads executed in other blocks
1244
_EBTR1_OFF_7L EQU H'FF' ; Block 1 not protected from table reads executed in other blocks
1246
;----- CONFIG7H Options --------------------------------------------------
1247
_EBTRB_ON_7H EQU H'BF' ; Boot block protected from table reads executed in other blocks
1248
_EBTRB_OFF_7H EQU H'FF' ; Boot block not protected from table reads executed in other blocks
1251
_DEVID1 EQU H'3FFFFE'
1252
_DEVID2 EQU H'3FFFFF'
1254
_IDLOC0 EQU H'200000'
1255
_IDLOC1 EQU H'200001'
1256
_IDLOC2 EQU H'200002'
1257
_IDLOC3 EQU H'200003'
1258
_IDLOC4 EQU H'200004'
1259
_IDLOC5 EQU H'200005'
1260
_IDLOC6 EQU H'200006'
1261
_IDLOC7 EQU H'200007'