~ubuntu-branches/ubuntu/quantal/mesa/quantal

« back to all changes in this revision

Viewing changes to src/gallium/drivers/i915/i915_fpc.h

  • Committer: Package Import Robot
  • Author(s): Timo Aaltonen
  • Date: 2012-08-23 15:37:30 UTC
  • mfrom: (1.7.6)
  • Revision ID: package-import@ubuntu.com-20120823153730-c499sefj7btu4386
Tags: 9.0~git20120821.c1114c61-0ubuntu1
* Merge from unreleased debian git.
  - Includes support for ATI Trinity PCI IDs (LP: #1009089)
* rules, control, libgl1-mesa-swx11*: Remove swx11 support.
* Refresh patches:
  - drop 115_llvm_dynamic_linking.diff,
    117_nullptr_check_in_query_version.patch, and
    118_glsl_initialize_samplers.patch, all upstream
  - disable 116_use_shared_galliumcore.diff until it's reviewed and
    reworked to apply
* not-installed, libegl1-mesa-drivers-install.linux.in: Updated to
  match the single-pass build.
* libgl1-mesa-dri.*install.in: Drop libglsl.so, it's included in
  libdricore.so now.
* rules: Don't disable GLU on the common flags, we need to build it
  on the dri target.
* libglu*install.in: Fix the source file paths to match the build target.
  Drop the static lib from -dev since only shared libs get built.
* libgl1-mesa-dev.install.in: Fix the source file paths to match the
  build target.
* libgl1-mesa-dri.install.linux.in: Don't try to install libgallium.so,
  which isn't built yet.
* rules: Enable llvmpipe on armhf to see if it works or not.
* rules: Remove bin/install-sh on clean, and don't create a symlink for
  it.
* control: Add Pre-Depends on dpkg-dev due to the binaries using xz
  compression.

Show diffs side-by-side

added added

removed removed

Lines of Context:
151
151
}
152
152
 
153
153
 
 
154
#define A0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT)
 
155
#define D0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT)
 
156
#define T0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT)
 
157
#define A0_SRC0( reg ) (((reg)&UREG_MASK)>>UREG_A0_SRC0_SHIFT_LEFT)
 
158
#define A1_SRC0( reg ) (((reg)&UREG_MASK)<<UREG_A1_SRC0_SHIFT_RIGHT)
 
159
#define A1_SRC1( reg ) (((reg)&UREG_MASK)>>UREG_A1_SRC1_SHIFT_LEFT)
 
160
#define A2_SRC1( reg ) (((reg)&UREG_MASK)<<UREG_A2_SRC1_SHIFT_RIGHT)
 
161
#define A2_SRC2( reg ) (((reg)&UREG_MASK)>>UREG_A2_SRC2_SHIFT_LEFT)
 
162
 
 
163
/* These are special, and don't have swizzle/negate bits.
 
164
 */
 
165
#define T0_SAMPLER( reg )     (GET_UREG_NR(reg)<<T0_SAMPLER_NR_SHIFT)
 
166
#define T1_ADDRESS_REG( reg ) ((GET_UREG_NR(reg)<<T1_ADDRESS_REG_NR_SHIFT) | \
 
167
                               (GET_UREG_TYPE(reg)<<T1_ADDRESS_REG_TYPE_SHIFT))
 
168
 
 
169
 
 
170
/* Macros for translating UREG's into the various register fields used
 
171
 * by the I915 programmable unit.
 
172
 */
 
173
#define UREG_A0_DEST_SHIFT_LEFT  (UREG_TYPE_SHIFT - A0_DEST_TYPE_SHIFT)
 
174
#define UREG_A0_SRC0_SHIFT_LEFT  (UREG_TYPE_SHIFT - A0_SRC0_TYPE_SHIFT)
 
175
#define UREG_A1_SRC0_SHIFT_RIGHT (A1_SRC0_CHANNEL_W_SHIFT - UREG_CHANNEL_W_SHIFT)
 
176
#define UREG_A1_SRC1_SHIFT_LEFT  (UREG_TYPE_SHIFT - A1_SRC1_TYPE_SHIFT)
 
177
#define UREG_A2_SRC1_SHIFT_RIGHT (A2_SRC1_CHANNEL_W_SHIFT - UREG_CHANNEL_W_SHIFT)
 
178
#define UREG_A2_SRC2_SHIFT_LEFT  (UREG_TYPE_SHIFT - A2_SRC2_TYPE_SHIFT)
 
179
 
 
180
#define UREG_MASK         0xffffff00
 
181
#define UREG_TYPE_NR_MASK ((REG_TYPE_MASK << UREG_TYPE_SHIFT) | \
 
182
                           (REG_NR_MASK << UREG_NR_SHIFT))
 
183
 
 
184
 
 
185
 
154
186
 
155
187
/***********************************************************************
156
188
 * Public interface for the compiler