254
262
} CpuidFieldSupported;
257
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3, [FUNC] */
265
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */
258
266
#define CPUID_FIELD_DATA_LEVEL_0 \
259
FIELDDEF( 0, EAX, COMMON, 0, 32, NUMLEVELS, ANY, FALSE) \
260
FIELDDEF( 0, EBX, COMMON, 0, 32, VENDOR1, YES, TRUE) \
261
FIELDDEF( 0, ECX, COMMON, 0, 32, VENDOR3, YES, TRUE) \
262
FIELDDEF( 0, EDX, COMMON, 0, 32, VENDOR2, YES, TRUE)
267
FIELD( 0, EAX, COMMON, 0, 32, NUMLEVELS, ANY, FALSE) \
268
FIELD( 0, EBX, COMMON, 0, 32, VENDOR1, YES, TRUE) \
269
FIELD( 0, ECX, COMMON, 0, 32, VENDOR3, YES, TRUE) \
270
FIELD( 0, EDX, COMMON, 0, 32, VENDOR2, YES, TRUE)
264
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3, [FUNC] */
272
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */
265
273
#define CPUID_FIELD_DATA_LEVEL_1 \
266
FIELDDEFA( 1, EAX, COMMON, 0, 4, STEPPING, ANY, FALSE, STEPPING) \
267
FIELDDEFA( 1, EAX, COMMON, 4, 4, MODEL, ANY, FALSE, MODEL) \
268
FIELDDEFA( 1, EAX, COMMON, 8, 4, FAMILY, YES, FALSE, FAMILY) \
269
FIELDDEF( 1, EAX, COMMON, 12, 2, TYPE, ANY, FALSE) \
270
FIELDDEFA( 1, EAX, COMMON, 16, 4, EXTMODEL, ANY, FALSE, EXT_MODEL) \
271
FIELDDEFA( 1, EAX, COMMON, 20, 8, EXTFAMILY, YES, FALSE, EXT_FAMILY) \
272
FIELDDEF( 1, EBX, COMMON, 0, 8, BRAND_ID, ANY, FALSE) \
273
FIELDDEF( 1, EBX, COMMON, 8, 8, CLFL_SIZE, ANY, FALSE) \
274
FIELDDEFA( 1, EBX, COMMON, 16, 8, LCPU_COUNT, ANY, FALSE, LCPU_COUNT) \
275
FIELDDEFA( 1, EBX, COMMON, 24, 8, APICID, ANY, FALSE, APICID) \
276
FLAGDEFA( 1, ECX, COMMON, 0, 1, SSE3, YES, TRUE, SSE3) \
277
FLAGDEFA( 1, ECX, INTEL, 1, 1, PCLMULQDQ, YES, TRUE, PCLMULQDQ) \
278
FLAGDEF( 1, ECX, INTEL, 2, 1, NDA2, NO, FALSE) \
279
FLAGDEFA( 1, ECX, COMMON, 3, 1, MWAIT, ANY, FALSE, MWAIT) \
280
FLAGDEFA( 1, ECX, INTEL, 4, 1, DSCPL, NO, FALSE, DSCPL) \
281
FLAGDEFA( 1, ECX, INTEL, 5, 1, VMX, YES, FALSE, VMX) \
282
FLAGDEF( 1, ECX, VIA, 5, 1, VMX, YES, FALSE) \
283
FLAGDEF( 1, ECX, INTEL, 6, 1, SMX, NO, FALSE) \
284
FLAGDEF( 1, ECX, INTEL, 7, 1, EST, NO, FALSE) \
285
FLAGDEF( 1, ECX, INTEL, 8, 1, TM2, NO, FALSE) \
286
FLAGDEFA( 1, ECX, COMMON, 9, 1, SSSE3, YES, TRUE, SSSE3) \
287
FLAGDEF( 1, ECX, INTEL, 10, 1, HTCACHE, NO, FALSE) \
288
FLAGDEFA( 1, ECX, INTEL, 12, 1, FMA, NO, TRUE, FMA) \
289
FLAGDEFA( 1, ECX, COMMON, 13, 1, CMPX16, YES, TRUE, CMPX16) \
290
FLAGDEF( 1, ECX, INTEL, 14, 1, xPPR, NO, FALSE) \
291
FLAGDEF( 1, ECX, INTEL, 15, 1, PERF_MSR, NO, FALSE) \
292
FLAGDEF( 1, ECX, INTEL, 17, 1, PCID, NO, FALSE) \
293
FLAGDEF( 1, ECX, INTEL, 18, 1, DCA, NO, FALSE) \
294
FLAGDEFA( 1, ECX, INTEL, 19, 1, SSE41, YES, TRUE, SSE41) \
295
FLAGDEFA( 1, ECX, INTEL, 20, 1, SSE42, YES, TRUE, SSE42) \
296
FLAGDEF( 1, ECX, INTEL, 21, 1, X2APIC, NO, FALSE) \
297
FLAGDEFA( 1, ECX, INTEL, 22, 1, MOVBE, YES, TRUE, MOVBE) \
298
FLAGDEFA( 1, ECX, COMMON, 23, 1, POPCNT, YES, TRUE, POPCNT) \
299
FLAGDEF( 1, ECX, INTEL, 24, 1, ULE, NO, TRUE) \
300
FLAGDEFA( 1, ECX, INTEL, 25, 1, AES, YES, TRUE, AES) \
301
FLAGDEFA( 1, ECX, INTEL, 26, 1, XSAVE, NO, FALSE, XSAVE) \
302
FLAGDEF( 1, ECX, INTEL, 27, 1, OSXSAVE, NO, TRUE) \
303
FLAGDEFA( 1, ECX, INTEL, 28, 1, AVX, NO, TRUE, AVX) \
304
FLAGDEFA( 1, ECX, COMMON, 31, 1, HYPERVISOR, ANY, FALSE, HYPERVISOR)\
305
FLAGDEFA( 1, EDX, COMMON, 0, 1, FPU, YES, TRUE, FPU) \
306
FLAGDEFA( 1, EDX, COMMON, 1, 1, VME, YES, FALSE, VME) \
307
FLAGDEF( 1, EDX, COMMON, 2, 1, DBGE, YES, FALSE) \
308
FLAGDEF( 1, EDX, COMMON, 3, 1, PGSZE, YES, FALSE) \
309
FLAGDEFA( 1, EDX, COMMON, 4, 1, TSC, YES, TRUE, TSC) \
310
FLAGDEF( 1, EDX, COMMON, 5, 1, MSR, YES, FALSE) \
311
FLAGDEFA( 1, EDX, COMMON, 6, 1, PAE, YES, FALSE, PAE) \
312
FLAGDEF( 1, EDX, COMMON, 7, 1, MCK, YES, FALSE) \
313
FLAGDEF( 1, EDX, COMMON, 8, 1, CPMX, YES, TRUE) \
314
FLAGDEFA( 1, EDX, COMMON, 9, 1, APIC, ANY, FALSE, APIC) \
315
FLAGDEFA( 1, EDX, COMMON, 11, 1, SEP, YES, TRUE, SEP) \
316
FLAGDEFA( 1, EDX, COMMON, 12, 1, MTRR, YES, FALSE, MTRR) \
317
FLAGDEFA( 1, EDX, COMMON, 13, 1, PGE, YES, FALSE, PGE) \
318
FLAGDEFA( 1, EDX, COMMON, 14, 1, MCA, YES, FALSE, MCA) \
319
FLAGDEFA( 1, EDX, COMMON, 15, 1, CMOV, YES, TRUE, CMOV) \
320
FLAGDEFA( 1, EDX, COMMON, 16, 1, PAT, YES, FALSE, PAT) \
321
FLAGDEF( 1, EDX, COMMON, 17, 1, 36PG, YES, FALSE) \
322
FLAGDEF( 1, EDX, INTEL, 18, 1, PSN, YES, FALSE) \
323
FLAGDEFA( 1, EDX, COMMON, 19, 1, CLFL, YES, TRUE, CLFL) \
324
FLAGDEF( 1, EDX, INTEL, 21, 1, DTES, YES, FALSE) \
325
FLAGDEF( 1, EDX, INTEL, 22, 1, ACPI, YES, FALSE) \
326
FLAGDEFA( 1, EDX, COMMON, 23, 1, MMX, YES, TRUE, MMX) \
327
FLAGDEFA( 1, EDX, COMMON, 24, 1, FXSAVE, YES, TRUE, FXSAVE) \
328
FLAGDEFA( 1, EDX, COMMON, 25, 1, SSE, YES, TRUE, SSE) \
329
FLAGDEFA( 1, EDX, COMMON, 26, 1, SSE2, YES, TRUE, SSE2) \
330
FLAGDEF( 1, EDX, INTEL, 27, 1, SS, YES, FALSE) \
331
FLAGDEFA( 1, EDX, COMMON, 28, 1, HT, ANY, FALSE, HT) \
332
FLAGDEF( 1, EDX, INTEL, 29, 1, TM, NO, FALSE) \
333
FLAGDEF( 1, EDX, INTEL, 30, 1, IA64, NO, FALSE) \
334
FLAGDEF( 1, EDX, INTEL, 31, 1, PBE, NO, FALSE)
274
FIELD( 1, EAX, COMMON, 0, 4, STEPPING, ANY, FALSE) \
275
FIELD( 1, EAX, COMMON, 4, 4, MODEL, ANY, FALSE) \
276
FIELD( 1, EAX, COMMON, 8, 4, FAMILY, YES, FALSE) \
277
FIELD( 1, EAX, COMMON, 12, 2, TYPE, ANY, FALSE) \
278
FIELD( 1, EAX, COMMON, 16, 4, EXTENDED_MODEL, ANY, FALSE) \
279
FIELD( 1, EAX, COMMON, 20, 8, EXTENDED_FAMILY, YES, FALSE) \
280
FIELD( 1, EBX, COMMON, 0, 8, BRAND_ID, ANY, FALSE) \
281
FIELD( 1, EBX, COMMON, 8, 8, CLFL_SIZE, ANY, FALSE) \
282
FIELD( 1, EBX, COMMON, 16, 8, LCPU_COUNT, ANY, FALSE) \
283
FIELD( 1, EBX, COMMON, 24, 8, APICID, ANY, FALSE) \
284
FLAG( 1, ECX, COMMON, 0, 1, SSE3, YES, TRUE) \
285
FLAG( 1, ECX, COMMON, 1, 1, PCLMULQDQ, YES, TRUE) \
286
FLAG( 1, ECX, INTEL, 2, 1, DTES64, NO, FALSE) \
287
FLAG( 1, ECX, COMMON, 3, 1, MWAIT, ANY, FALSE) \
288
FLAG( 1, ECX, INTEL, 4, 1, DSCPL, NO, FALSE) \
289
FLAG( 1, ECX, INTEL, 5, 1, VMX, YES, FALSE) \
290
FLAG( 1, ECX, VIA, 5, 1, VIA_VMX, YES, FALSE) \
291
FLAG( 1, ECX, INTEL, 6, 1, SMX, NO, FALSE) \
292
FLAG( 1, ECX, INTEL, 7, 1, EIST, NO, FALSE) \
293
FLAG( 1, ECX, INTEL, 8, 1, TM2, NO, FALSE) \
294
FLAG( 1, ECX, COMMON, 9, 1, SSSE3, YES, TRUE) \
295
FLAG( 1, ECX, INTEL, 10, 1, CNXTID, NO, FALSE) \
296
FLAG( 1, ECX, INTEL, 11, 1, NDA11, NO, FALSE) \
297
FLAG( 1, ECX, COMMON, 12, 1, FMA, YES, TRUE) \
298
FLAG( 1, ECX, COMMON, 13, 1, CMPXCHG16B, YES, TRUE) \
299
FLAG( 1, ECX, INTEL, 14, 1, xTPR, NO, FALSE) \
300
FLAG( 1, ECX, INTEL, 15, 1, PDCM, NO, FALSE) \
301
FLAG( 1, ECX, INTEL, 17, 1, PCID, YES, FALSE) \
302
FLAG( 1, ECX, INTEL, 18, 1, DCA, NO, FALSE) \
303
FLAG( 1, ECX, COMMON, 19, 1, SSE41, YES, TRUE) \
304
FLAG( 1, ECX, COMMON, 20, 1, SSE42, YES, TRUE) \
305
FLAG( 1, ECX, INTEL, 21, 1, x2APIC, NO, FALSE) \
306
FLAG( 1, ECX, INTEL, 22, 1, MOVBE, YES, TRUE) \
307
FLAG( 1, ECX, COMMON, 23, 1, POPCNT, YES, TRUE) \
308
FLAG( 1, ECX, COMMON, 24, 1, TSC_DEADLINE, NO, FALSE) \
309
FLAG( 1, ECX, COMMON, 25, 1, AES, YES, TRUE) \
310
FLAG( 1, ECX, COMMON, 26, 1, XSAVE, YES, FALSE) \
311
FLAG( 1, ECX, COMMON, 27, 1, OSXSAVE, ANY, FALSE) \
312
FLAG( 1, ECX, COMMON, 28, 1, AVX, YES, TRUE) \
313
FLAG( 1, ECX, COMMON, 29, 1, F16, YES, TRUE) \
314
FLAG( 1, ECX, COMMON, 30, 1, RDRAND, YES, TRUE) \
315
FLAG( 1, ECX, COMMON, 31, 1, HYPERVISOR, ANY, FALSE) \
316
FLAG( 1, EDX, COMMON, 0, 1, FPU, YES, TRUE) \
317
FLAG( 1, EDX, COMMON, 1, 1, VME, YES, FALSE) \
318
FLAG( 1, EDX, COMMON, 2, 1, DE, YES, FALSE) \
319
FLAG( 1, EDX, COMMON, 3, 1, PSE, YES, FALSE) \
320
FLAG( 1, EDX, COMMON, 4, 1, TSC, YES, TRUE) \
321
FLAG( 1, EDX, COMMON, 5, 1, MSR, YES, FALSE) \
322
FLAG( 1, EDX, COMMON, 6, 1, PAE, YES, FALSE) \
323
FLAG( 1, EDX, COMMON, 7, 1, MCE, YES, FALSE) \
324
FLAG( 1, EDX, COMMON, 8, 1, CX8, YES, TRUE) \
325
FLAG( 1, EDX, COMMON, 9, 1, APIC, ANY, FALSE) \
326
FLAG( 1, EDX, COMMON, 11, 1, SEP, YES, TRUE) \
327
FLAG( 1, EDX, COMMON, 12, 1, MTRR, YES, FALSE) \
328
FLAG( 1, EDX, COMMON, 13, 1, PGE, YES, FALSE) \
329
FLAG( 1, EDX, COMMON, 14, 1, MCA, YES, FALSE) \
330
FLAG( 1, EDX, COMMON, 15, 1, CMOV, YES, TRUE) \
331
FLAG( 1, EDX, COMMON, 16, 1, PAT, YES, FALSE) \
332
FLAG( 1, EDX, COMMON, 17, 1, PSE36, YES, FALSE) \
333
FLAG( 1, EDX, INTEL, 18, 1, PSN, YES, FALSE) \
334
FLAG( 1, EDX, COMMON, 19, 1, CLFSH, YES, TRUE) \
335
FLAG( 1, EDX, INTEL, 21, 1, DS, YES, FALSE) \
336
FLAG( 1, EDX, INTEL, 22, 1, ACPI, YES, FALSE) \
337
FLAG( 1, EDX, COMMON, 23, 1, MMX, YES, TRUE) \
338
FLAG( 1, EDX, COMMON, 24, 1, FXSR, YES, TRUE) \
339
FLAG( 1, EDX, COMMON, 25, 1, SSE, YES, TRUE) \
340
FLAG( 1, EDX, COMMON, 26, 1, SSE2, YES, TRUE) \
341
FLAG( 1, EDX, INTEL, 27, 1, SS, YES, FALSE) \
342
FLAG( 1, EDX, COMMON, 28, 1, HTT, ANY, FALSE) \
343
FLAG( 1, EDX, INTEL, 29, 1, TM, NO, FALSE) \
344
FLAG( 1, EDX, INTEL, 30, 1, IA64, NO, FALSE) \
345
FLAG( 1, EDX, INTEL, 31, 1, PBE, NO, FALSE)
336
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3, [FUNC] */
347
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */
337
348
#define CPUID_FIELD_DATA_LEVEL_4 \
338
FIELDDEF( 4, EAX, INTEL, 0, 5, CACHE_TYPE, NA, FALSE) \
339
FIELDDEF( 4, EAX, INTEL, 5, 3, CACHE_LEVEL, NA, FALSE) \
340
FLAGDEF( 4, EAX, INTEL, 8, 1, CACHE_SELF_INIT, NA, FALSE) \
341
FLAGDEF( 4, EAX, INTEL, 9, 1, CACHE_FULLY_ASSOC, NA, FALSE) \
342
FIELDDEF( 4, EAX, INTEL, 14, 12, CACHE_NUMHT_SHARING, NA, FALSE) \
343
FIELDDEFA( 4, EAX, INTEL, 26, 6, CORE_COUNT, NA, FALSE, INTEL_CORE_COUNT) \
344
FIELDDEF( 4, EBX, INTEL, 0, 12, CACHE_LINE, NA, FALSE) \
345
FIELDDEF( 4, EBX, INTEL, 12, 10, CACHE_PART, NA, FALSE) \
346
FIELDDEF( 4, EBX, INTEL, 22, 10, CACHE_WAYS, NA, FALSE) \
347
FIELDDEF( 4, ECX, INTEL, 0, 32, CACHE_SETS, NA, FALSE) \
348
FLAGDEF( 4, EDX, INTEL, 0, 1, CACHE_WBINVD_NOT_GUARANTEED, NA, FALSE) \
349
FLAGDEF( 4, EDX, INTEL, 1, 1, CACHE_IS_INCLUSIVE, NA, FALSE)
351
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3, [FUNC] */
352
#define CPUID_FIELD_DATA_LEVEL_5 \
353
FIELDDEFA( 5, EAX, COMMON, 0, 16, MWAIT_MIN_SIZE, NA, FALSE, MWAIT_MIN_SIZE) \
354
FIELDDEFA( 5, EBX, COMMON, 0, 16, MWAIT_MAX_SIZE, NA, FALSE, MWAIT_MAX_SIZE) \
355
FLAGDEF( 5, ECX, COMMON, 0, 1, MWAIT_EXTENSIONS, NA, FALSE) \
356
FLAGDEFA( 5, ECX, COMMON, 1, 1, MWAIT_INTR_BREAK, NA, FALSE, MWAIT_INTR_BREAK) \
357
FIELDDEF( 5, EDX, INTEL, 0, 4, MWAIT_C0_SUBSTATE, NA, FALSE) \
358
FIELDDEF( 5, EDX, INTEL, 4, 4, MWAIT_C1_SUBSTATE, NA, FALSE) \
359
FIELDDEF( 5, EDX, INTEL, 8, 4, MWAIT_C2_SUBSTATE, NA, FALSE) \
360
FIELDDEF( 5, EDX, INTEL, 12, 4, MWAIT_C3_SUBSTATE, NA, FALSE) \
361
FIELDDEF( 5, EDX, INTEL, 16, 4, MWAIT_C4_SUBSTATE, NA, FALSE)
363
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3, [FUNC] */
349
FIELD( 4, EAX, INTEL, 0, 5, LEAF4_CACHE_TYPE, NA, FALSE) \
350
FIELD( 4, EAX, INTEL, 5, 3, LEAF4_CACHE_LEVEL, NA, FALSE) \
351
FLAG( 4, EAX, INTEL, 8, 1, LEAF4_CACHE_SELF_INIT, NA, FALSE) \
352
FLAG( 4, EAX, INTEL, 9, 1, LEAF4_CACHE_FULLY_ASSOC, NA, FALSE) \
353
FIELD( 4, EAX, INTEL, 14, 12, LEAF4_CACHE_NUMHT_SHARING, NA, FALSE) \
354
FIELD( 4, EAX, INTEL, 26, 6, LEAF4_CORE_COUNT, NA, FALSE) \
355
FIELD( 4, EBX, INTEL, 0, 12, LEAF4_CACHE_LINE, NA, FALSE) \
356
FIELD( 4, EBX, INTEL, 12, 10, LEAF4_CACHE_PART, NA, FALSE) \
357
FIELD( 4, EBX, INTEL, 22, 10, LEAF4_CACHE_WAYS, NA, FALSE) \
358
FIELD( 4, ECX, INTEL, 0, 32, LEAF4_CACHE_SETS, NA, FALSE) \
359
FLAG( 4, EDX, INTEL, 0, 1, LEAF4_CACHE_WBINVD_NOT_GUARANTEED, NA, FALSE) \
360
FLAG( 4, EDX, INTEL, 1, 1, LEAF4_CACHE_IS_INCLUSIVE, NA, FALSE)
362
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */
363
#define CPUID_FIELD_DATA_LEVEL_5 \
364
FIELD( 5, EAX, COMMON, 0, 16, MWAIT_MIN_SIZE, NA, FALSE) \
365
FIELD( 5, EBX, COMMON, 0, 16, MWAIT_MAX_SIZE, NA, FALSE) \
366
FLAG( 5, ECX, COMMON, 0, 1, MWAIT_EXTENSIONS, NA, FALSE) \
367
FLAG( 5, ECX, COMMON, 1, 1, MWAIT_INTR_BREAK, NA, FALSE) \
368
FIELD( 5, EDX, INTEL, 0, 4, MWAIT_C0_SUBSTATE, NA, FALSE) \
369
FIELD( 5, EDX, INTEL, 4, 4, MWAIT_C1_SUBSTATE, NA, FALSE) \
370
FIELD( 5, EDX, INTEL, 8, 4, MWAIT_C2_SUBSTATE, NA, FALSE) \
371
FIELD( 5, EDX, INTEL, 12, 4, MWAIT_C3_SUBSTATE, NA, FALSE) \
372
FIELD( 5, EDX, INTEL, 16, 4, MWAIT_C4_SUBSTATE, NA, FALSE)
374
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */
364
375
#define CPUID_FIELD_DATA_LEVEL_6 \
365
FLAGDEF( 6, EAX, INTEL, 0, 1, THERMAL_SENSOR, NA, FALSE) \
366
FLAGDEF( 6, EAX, INTEL, 1, 1, TURBO_MODE, NA, FALSE) \
367
FIELDDEF( 6, EBX, INTEL, 0, 4, NUM_INTR_THRESHOLDS, NA, FALSE) \
368
FLAGDEF( 6, ECX, INTEL, 0, 1, HW_COORD_FEEDBACK, NA, FALSE) \
369
FLAGDEF( 6, ECX, INTEL, 3, 1, ENERGY_PERF_BIAS, NA, FALSE)
371
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3, [FUNC] */
376
FLAG( 6, EAX, INTEL, 0, 1, THERMAL_SENSOR, NA, FALSE) \
377
FLAG( 6, EAX, INTEL, 1, 1, TURBO_MODE, NA, FALSE) \
378
FLAG( 6, EAX, INTEL, 2, 1, APIC_INVARIANT, NA, FALSE) \
379
FIELD( 6, EBX, INTEL, 0, 4, NUM_INTR_THRESHOLDS, NA, FALSE) \
380
FLAG( 6, ECX, INTEL, 0, 1, HW_COORD_FEEDBACK, NA, FALSE) \
381
FLAG( 6, ECX, INTEL, 3, 1, ENERGY_PERF_BIAS, NA, FALSE)
383
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */
384
#define CPUID_FIELD_DATA_LEVEL_7 \
385
FLAG( 7, EBX, INTEL, 0, 1, FSGSBASE, YES, TRUE) \
386
FLAG( 7, EBX, INTEL, 7, 1, SMEP, NO, FALSE) \
387
FLAG( 7, EBX, INTEL, 9, 1, ENFSTRG, YES, TRUE)
389
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */
372
390
#define CPUID_FIELD_DATA_LEVEL_A \
373
FIELDDEFA( A, EAX, INTEL, 0, 8, PMC_VERSION, NA, FALSE, PMC_VERSION) \
374
FIELDDEFA( A, EAX, INTEL, 8, 8, NUM_PMCS, NA, FALSE, NUM_PMCS) \
375
FIELDDEF( A, EAX, INTEL, 16, 8, PMC_BIT_WIDTH, NA, FALSE) \
376
FIELDDEFA( A, EAX, INTEL, 24, 8, PMC_EBX_LENGTH, NA, FALSE, PMC_EBX_LENGTH) \
377
FLAGDEF( A, EBX, INTEL, 0, 1, PMC_CORE_CYCLE, NA, FALSE) \
378
FLAGDEF( A, EBX, INTEL, 1, 1, PMC_INSTR_RETIRED, NA, FALSE) \
379
FLAGDEF( A, EBX, INTEL, 2, 1, PMC_REF_CYCLES, NA, FALSE) \
380
FLAGDEF( A, EBX, INTEL, 3, 1, PMC_LAST_LVL_CREF, NA, FALSE) \
381
FLAGDEF( A, EBX, INTEL, 4, 1, PMC_LAST_LVL_CMISS, NA, FALSE) \
382
FLAGDEF( A, EBX, INTEL, 5, 1, PMC_BR_INST_RETIRED, NA, FALSE) \
383
FLAGDEF( A, EBX, INTEL, 6, 1, PMC_BR_MISS_RETIRED, NA, FALSE) \
384
FIELDDEF( A, EDX, INTEL, 0, 5, PMC_FIXED_NUM, NA, FALSE) \
385
FIELDDEF( A, EDX, INTEL, 5, 8, PMC_FIXED_SIZE, NA, FALSE)
391
FIELD( A, EAX, INTEL, 0, 8, PMC_VERSION, NA, FALSE) \
392
FIELD( A, EAX, INTEL, 8, 8, PMC_NUM_GEN, NA, FALSE) \
393
FIELD( A, EAX, INTEL, 16, 8, PMC_WIDTH_GEN, NA, FALSE) \
394
FIELD( A, EAX, INTEL, 24, 8, PMC_EBX_LENGTH, NA, FALSE) \
395
FLAG( A, EBX, INTEL, 0, 1, PMC_CORE_CYCLES, NA, FALSE) \
396
FLAG( A, EBX, INTEL, 1, 1, PMC_INSTR_RETIRED, NA, FALSE) \
397
FLAG( A, EBX, INTEL, 2, 1, PMC_REF_CYCLES, NA, FALSE) \
398
FLAG( A, EBX, INTEL, 3, 1, PMC_LAST_LVL_CREF, NA, FALSE) \
399
FLAG( A, EBX, INTEL, 4, 1, PMC_LAST_LVL_CMISS, NA, FALSE) \
400
FLAG( A, EBX, INTEL, 5, 1, PMC_BR_INST_RETIRED, NA, FALSE) \
401
FLAG( A, EBX, INTEL, 6, 1, PMC_BR_MISS_RETIRED, NA, FALSE) \
402
FIELD( A, EDX, INTEL, 0, 5, PMC_NUM_FIXED, NA, FALSE) \
403
FIELD( A, EDX, INTEL, 5, 8, PMC_WIDTH_FIXED, NA, FALSE)
387
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3, [FUNC] */
405
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */
388
406
#define CPUID_FIELD_DATA_LEVEL_B \
389
FIELDDEF( B, EAX, INTEL, 0, 5, MASK_WIDTH, NA, FALSE) \
390
FIELDDEF( B, EBX, INTEL, 0, 16, CPUS_SHARING_LEVEL, NA, FALSE) \
391
FIELDDEF( B, ECX, INTEL, 0, 8, LEVEL_NUMBER, NA, FALSE) \
392
FIELDDEF( B, ECX, INTEL, 8, 8, LEVEL_TYPE, NA, FALSE) \
393
FIELDDEF( B, EDX, INTEL, 0, 32, X2APIC_ID, NA, FALSE)
395
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3, [FUNC] */
407
FIELD( B, EAX, INTEL, 0, 5, MASK_WIDTH, NA, FALSE) \
408
FIELD( B, EBX, INTEL, 0, 16, CPUS_SHARING_LEVEL, NA, FALSE) \
409
FIELD( B, ECX, INTEL, 0, 8, LEVEL_NUMBER, NA, FALSE) \
410
FIELD( B, ECX, INTEL, 8, 8, LEVEL_TYPE, NA, FALSE) \
411
FIELD( B, EDX, INTEL, 0, 32, X2APIC_ID, NA, FALSE)
413
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */
414
#define CPUID_FIELD_DATA_LEVEL_D \
415
FLAG( D, EAX, COMMON, 0, 1, XCR0_MASTER_LEGACY_FP, YES, FALSE) \
416
FLAG( D, EAX, COMMON, 1, 1, XCR0_MASTER_SSE, YES, FALSE) \
417
FLAG( D, EAX, COMMON, 2, 1, XCR0_MASTER_YMM_H, YES, FALSE) \
418
FIELD( D, EAX, COMMON, 3, 29, XCR0_MASTER_LOWER, NO, FALSE) \
419
FIELD( D, EBX, COMMON, 0, 32, XSAVE_ENABLED_SIZE, YES, FALSE) \
420
FIELD( D, ECX, COMMON, 0, 32, XSAVE_MAX_SIZE, YES, FALSE) \
421
FIELD( D, EDX, COMMON, 0, 32, XCR0_MASTER_UPPER, NO, FALSE)
423
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */
396
424
#define CPUID_FIELD_DATA_LEVEL_400 \
397
FIELDDEF(400, EAX, COMMON, 0, 32, NUM_HYP_LEVELS, NA, FALSE) \
398
FIELDDEF(400, EBX, COMMON, 0, 32, HYPERVISOR1, NA, FALSE) \
399
FIELDDEF(400, ECX, COMMON, 0, 32, HYPERVISOR2, NA, FALSE) \
400
FIELDDEF(400, EDX, COMMON, 0, 32, HYPERVISOR3, NA, FALSE)
425
FIELD(400, EAX, COMMON, 0, 32, NUM_HYP_LEVELS, NA, FALSE) \
426
FIELD(400, EBX, COMMON, 0, 32, HYPERVISOR1, NA, FALSE) \
427
FIELD(400, ECX, COMMON, 0, 32, HYPERVISOR2, NA, FALSE) \
428
FIELD(400, EDX, COMMON, 0, 32, HYPERVISOR3, NA, FALSE)
402
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3, [FUNC] */
430
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */
403
431
#define CPUID_FIELD_DATA_LEVEL_410 \
404
FIELDDEF(410, EAX, COMMON, 0, 32, TSC_HZ, NA, FALSE) \
405
FIELDDEF(410, EBX, COMMON, 0, 32, ACPIBUS_HZ, NA, FALSE)
432
FIELD(410, EAX, COMMON, 0, 32, TSC_HZ, NA, FALSE) \
433
FIELD(410, EBX, COMMON, 0, 32, ACPIBUS_HZ, NA, FALSE)
407
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3, [FUNC] */
435
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */
408
436
#define CPUID_FIELD_DATA_LEVEL_80 \
409
FIELDDEF( 80, EAX, COMMON, 0, 32, NUM_EXT_LEVELS, NA, FALSE) \
410
FIELDDEF( 80, EBX, AMD, 0, 32, AMD_VENDOR1, NA, FALSE) \
411
FIELDDEF( 80, ECX, AMD, 0, 32, AMD_VENDOR3, NA, FALSE) \
412
FIELDDEF( 80, EDX, AMD, 0, 32, AMD_VENDOR2, NA, FALSE)
437
FIELD( 80, EAX, COMMON, 0, 32, NUM_EXT_LEVELS, NA, FALSE) \
438
FIELD( 80, EBX, AMD, 0, 32, LEAF80_VENDOR1, NA, FALSE) \
439
FIELD( 80, ECX, AMD, 0, 32, LEAF80_VENDOR3, NA, FALSE) \
440
FIELD( 80, EDX, AMD, 0, 32, LEAF80_VENDOR2, NA, FALSE)
414
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3, [FUNC] */
442
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */
415
443
#define CPUID_FIELD_DATA_LEVEL_81 \
416
FIELDDEF( 81, EAX, INTEL, 0, 32, UNKNOWN81EAX, ANY, FALSE) \
417
FIELDDEF( 81, EAX, AMD, 0, 4, STEPPING, ANY, FALSE) \
418
FIELDDEF( 81, EAX, AMD, 4, 4, MODEL, ANY, FALSE) \
419
FIELDDEF( 81, EAX, AMD, 8, 4, FAMILY, ANY, FALSE) \
420
FIELDDEF( 81, EAX, AMD, 12, 2, TYPE, ANY, FALSE) \
421
FIELDDEF( 81, EAX, AMD, 16, 4, EXTMODEL, ANY, FALSE) \
422
FIELDDEF( 81, EAX, AMD, 20, 8, EXTFAMILY, ANY, FALSE) \
423
FIELDDEF( 81, EBX, INTEL, 0, 32, UNKNOWN81EBX, ANY, FALSE) \
424
FIELDDEF( 81, EBX, AMD, 0, 16, BRAND_ID, ANY, FALSE) \
425
FIELDDEF( 81, EBX, AMD, 16, 16, UNDEF, ANY, FALSE) \
426
FLAGDEFA( 81, ECX, COMMON, 0, 1, LAHF, YES, TRUE, LAHF64) \
427
FLAGDEFA( 81, ECX, AMD, 1, 1, CMPLEGACY, NO, FALSE, CMPLEGACY) \
428
FLAGDEFA( 81, ECX, AMD, 2, 1, SVM, YES, FALSE, SVM) \
429
FLAGDEFA( 81, ECX, AMD, 3, 1, EXTAPICSPC, YES, FALSE, EXTAPICSPC) \
430
FLAGDEFA( 81, ECX, AMD, 4, 1, CR8AVAIL, NO, FALSE, CR8AVAIL) \
431
FLAGDEFA( 81, ECX, AMD, 5, 1, ABM, YES, TRUE, ABM) \
432
FLAGDEFA( 81, ECX, AMD, 6, 1, SSE4A, YES, TRUE, SSE4A) \
433
FLAGDEF( 81, ECX, AMD, 7, 1, MISALIGNED_SSE, YES, TRUE) \
434
FLAGDEFA( 81, ECX, AMD, 8, 1, 3DNPREFETCH, YES, TRUE, 3DNPREFETCH) \
435
FLAGDEF( 81, ECX, AMD, 9, 1, OSVW, NO, FALSE) \
436
FLAGDEF( 81, ECX, AMD, 10, 1, IBS, NO, FALSE) \
437
FLAGDEF( 81, ECX, AMD, 11, 1, SSE5, NO, TRUE) \
438
FLAGDEF( 81, ECX, AMD, 12, 1, SKINIT, NO, FALSE) \
439
FLAGDEF( 81, ECX, AMD, 13, 1, WATCHDOG, NO, FALSE) \
440
FLAGDEF( 81, ECX, AMD, 19, 1, NODEID, NO, FALSE) \
441
FLAGDEF( 81, EDX, AMD, 0, 1, FPU, YES, TRUE) \
442
FLAGDEF( 81, EDX, AMD, 1, 1, VME, YES, FALSE) \
443
FLAGDEF( 81, EDX, AMD, 2, 1, DBGE, YES, FALSE) \
444
FLAGDEF( 81, EDX, AMD, 3, 1, PGSZE, YES, FALSE) \
445
FLAGDEF( 81, EDX, AMD, 4, 1, TSC, YES, TRUE) \
446
FLAGDEF( 81, EDX, AMD, 5, 1, MSR, YES, FALSE) \
447
FLAGDEF( 81, EDX, AMD, 6, 1, PAE, YES, FALSE) \
448
FLAGDEF( 81, EDX, AMD, 7, 1, MCK, YES, FALSE) \
449
FLAGDEF( 81, EDX, AMD, 8, 1, CPMX, YES, TRUE) \
450
FLAGDEF( 81, EDX, AMD, 9, 1, APIC, ANY, FALSE) \
451
FLAGDEFA( 81, EDX, COMMON, 11, 1, SYSC, ANY, TRUE, SYSC) \
452
FLAGDEF( 81, EDX, AMD, 12, 1, MTRR, YES, FALSE) \
453
FLAGDEF( 81, EDX, AMD, 13, 1, PGE, YES, FALSE) \
454
FLAGDEF( 81, EDX, AMD, 14, 1, MCA, YES, FALSE) \
455
FLAGDEF( 81, EDX, AMD, 15, 1, CMOV, YES, TRUE) \
456
FLAGDEF( 81, EDX, AMD, 16, 1, PAT, YES, FALSE) \
457
FLAGDEF( 81, EDX, AMD, 17, 1, 36PG, YES, FALSE) \
458
FLAGDEFA( 81, EDX, COMMON, 20, 1, NX, YES, FALSE, NX) \
459
FLAGDEFA( 81, EDX, AMD, 22, 1, MMXEXT, YES, TRUE, MMXEXT) \
460
FLAGDEF( 81, EDX, AMD, 23, 1, MMX, YES, TRUE) \
461
FLAGDEF( 81, EDX, AMD, 24, 1, FXSAVE, YES, TRUE) \
462
FLAGDEFA( 81, EDX, AMD, 25, 1, FFXSR, YES, FALSE, FFXSR) \
463
FLAGDEF( 81, EDX, COMMON, 26, 1, PDPE1GB, NO, FALSE) \
464
FLAGDEFA( 81, EDX, COMMON, 27, 1, RDTSCP, YES, TRUE, RDTSCP) \
465
FLAGDEFA( 81, EDX, COMMON, 29, 1, LM, YES, FALSE, LM) \
466
FLAGDEFA( 81, EDX, AMD, 30, 1, 3DNOWPLUS, YES, TRUE, 3DNOWPLUS) \
467
FLAGDEFA( 81, EDX, AMD, 31, 1, 3DNOW, YES, TRUE, 3DNOW)
444
FIELD( 81, EAX, INTEL, 0, 32, UNKNOWN81EAX, ANY, FALSE) \
445
FIELD( 81, EAX, AMD, 0, 4, LEAF81_STEPPING, ANY, FALSE) \
446
FIELD( 81, EAX, AMD, 4, 4, LEAF81_MODEL, ANY, FALSE) \
447
FIELD( 81, EAX, AMD, 8, 4, LEAF81_FAMILY, ANY, FALSE) \
448
FIELD( 81, EAX, AMD, 12, 2, LEAF81_TYPE, ANY, FALSE) \
449
FIELD( 81, EAX, AMD, 16, 4, LEAF81_EXTENDED_MODEL, ANY, FALSE) \
450
FIELD( 81, EAX, AMD, 20, 8, LEAF81_EXTENDED_FAMILY, ANY, FALSE) \
451
FIELD( 81, EBX, INTEL, 0, 32, UNKNOWN81EBX, ANY, FALSE) \
452
FIELD( 81, EBX, AMD, 0, 16, LEAF81_BRAND_ID, ANY, FALSE) \
453
FIELD( 81, EBX, AMD, 16, 16, UNDEF, ANY, FALSE) \
454
FLAG( 81, ECX, COMMON, 0, 1, LAHF64, YES, TRUE) \
455
FLAG( 81, ECX, AMD, 1, 1, CMPLEGACY, NO, FALSE) \
456
FLAG( 81, ECX, AMD, 2, 1, SVM, YES, FALSE) \
457
FLAG( 81, ECX, AMD, 3, 1, EXTAPICSPC, YES, FALSE) \
458
FLAG( 81, ECX, AMD, 4, 1, CR8AVAIL, NO, FALSE) \
459
FLAG( 81, ECX, AMD, 5, 1, ABM, YES, TRUE) \
460
FLAG( 81, ECX, AMD, 6, 1, SSE4A, YES, TRUE) \
461
FLAG( 81, ECX, AMD, 7, 1, MISALIGNED_SSE, YES, TRUE) \
462
FLAG( 81, ECX, AMD, 8, 1, 3DNPREFETCH, YES, TRUE) \
463
FLAG( 81, ECX, AMD, 9, 1, OSVW, ANY, FALSE) \
464
FLAG( 81, ECX, AMD, 10, 1, IBS, NO, FALSE) \
465
FLAG( 81, ECX, AMD, 11, 1, XOP, YES, TRUE) \
466
FLAG( 81, ECX, AMD, 12, 1, SKINIT, NO, FALSE) \
467
FLAG( 81, ECX, AMD, 13, 1, WATCHDOG, NO, FALSE) \
468
FLAG( 81, ECX, AMD, 15, 1, LWP, NO, FALSE) \
469
FLAG( 81, ECX, AMD, 16, 1, FMA4, YES, TRUE) \
470
FLAG( 81, ECX, AMD, 19, 1, NODEID, NO, FALSE) \
471
FLAG( 81, ECX, AMD, 22, 1, TOPOLOGY, NO, FALSE) \
472
FLAG( 81, EDX, AMD, 0, 1, LEAF81_FPU, YES, TRUE) \
473
FLAG( 81, EDX, AMD, 1, 1, LEAF81_VME, YES, FALSE) \
474
FLAG( 81, EDX, AMD, 2, 1, LEAF81_DE, YES, FALSE) \
475
FLAG( 81, EDX, AMD, 3, 1, LEAF81_PSE, YES, FALSE) \
476
FLAG( 81, EDX, AMD, 4, 1, LEAF81_TSC, YES, TRUE) \
477
FLAG( 81, EDX, AMD, 5, 1, LEAF81_MSR, YES, FALSE) \
478
FLAG( 81, EDX, AMD, 6, 1, LEAF81_PAE, YES, FALSE) \
479
FLAG( 81, EDX, AMD, 7, 1, LEAF81_MCE, YES, FALSE) \
480
FLAG( 81, EDX, AMD, 8, 1, LEAF81_CX8, YES, TRUE) \
481
FLAG( 81, EDX, AMD, 9, 1, LEAF81_APIC, ANY, FALSE) \
482
FLAG( 81, EDX, COMMON, 11, 1, SYSC, ANY, TRUE) \
483
FLAG( 81, EDX, AMD, 12, 1, LEAF81_MTRR, YES, FALSE) \
484
FLAG( 81, EDX, AMD, 13, 1, LEAF81_PGE, YES, FALSE) \
485
FLAG( 81, EDX, AMD, 14, 1, LEAF81_MCA, YES, FALSE) \
486
FLAG( 81, EDX, AMD, 15, 1, LEAF81_CMOV, YES, TRUE) \
487
FLAG( 81, EDX, AMD, 16, 1, LEAF81_PAT, YES, FALSE) \
488
FLAG( 81, EDX, AMD, 17, 1, LEAF81_PSE36, YES, FALSE) \
489
FLAG( 81, EDX, COMMON, 20, 1, NX, YES, FALSE) \
490
FLAG( 81, EDX, AMD, 22, 1, MMXEXT, YES, TRUE) \
491
FLAG( 81, EDX, AMD, 23, 1, LEAF81_MMX, YES, TRUE) \
492
FLAG( 81, EDX, AMD, 24, 1, LEAF81_FXSR, YES, TRUE) \
493
FLAG( 81, EDX, AMD, 25, 1, FFXSR, YES, FALSE) \
494
FLAG( 81, EDX, COMMON, 26, 1, PDPE1GB, YES, FALSE) \
495
FLAG( 81, EDX, COMMON, 27, 1, RDTSCP, YES, TRUE) \
496
FLAG( 81, EDX, COMMON, 29, 1, LM, YES, FALSE) \
497
FLAG( 81, EDX, AMD, 30, 1, 3DNOWPLUS, YES, TRUE) \
498
FLAG( 81, EDX, AMD, 31, 1, 3DNOW, YES, TRUE)
469
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3, [FUNC] */
500
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */
470
501
#define CPUID_FIELD_DATA_LEVEL_8x \
471
FIELDDEF( 86, ECX, AMD, 0, 8, L2CACHE_LINE, NA, FALSE) \
472
FIELDDEF( 86, ECX, AMD, 8, 4, L2CACHE_LINE_PER_TAG, NA, FALSE) \
473
FIELDDEF( 86, ECX, AMD, 12, 4, L2CACHE_WAYS, NA, FALSE) \
474
FIELDDEF( 86, ECX, AMD, 16, 16, L2CACHE_SIZE, NA, FALSE) \
475
FIELDDEF( 86, EDX, AMD, 0, 8, L3CACHE_LINE, NA, FALSE) \
476
FIELDDEF( 86, EDX, AMD, 8, 4, L3CACHE_LINE_PER_TAG,NA, FALSE) \
477
FIELDDEF( 86, EDX, AMD, 12, 4, L3CACHE_WAYS, NA, FALSE) \
478
FIELDDEF( 86, EDX, AMD, 18, 14, L3CACHE_SIZE, NA, FALSE) \
479
FLAGDEF( 87, EDX, AMD, 0, 1, TS, NA, FALSE) \
480
FLAGDEF( 87, EDX, AMD, 1, 1, FID, NA, FALSE) \
481
FLAGDEF( 87, EDX, AMD, 2, 1, VID, NA, FALSE) \
482
FLAGDEF( 87, EDX, AMD, 3, 1, TTP, NA, FALSE) \
483
FLAGDEF( 87, EDX, AMD, 4, 1, TM, NA, FALSE) \
484
FLAGDEF( 87, EDX, AMD, 5, 1, STC, NA, FALSE) \
485
FLAGDEF( 87, EDX, AMD, 6, 1, 100MHZSTEPS, NA, FALSE) \
486
FLAGDEF( 87, EDX, AMD, 7, 1, HWPSTATE, NA, FALSE) \
487
FLAGDEF( 87, EDX, COMMON, 8, 1, TSC_INVARIANT, NA, FALSE) \
488
FIELDDEFA(88, EAX, COMMON, 0, 8, PHYSBITS, NA, FALSE, PHYS_BITS) \
489
FIELDDEFA(88, EAX, COMMON, 8, 8, VIRTBITS, NA, FALSE, VIRT_BITS) \
490
FIELDDEFA(88, ECX, AMD, 0, 8, CORE_COUNT, NA, FALSE, AMD_CORE_COUNT) \
491
FIELDDEFA(88, ECX, AMD, 12, 4, APICID_COREID_SIZE, NA, FALSE, AMD_APICID_COREID_SIZE) \
492
FIELDDEFA(8A, EAX, AMD, 0, 8, SVM_REVISION, YES, FALSE, SVM_REVISION) \
493
FLAGDEF( 8A, EAX, AMD, 8, 1, SVM_HYPERVISOR, NO, FALSE) \
494
FIELDDEF( 8A, EAX, AMD, 9, 23, SVMEAX_RSVD, NO, FALSE) \
495
FIELDDEF( 8A, EBX, AMD, 0, 32, SVM_N_ASIDS, ANY, FALSE) \
496
FIELDDEF( 8A, ECX, AMD, 0, 32, SVMECX_RSVD, NO, FALSE) \
497
FLAGDEFA( 8A, EDX, AMD, 0, 1, SVM_NP, YES, FALSE, NPT) \
498
FLAGDEF( 8A, EDX, AMD, 1, 1, SVM_LBR, NO, FALSE) \
499
FLAGDEF( 8A, EDX, AMD, 2, 1, SVM_LOCK, NO, FALSE) \
500
FLAGDEF( 8A, EDX, AMD, 3, 1, SVM_NRIP, NO, FALSE) \
501
FLAGDEFA( 8A, EDX, AMD, 10, 1, SVM_PAUSE_FILTER, NO, FALSE, PAUSE_FILTER)
505
#define CPUID_FIELD_DATA_LEVEL_8A_BD \
506
FIELDDEF( 8A, EDX, AMD, 4, 6, SVMEDX_RSVD0, NO, FALSE) \
507
FIELDDEF( 8A, EDX, AMD, 11, 21, SVMEDX_RSVD1, NO, FALSE)
502
FIELD( 85, EAX, AMD, 0, 8, ITLB_ENTRIES_2M4M_PGS, NA, FALSE) \
503
FIELD( 85, EAX, AMD, 8, 8, ITLB_ASSOC_2M4M_PGS, NA, FALSE) \
504
FIELD( 85, EAX, AMD, 16, 8, DTLB_ENTRIES_2M4M_PGS, NA, FALSE) \
505
FIELD( 85, EAX, AMD, 24, 8, DTLB_ASSOC_2M4M_PGS, NA, FALSE) \
506
FIELD( 85, EBX, AMD, 0, 8, ITLB_ENTRIES_4K_PGS, NA, FALSE) \
507
FIELD( 85, EBX, AMD, 8, 8, ITLB_ASSOC_4K_PGS, NA, FALSE) \
508
FIELD( 85, EBX, AMD, 16, 8, DTLB_ENTRIES_4K_PGS, NA, FALSE) \
509
FIELD( 85, EBX, AMD, 24, 8, DTLB_ASSOC_4K_PGS, NA, FALSE) \
510
FIELD( 85, ECX, AMD, 0, 8, L1_DCACHE_LINE_SIZE, NA, FALSE) \
511
FIELD( 85, ECX, AMD, 8, 8, L1_DCACHE_LINES_PER_TAG, NA, FALSE) \
512
FIELD( 85, ECX, AMD, 16, 8, L1_DCACHE_ASSOC, NA, FALSE) \
513
FIELD( 85, ECX, AMD, 24, 8, L1_DCACHE_SIZE, NA, FALSE) \
514
FIELD( 85, EDX, AMD, 0, 8, L1_ICACHE_LINE_SIZE, NA, FALSE) \
515
FIELD( 85, EDX, AMD, 8, 8, L1_ICACHE_LINES_PER_TAG, NA, FALSE) \
516
FIELD( 85, EDX, AMD, 16, 8, L1_ICACHE_ASSOC, NA, FALSE) \
517
FIELD( 85, EDX, AMD, 24, 8, L1_ICACHE_SIZE, NA, FALSE) \
518
FIELD( 86, EAX, AMD, 0, 12, L2_ITLB_ENTRIES_2M4M_PGS, NA, FALSE) \
519
FIELD( 86, EAX, AMD, 12, 4, L2_ITLB_ASSOC_2M4M_PGS, NA, FALSE) \
520
FIELD( 86, EAX, AMD, 16, 12, L2_DTLB_ENTRIES_2M4M_PGS, NA, FALSE) \
521
FIELD( 86, EAX, AMD, 28, 4, L2_DTLB_ASSOC_2M4M_PGS, NA, FALSE) \
522
FIELD( 86, EBX, AMD, 0, 12, L2_ITLB_ENTRIES_4K_PGS, NA, FALSE) \
523
FIELD( 86, EBX, AMD, 12, 4, L2_ITLB_ASSOC_4K_PGS, NA, FALSE) \
524
FIELD( 86, EBX, AMD, 16, 12, L2_DTLB_ENTRIES_4K_PGS, NA, FALSE) \
525
FIELD( 86, EBX, AMD, 28, 4, L2_DTLB_ASSOC_4K_PGS, NA, FALSE) \
526
FIELD( 86, ECX, AMD, 0, 8, L2CACHE_LINE, NA, FALSE) \
527
FIELD( 86, ECX, AMD, 8, 4, L2CACHE_LINE_PER_TAG, NA, FALSE) \
528
FIELD( 86, ECX, AMD, 12, 4, L2CACHE_WAYS, NA, FALSE) \
529
FIELD( 86, ECX, AMD, 16, 16, L2CACHE_SIZE, NA, FALSE) \
530
FIELD( 86, EDX, AMD, 0, 8, L3CACHE_LINE, NA, FALSE) \
531
FIELD( 86, EDX, AMD, 8, 4, L3CACHE_LINE_PER_TAG, NA, FALSE) \
532
FIELD( 86, EDX, AMD, 12, 4, L3CACHE_WAYS, NA, FALSE) \
533
FIELD( 86, EDX, AMD, 18, 14, L3CACHE_SIZE, NA, FALSE) \
534
FLAG( 87, EDX, AMD, 0, 1, TS, NA, FALSE) \
535
FLAG( 87, EDX, AMD, 1, 1, FID, NA, FALSE) \
536
FLAG( 87, EDX, AMD, 2, 1, VID, NA, FALSE) \
537
FLAG( 87, EDX, AMD, 3, 1, TTP, NA, FALSE) \
538
FLAG( 87, EDX, AMD, 4, 1, LEAF87_TM, NA, FALSE) \
539
FLAG( 87, EDX, AMD, 5, 1, STC, NA, FALSE) \
540
FLAG( 87, EDX, AMD, 6, 1, 100MHZSTEPS, NA, FALSE) \
541
FLAG( 87, EDX, AMD, 7, 1, HWPSTATE, NA, FALSE) \
542
FLAG( 87, EDX, COMMON, 8, 1, TSC_INVARIANT, NA, FALSE) \
543
FLAG( 87, EDX, COMMON, 9, 1, CORE_PERF_BOOST, NA, FALSE) \
544
FIELD( 88, EAX, COMMON, 0, 8, PHYS_BITS, NA, FALSE) \
545
FIELD( 88, EAX, COMMON, 8, 8, VIRT_BITS, NA, FALSE) \
546
FIELD( 88, EAX, COMMON, 16, 8, GUEST_PHYS_ADDR_SZ, NA, FALSE) \
547
FIELD( 88, ECX, AMD, 0, 8, LEAF88_CORE_COUNT, NA, FALSE) \
548
FIELD( 88, ECX, AMD, 12, 4, APICID_COREID_SIZE, NA, FALSE) \
549
FIELD( 8A, EAX, AMD, 0, 8, SVM_REVISION, YES, FALSE) \
550
FLAG( 8A, EAX, AMD, 8, 1, SVM_HYPERVISOR, NO, FALSE) \
551
FIELD( 8A, EAX, AMD, 9, 23, SVMEAX_RSVD, NO, FALSE) \
552
FIELD( 8A, EBX, AMD, 0, 32, SVM_NUM_ASIDS, YES, FALSE) \
553
FIELD( 8A, ECX, AMD, 0, 32, SVMECX_RSVD, NO, FALSE) \
554
FLAG( 8A, EDX, AMD, 0, 1, SVM_NPT, YES, FALSE) \
555
FLAG( 8A, EDX, AMD, 1, 1, SVM_LBR, NO, FALSE) \
556
FLAG( 8A, EDX, AMD, 2, 1, SVM_LOCK, YES, FALSE) \
557
FLAG( 8A, EDX, AMD, 3, 1, SVM_NRIP, YES, FALSE) \
558
FLAG( 8A, EDX, AMD, 4, 1, SVM_TSC_RATE_MSR, NO, FALSE) \
559
FLAG( 8A, EDX, AMD, 5, 1, SVM_VMCB_CLEAN, YES, FALSE) \
560
FLAG( 8A, EDX, AMD, 6, 1, SVM_FLUSH_BY_ASID, YES, FALSE) \
561
FLAG( 8A, EDX, AMD, 7, 1, SVM_DECODE_ASSISTS, YES, FALSE) \
562
FIELD( 8A, EDX, AMD, 8, 2, SVMEDX_RSVD0, NO, FALSE) \
563
FLAG( 8A, EDX, AMD, 10, 1, SVM_PAUSE_FILTER, NO, FALSE) \
564
FLAG( 8A, EDX, AMD, 11, 1, SVMEDX_RSVD1, NO, FALSE) \
565
FLAG( 8A, EDX, AMD, 12, 1, SVM_PAUSE_THRESHOLD, NO, FALSE) \
566
FIELD( 8A, EDX, AMD, 13, 19, SVMEDX_RSVD2, NO, FALSE)
568
/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3 */
569
#define CPUID_FIELD_DATA_LEVEL_81x \
570
FIELD(819, EAX, AMD, 0, 12, L1_ITLB_ENTRIES_1G_PGS, NA, FALSE) \
571
FIELD(819, EAX, AMD, 12, 4, L1_ITLB_ASSOC_1G_PGS, NA, FALSE) \
572
FIELD(819, EAX, AMD, 16, 12, L1_DTLB_ENTRIES_1G_PGS, NA, FALSE) \
573
FIELD(819, EAX, AMD, 28, 4, L1_DTLB_ASSOC_1G_PGS, NA, FALSE) \
574
FIELD(819, EBX, AMD, 0, 12, L2_ITLB_ENTRIES_1G_PGS, NA, FALSE) \
575
FIELD(819, EBX, AMD, 12, 4, L2_ITLB_ASSOC_1G_PGS, NA, FALSE) \
576
FIELD(819, EBX, AMD, 16, 12, L2_DTLB_ENTRIES_1G_PGS, NA, FALSE) \
577
FIELD(819, EBX, AMD, 28, 4, L2_DTLB_ASSOC_1G_PGS, NA, FALSE) \
578
FLAG( 81A, EAX, AMD, 0, 1, FP128, NA, FALSE) \
579
FLAG( 81A, EAX, AMD, 1, 1, MOVU, NA, FALSE) \
580
FLAG( 81B, EAX, AMD, 0, 1, IBS_FFV, NA, FALSE) \
581
FLAG( 81B, EAX, AMD, 1, 1, IBS_FETCHSAM, NA, FALSE) \
582
FLAG( 81B, EAX, AMD, 2, 1, IBS_OPSAM, NA, FALSE) \
583
FLAG( 81B, EAX, AMD, 3, 1, RW_OPCOUNT, NA, FALSE) \
584
FLAG( 81B, EAX, AMD, 4, 1, OPCOUNT, NA, FALSE) \
585
FLAG( 81B, EAX, AMD, 5, 1, BRANCH_TARGET_ADDR, NA, FALSE) \
586
FLAG( 81B, EAX, AMD, 6, 1, OPCOUNT_EXT, NA, FALSE) \
587
FLAG( 81B, EAX, AMD, 7, 1, RIP_INVALID_CHECK, NA, FALSE) \
588
FLAG( 81C, EAX, AMD, 0, 1, LWP_AVAIL, NA, FALSE) \
589
FLAG( 81C, EAX, AMD, 1, 1, LWP_VAL_AVAIL, NA, FALSE) \
590
FLAG( 81C, EAX, AMD, 2, 1, LWP_IRE_AVAIL, NA, FALSE) \
591
FLAG( 81C, EAX, AMD, 3, 1, LWP_BRE_AVAIL, NA, FALSE) \
592
FLAG( 81C, EAX, AMD, 4, 1, LWP_DME_AVAIL, NA, FALSE) \
593
FLAG( 81C, EAX, AMD, 5, 1, LWP_CNH_AVAIL, NA, FALSE) \
594
FLAG( 81C, EAX, AMD, 6, 1, LWP_RNH_AVAIL, NA, FALSE) \
595
FLAG( 81C, EAX, AMD, 31, 1, LWP_INT_AVAIL, NA, FALSE) \
596
FIELD(81C, EBX, AMD, 0, 8, LWP_CB_SIZE, NA, FALSE) \
597
FIELD(81C, EBX, AMD, 8, 8, LWP_EVENT_SIZE, NA, FALSE) \
598
FIELD(81C, EBX, AMD, 16, 8, LWP_MAX_EVENTS, NA, FALSE) \
599
FIELD(81C, EBX, AMD, 24, 8, LWP_EVENT_OFFSET, NA, FALSE) \
600
FIELD(81C, ECX, AMD, 0, 4, LWP_LATENCY_MAX, NA, FALSE) \
601
FLAG( 81C, ECX, AMD, 5, 1, LWP_DATA_ADDR_VALID, NA, FALSE) \
602
FIELD(81C, ECX, AMD, 6, 3, LWP_LATENCY_ROUND, NA, FALSE) \
603
FIELD(81C, ECX, AMD, 9, 7, LWP_VERSION, NA, FALSE) \
604
FIELD(81C, ECX, AMD, 16, 8, LWP_MIN_BUF_SIZE, NA, FALSE) \
605
FLAG( 81C, ECX, AMD, 28, 1, LWP_BRANCH_PRED, NA, FALSE) \
606
FLAG( 81C, ECX, AMD, 29, 1, LWP_IP_FILTERING, NA, FALSE) \
607
FLAG( 81C, ECX, AMD, 30, 1, LWP_CACHE_LEVEL, NA, FALSE) \
608
FLAG( 81C, ECX, AMD, 31, 1, LWP_CACHE_LATENCY, NA, FALSE) \
609
FLAG( 81C, EDX, AMD, 0, 1, LWP_SUPPORTED, NA, FALSE) \
610
FLAG( 81C, EDX, AMD, 1, 1, LWP_VAL_SUPPORTED, NA, FALSE) \
611
FLAG( 81C, EDX, AMD, 2, 1, LWP_IRE_SUPPORTED, NA, FALSE) \
612
FLAG( 81C, EDX, AMD, 3, 1, LWP_BRE_SUPPORTED, NA, FALSE) \
613
FLAG( 81C, EDX, AMD, 4, 1, LWP_DME_SUPPORTED, NA, FALSE) \
614
FLAG( 81C, EDX, AMD, 5, 1, LWP_CNH_SUPPORTED, NA, FALSE) \
615
FLAG( 81C, EDX, AMD, 6, 1, LWP_RNH_SUPPORTED, NA, FALSE) \
616
FLAG( 81C, EDX, AMD, 31, 1, LWP_INT_SUPPORTED, NA, FALSE) \
617
FIELD(81D, EAX, AMD, 0, 5, LEAF81D_CACHE_TYPE, NA, FALSE) \
618
FIELD(81D, EAX, AMD, 5, 3, LEAF81D_CACHE_LEVEL, NA, FALSE) \
619
FLAG( 81D, EAX, AMD, 8, 1, LEAF81D_CACHE_SELF_INIT, NA, FALSE) \
620
FLAG( 81D, EAX, AMD, 9, 1, LEAF81D_CACHE_FULLY_ASSOC, NA, FALSE) \
621
FIELD(81D, EAX, AMD, 14, 12, LEAF81D_NUM_SHARING_CACHE, NA, FALSE) \
622
FIELD(81D, EBX, AMD, 0, 12, LEAF81D_CACHE_LINE_SIZE, NA, FALSE) \
623
FIELD(81D, EBX, AMD, 12, 10, LEAF81D_CACHE_PHYS_PARTITIONS, NA, FALSE) \
624
FIELD(81D, EBX, AMD, 22, 10, LEAF81D_CACHE_WAYS, NA, FALSE) \
625
FIELD(81D, ECX, AMD, 0, 32, LEAF81D_CACHE_NUM_SETS, NA, FALSE) \
626
FLAG( 81D, EDX, AMD, 0, 1, LEAF81D_CACHE_WBINVD, NA, FALSE) \
627
FLAG( 81D, EDX, AMD, 1, 1, LEAF81D_CACHE_INCLUSIVE, NA, FALSE) \
628
FIELD(81E, EAX, AMD, 0, 32, EXTENDED_APICID, NA, FALSE) \
629
FIELD(81E, EBX, AMD, 0, 8, COMPUTE_UNIT_ID, NA, FALSE) \
630
FIELD(81E, EBX, AMD, 8, 2, CORES_PER_COMPUTE_UNIT, NA, FALSE) \
631
FIELD(81E, ECX, AMD, 0, 8, NODEID, NA, FALSE) \
632
FIELD(81E, ECX, AMD, 8, 3, NODES_PER_PKG, NA, FALSE)
634
#define INTEL_CPUID_FIELD_DATA
636
#define AMD_CPUID_FIELD_DATA
512
638
#define CPUID_FIELD_DATA \
513
639
CPUID_FIELD_DATA_LEVEL_0 \