1033
1033
/* Interrupt 0 is the reset vector. */
1035
1035
/* PSC2 Capture Event */
1036
#define PSC2_CAPT_vect_num 1
1036
1037
#define PSC2_CAPT_vect _VECTOR(1)
1038
1039
/* PSC2 End Cycle */
1040
#define PSC2_EC_vect_num 2
1039
1041
#define PSC2_EC_vect _VECTOR(2)
1041
1043
/* PSC1 Capture Event */
1044
#define PSC1_CAPT_vect_num 3
1042
1045
#define PSC1_CAPT_vect _VECTOR(3)
1044
1047
/* PSC1 End Cycle */
1048
#define PSC1_EC_vect_num 4
1045
1049
#define PSC1_EC_vect _VECTOR(4)
1047
1051
/* PSC0 Capture Event */
1052
#define PSC0_CAPT_vect_num 5
1048
1053
#define PSC0_CAPT_vect _VECTOR(5)
1050
1055
/* PSC0 End Cycle */
1056
#define PSC0_EC_vect_num 6
1051
1057
#define PSC0_EC_vect _VECTOR(6)
1053
1059
/* Analog Comparator 0 */
1060
#define ANALOG_COMP_0_vect_num 7
1054
1061
#define ANALOG_COMP_0_vect _VECTOR(7)
1056
1063
/* Analog Comparator 1 */
1064
#define ANALOG_COMP_1_vect_num 8
1057
1065
#define ANALOG_COMP_1_vect _VECTOR(8)
1059
1067
/* Analog Comparator 2 */
1068
#define ANALOG_COMP_2_vect_num 9
1060
1069
#define ANALOG_COMP_2_vect _VECTOR(9)
1062
1071
/* External Interrupt Request 0 */
1072
#define INT0_vect_num 10
1063
1073
#define INT0_vect _VECTOR(10)
1065
1075
/* Timer/Counter1 Capture Event */
1076
#define TIMER1_CAPT_vect_num 11
1066
1077
#define TIMER1_CAPT_vect _VECTOR(11)
1068
1079
/* Timer/Counter1 Compare Match A */
1080
#define TIMER1_COMPA_vect_num 12
1069
1081
#define TIMER1_COMPA_vect _VECTOR(12)
1071
1083
/* Timer/Counter Compare Match B */
1084
#define TIMER1_COMPB_vect_num 13
1072
1085
#define TIMER1_COMPB_vect _VECTOR(13)
1074
1087
/* Timer/Counter1 Overflow */
1088
#define TIMER1_OVF_vect_num 15
1075
1089
#define TIMER1_OVF_vect _VECTOR(15)
1077
1091
/* Timer/Counter0 Compare Match A */
1092
#define TIMER0_COMP_A_vect_num 16
1078
1093
#define TIMER0_COMP_A_vect _VECTOR(16)
1080
1095
/* Timer/Counter0 Overflow */
1096
#define TIMER0_OVF_vect_num 17
1081
1097
#define TIMER0_OVF_vect _VECTOR(17)
1083
1099
/* ADC Conversion Complete */
1100
#define ADC_vect_num 18
1084
1101
#define ADC_vect _VECTOR(18)
1086
1103
/* External Interrupt Request 1 */
1104
#define INT1_vect_num 19
1087
1105
#define INT1_vect _VECTOR(19)
1089
1107
/* SPI Serial Transfer Complete */
1108
#define SPI_STC_vect_num 20
1090
1109
#define SPI_STC_vect _VECTOR(20)
1092
1111
/* USART, Rx Complete */
1112
#define USART_RX_vect_num 21
1093
1113
#define USART_RX_vect _VECTOR(21)
1095
1115
/* USART Data Register Empty */
1116
#define USART_UDRE_vect_num 22
1096
1117
#define USART_UDRE_vect _VECTOR(22)
1098
1119
/* USART, Tx Complete */
1120
#define USART_TX_vect_num 23
1099
1121
#define USART_TX_vect _VECTOR(23)
1101
1123
/* External Interrupt Request 2 */
1124
#define INT2_vect_num 24
1102
1125
#define INT2_vect _VECTOR(24)
1104
1127
/* Watchdog Timeout Interrupt */
1128
#define WDT_vect_num 25
1105
1129
#define WDT_vect _VECTOR(25)
1107
1131
/* EEPROM Ready */
1132
#define EE_READY_vect_num 26
1108
1133
#define EE_READY_vect _VECTOR(26)
1110
1135
/* Timer Counter 0 Compare Match B */
1136
#define TIMER0_COMPB_vect_num 27
1111
1137
#define TIMER0_COMPB_vect _VECTOR(27)
1113
1139
/* External Interrupt Request 3 */
1140
#define INT3_vect_num 28
1114
1141
#define INT3_vect _VECTOR(28)
1116
1143
/* Store Program Memory Read */
1144
#define SPM_READY_vect_num 31
1117
1145
#define SPM_READY_vect _VECTOR(31)
1119
1147
#define _VECTORS_SIZE (4 * 32)