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/* Copyright (c) 2008 Atmel Corporation
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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* Neither the name of the copyright holders nor the names of
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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/* $Id: iom32c1.h,v 1.1.2.3 2008/04/28 17:06:22 arcanum Exp $ */
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/* avr/iom32c1.h - definitions for ATmega32C1. */
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/* This file should only be included from <avr/io.h>, never directly. */
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# error "Include <avr/io.h> instead of this file."
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# define _AVR_IOXXX_H_ "iom32c1.h"
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# error "Attempt to include more than one <avr/ioXXX.h> file."
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#ifndef _AVR_IOM32C1_H_
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#define _AVR_IOM32C1_H_ 1
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/* Registers and associated bit numbers */
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#define PINB _SFR_IO8(0x03)
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#define DDRB _SFR_IO8(0x04)
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#define PORTB _SFR_IO8(0x05)
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#define PINC _SFR_IO8(0x06)
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#define DDRC _SFR_IO8(0x07)
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#define PORTC _SFR_IO8(0x08)
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#define PIND _SFR_IO8(0x09)
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#define DDRD _SFR_IO8(0x0A)
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#define PORTD _SFR_IO8(0x0B)
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#define PINE _SFR_IO8(0x0C)
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#define DDRE _SFR_IO8(0x0D)
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#define PORTE _SFR_IO8(0x0E)
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#define TIFR0 _SFR_IO8(0x15)
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#define TIFR1 _SFR_IO8(0x16)
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#define GPIOR1 _SFR_IO8(0x19)
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#define GPIOR2 _SFR_IO8(0x1A)
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#define PCIFR _SFR_IO8(0x1B)
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#define EIFR _SFR_IO8(0x1C)
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#define EIMSK _SFR_IO8(0x1D)
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#define GPIOR0 _SFR_IO8(0x1E)
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#define EECR _SFR_IO8(0x1F)
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#define EEDR _SFR_IO8(0x20)
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#define EEAR _SFR_IO16(0x21)
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#define EEARL _SFR_IO8(0x21)
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#define EEARH _SFR_IO8(0x22)
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#define GTCCR _SFR_IO8(0x23)
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#define TCCR0A _SFR_IO8(0x24)
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#define TCCR0B _SFR_IO8(0x25)
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#define TCNT0 _SFR_IO8(0x26)
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#define OCR0A _SFR_IO8(0x27)
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#define OCR0B _SFR_IO8(0x28)
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#define PLLCSR _SFR_IO8(0x29)
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#define SPCR _SFR_IO8(0x2C)
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#define SPSR _SFR_IO8(0x2D)
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#define SPDR _SFR_IO8(0x2E)
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#define ACSR _SFR_IO8(0x30)
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#define DWDR _SFR_IO8(0x31)
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#define SMCR _SFR_IO8(0x33)
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#define MCUSR _SFR_IO8(0x34)
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#define MCUCR _SFR_IO8(0x35)
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#define SPMCSR _SFR_IO8(0x37)
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#define WDTCSR _SFR_MEM8(0x60)
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#define CLKPR _SFR_MEM8(0x61)
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#define PRR _SFR_MEM8(0x64)
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#define OSCCAL _SFR_MEM8(0x66)
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#define EICRA _SFR_MEM8(0x69)
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#define PCMSK0 _SFR_MEM8(0x6A)
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#define PCMSK1 _SFR_MEM8(0x6B)
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#define PCMSK2 _SFR_MEM8(0x6C)
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#define PCMSK3 _SFR_MEM8(0x6D)
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#define TIMSK0 _SFR_MEM8(0x6E)
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#define TIMSK1 _SFR_MEM8(0x6F)
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#define AMP0CSR _SFR_MEM8(0x75)
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#define AMP1CSR _SFR_MEM8(0x76)
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#define AMP2CSR _SFR_MEM8(0x77)
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#ifndef __ASSEMBLER__
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#define ADC _SFR_MEM16(0x78)
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#define ADCW _SFR_MEM16(0x78)
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#define ADCL _SFR_MEM8(0x78)
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#define ADCH _SFR_MEM8(0x79)
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#define ADCSRA _SFR_MEM8(0x7A)
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#define ADCSRB _SFR_MEM8(0x7B)
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#define ADMUX _SFR_MEM8(0x7C)
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#define DIDR0 _SFR_MEM8(0x7E)
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#define DIDR1 _SFR_MEM8(0x7F)
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#define TCCR1A _SFR_MEM8(0x80)
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#define TCCR1B _SFR_MEM8(0x81)
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#define TCCR1C _SFR_MEM8(0x82)
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#define TCNT1 _SFR_MEM16(0x84)
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#define TCNT1L _SFR_MEM8(0x84)
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#define TCNT1H _SFR_MEM8(0x85)
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#define ICR1 _SFR_MEM16(0x86)
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#define ICR1L _SFR_MEM8(0x86)
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#define ICR1H _SFR_MEM8(0x87)
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#define OCR1A _SFR_MEM16(0x89)
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#define OCR1AL _SFR_MEM8(0x88)
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#define OCR1AH _SFR_MEM8(0x89)
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#define OCR1B _SFR_MEM16(0x8A)
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#define OCR1BL _SFR_MEM8(0x8A)
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#define OCR1BH _SFR_MEM8(0x8B)
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#define DACON _SFR_MEM8(0x90)
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#define DAC _SFR_MEM16(0x91)
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#define DACL _SFR_MEM8(0x91)
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#define DACH _SFR_MEM8(0x92)
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#define AC0CON _SFR_MEM8(0x94)
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#define AC1CON _SFR_MEM8(0x95)
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#define AC2CON _SFR_MEM8(0x96)
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#define AC3CON _SFR_MEM8(0x97)
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#define LINCR _SFR_MEM8(0xC8)
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#define LINSIR _SFR_MEM8(0xC9)
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#define LINENIR _SFR_MEM8(0xCA)
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#define LINERR _SFR_MEM8(0xCB)
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#define LINBTR _SFR_MEM8(0xCC)
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#define LINBRR _SFR_MEM16(0xCD)
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#define LINBRRL _SFR_MEM8(0xCD)
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#define LINBRRH _SFR_MEM8(0xCE)
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#define LINDLR _SFR_MEM8(0xCF)
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#define LINIDR _SFR_MEM8(0xD0)
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#define LINSEL _SFR_MEM8(0xD1)
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#define LINDAT _SFR_MEM8(0xD2)
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#define CANGCON _SFR_MEM8(0xD8)
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#define CANGSTA _SFR_MEM8(0xD9)
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#define CANGIT _SFR_MEM8(0xDA)
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#define CANGIE _SFR_MEM8(0xDB)
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#define CANEN2 _SFR_MEM8(0xDC)
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#define CANEN1 _SFR_MEM8(0xDD)
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#define CANIE2 _SFR_MEM8(0xDE)
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#define CANIE1 _SFR_MEM8(0xDF)
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#define CANSIT2 _SFR_MEM8(0xE0)
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#define CANSIT1 _SFR_MEM8(0xE1)
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#define CANBT1 _SFR_MEM8(0xE2)
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#define CANBT2 _SFR_MEM8(0xE3)
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#define CANBT3 _SFR_MEM8(0xE4)
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#define CANTCON _SFR_MEM8(0xE5)
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#define CANTIM _SFR_MEM16(0xE6)
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#define CANTIML _SFR_MEM8(0xE6)
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#define CANTIMH _SFR_MEM8(0xE7)
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#define CANTTC _SFR_MEM16(0xE8)
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#define CANTTCL _SFR_MEM8(0xE8)
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#define CANTTCH _SFR_MEM8(0xE9)
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#define CANTEC _SFR_MEM8(0xEA)
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#define CANREC _SFR_MEM8(0xEB)
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#define CANHPMOB _SFR_MEM8(0xEC)
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#define CANPAGE _SFR_MEM8(0xED)
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#define CANSTMOB _SFR_MEM8(0xEE)
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#define CANCDMOB _SFR_MEM8(0xEF)
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#define CANIDT4 _SFR_MEM8(0xF0)
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#define CANIDT3 _SFR_MEM8(0xF1)
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#define CANIDT2 _SFR_MEM8(0xF2)
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#define CANIDT1 _SFR_MEM8(0xF3)
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#define CANIDM4 _SFR_MEM8(0xF4)
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#define CANIDM3 _SFR_MEM8(0xF5)
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#define CANIDM2 _SFR_MEM8(0xF6)
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#define CANIDM1 _SFR_MEM8(0xF7)
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#define CANSTM _SFR_MEM16(0xF8)
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#define CANSTML _SFR_MEM8(0xF8)
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#define CANSTMH _SFR_MEM8(0xF9)
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#define CANMSG _SFR_MEM8(0xFA)
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/* Interrupt Vectors */
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/* Interrupt Vector 0 is the reset vector. */
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#define ANACOMP0_vect _VECTOR(1) /* Analog Comparator 0 */
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#define ANACOMP1_vect _VECTOR(2) /* Analog Comparator 1 */
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#define ANACOMP2_vect _VECTOR(3) /* Analog Comparator 2 */
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#define ANACOMP3_vect _VECTOR(4) /* Analog Comparator 3 */
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#define PSC_FAULT_vect _VECTOR(5) /* PSC Fault */
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#define PSC_EC_vect _VECTOR(6) /* PSC End of Cycle */
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#define INT0_vect _VECTOR(7) /* External Interrupt Request 0 */
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#define INT1_vect _VECTOR(8) /* External Interrupt Request 1 */
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#define INT2_vect _VECTOR(9) /* External Interrupt Request 2 */
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#define INT3_vect _VECTOR(10) /* External Interrupt Request 3 */
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#define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */
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#define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */
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#define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter1 Compare Match B */
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#define TIMER1_OVF_vect _VECTOR(14) /* Timer1/Counter1 Overflow */
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#define TIMER0_COMPA_vect _VECTOR(15) /* Timer/Counter0 Compare Match A */
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#define TIMER0_COMPB_vect _VECTOR(16) /* Timer/Counter0 Compare Match B */
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#define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */
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#define CAN_INT_vect _VECTOR(18) /* CAN MOB, Burst, General Errors */
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#define CAN_TOVF_vect _VECTOR(19) /* CAN Timer Overflow */
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#define LIN_TC_vect _VECTOR(20) /* LIN Transfer Complete */
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#define LIN_ERR_vect _VECTOR(21) /* LIN Error */
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#define PCINT0_vect _VECTOR(22) /* Pin Change Interrupt Request 0 */
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#define PCINT1_vect _VECTOR(23) /* Pin Change Interrupt Request 1 */
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#define PCINT2_vect _VECTOR(24) /* Pin Change Interrupt Request 2 */
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#define PCINT3_vect _VECTOR(25) /* Pin Change Interrupt Request 3 */
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#define SPI_STC_vect _VECTOR(26) /* SPI Serial Transfer Complete */
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#define ADC_vect _VECTOR(27) /* ADC Conversion Complete */
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#define WDT_vect _VECTOR(28) /* Watchdog Time-Out Interrupt */
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#define EE_READY_vect _VECTOR(29) /* EEPROM Ready */
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#define SPM_READY_vect _VECTOR(30) /* Store Program Memory Read */
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#define _VECTORS_SIZE (31 * 4)
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#define SPM_PAGESIZE (64)
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#define RAMSTART (0x100)
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#define RAMSIZE (0x800)
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#define RAMEND (RAMSTART + RAMSIZE - 1) /* Last On-Chip SRAM Location */
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#define XRAMSIZE (0x800)
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#define XRAMEND (RAMEND + XRAMSIZE)
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#define E2END (0x3FF)
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#define FLASHEND (0x7FFF)
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#define FUSE_MEMORY_SIZE 3
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#define FUSE_CKSEL0 ~_BV(0) /* Select Clock Source */
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#define FUSE_CKSEL1 ~_BV(1) /* Select Clock Source */
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#define FUSE_CKSEL2 ~_BV(2) /* Select Clock Source */
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#define FUSE_CKSEL3 ~_BV(3) /* Select Clock Source */
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#define FUSE_SUT0 ~_BV(4) /* Select start-up time */
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#define FUSE_SUT1 ~_BV(5) /* Select start-up time */
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#define FUSE_CKOUT ~_BV(6) /* Oscillator output option */
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#define FUSE_CKDIV8 ~_BV(7) /* Divide clock by 8 */
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#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
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/* High Fuse Byte */
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#define FUSE_BOOTRST ~_BV(0) /* Select Reset Vector */
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#define FUSE_BOOTSZ0 ~_BV(1) /* Select Boot Size */
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#define FUSE_BOOTSZ1 ~_BV(2) /* Select Boot Size */
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#define FUSE_EESAVE ~_BV(3) /* EEPROM memory is preserved through chip erase */
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#define FUSE_WDTON ~_BV(4) /* Watchdog timer always on */
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#define FUSE_SPIEN ~_BV(5) /* Enable Serial programming and Data Downloading */
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#define FUSE_DWEN ~_BV(6) /* debugWIRE Enable */
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#define FUSE_RSTDISBL ~_BV(7) /* External Reset Disable */
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#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN)
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/* Extended Fuse Byte */
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#define FUSE_BODLEVEL0 ~_BV(0) /* Brown-out Detector Trigger Level */
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#define FUSE_BODLEVEL1 ~_BV(1) /* Brown-out Detector Trigger Level */
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#define FUSE_BODLEVEL2 ~_BV(2) /* Brown-out Detector Trigger Level */
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#define FUSE_PSCRVB ~_BV(3) /* PSC Outputs xB Reset Value */
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#define FUSE_PSCRVA ~_BV(4) /* PSC Outputs xA Reset Value */
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#define FUSE_PSCRB ~_BV(5) /* PSC Reset Behavior */
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#define EFUSE_DEFAULT (FUSE_BODLEVEL1 & FUSE_BODLEVEL2)
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#define __LOCK_BITS_EXIST
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#define __BOOT_LOCK_BITS_0_EXIST
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#define __BOOT_LOCK_BITS_1_EXIST
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#endif /* _AVR_IOM32C1_H_ */
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removed
include/avr/iom32c1.h
