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/* Copyright (c) 2007 Anatoly Sokolov
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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* Neither the name of the copyright holders nor the names of
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE. */
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/* $Id: iousbxx2.h,v 1.3 2007/05/12 11:40:46 aesok Exp $ */
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/* iousbxx2.h - definitions for AT90USB82 and AT90USB162. */
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#ifndef _AVR_IOUSBXX2_H_
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#define _AVR_IOUSBXX2_H_ 1
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/* This file should only be included from <avr/io.h>, never directly. */
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# error "Include <avr/io.h> instead of this file."
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# define _AVR_IOXXX_H_ "iousbxx2.h"
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# error "Attempt to include more than one <avr/ioXXX.h> file."
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/* Registers and associated bit numbers */
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/* Reserved [0x00..0x02] */
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#define PINB _SFR_IO8(0X03)
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#define DDRB _SFR_IO8(0x04)
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#define PORTB _SFR_IO8(0x05)
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#define PINC _SFR_IO8(0x06)
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#define DDRC _SFR_IO8(0x07)
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#define PORTC _SFR_IO8(0x08)
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#define PIND _SFR_IO8(0x09)
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#define DDRD _SFR_IO8(0x0A)
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#define PORTD _SFR_IO8(0x0B)
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/* Reserved [0xC..0x14] */
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#define TIFR0 _SFR_IO8(0x15)
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#define TIFR1 _SFR_IO8(0x16)
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/* Reserved [0x17..0x1A] */
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#define PCIFR _SFR_IO8(0x1B)
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#define EIFR _SFR_IO8(0x1C)
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#define EIMSK _SFR_IO8(0x1D)
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#define GPIOR0 _SFR_IO8(0x1E)
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#define EECR _SFR_IO8(0x1F)
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#define EEDR _SFR_IO8(0x20)
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#define EEAR _SFR_IO16(0x21)
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#define EEARL _SFR_IO8(0x21)
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#define EEARH _SFR_IO8(0x22)
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/* 6-char sequence denoting where to find the EEPROM registers in memory space.
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Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
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First two letters: EECR address.
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Second two letters: EEDR address.
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Last two letters: EEAR address. */
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#define __EEPROM_REG_LOCATIONS__ 1F2021
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#define GTCCR _SFR_IO8(0x23)
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#define TCCR0A _SFR_IO8(0x24)
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#define TCCR0B _SFR_IO8(0x25)
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#define TCNT0 _SFR_IO8(0X26)
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#define OCR0A _SFR_IO8(0x27)
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#define OCR0B _SFR_IO8(0X28)
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#define PLLCSR _SFR_IO8(0x29)
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#define GPIOR1 _SFR_IO8(0x2A)
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#define GPIOR2 _SFR_IO8(0x2B)
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#define SPCR _SFR_IO8(0x2C)
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#define SPSR _SFR_IO8(0x2D)
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#define SPDR _SFR_IO8(0x2E)
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/* Reserved [0x2F] */
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#define ACSR _SFR_IO8(0x30)
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#define DWDR _SFR_IO8(0x31)
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/* Reserved [0x32] */
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#define SMCR _SFR_IO8(0x33)
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#define MCUSR _SFR_IO8(0x34)
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#define MCUCR _SFR_IO8(0x35)
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/* Reserved [0x36] */
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#define SPMCSR _SFR_IO8(0x37)
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/* Reserved [0x38..0x3C] */
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/* SP [0x3D..0x3E] */
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#define WDTCSR _SFR_MEM8(0x60)
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#define CLKPR _SFR_MEM8(0x61)
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#define WDTCKD _SFR_MEM8(0x62)
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#define REGCR _SFR_MEM8(0x63)
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#define PRR0 _SFR_MEM8(0x64)
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#define PRR1 _SFR_MEM8(0x65)
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#define OSCCAL _SFR_MEM8(0x66)
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/* Reserved [0x67] */
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#define PCICR _SFR_MEM8(0x68)
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#define EICRA _SFR_MEM8(0x69)
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#define EICRB _SFR_MEM8(0x6A)
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#define PCMSK0 _SFR_MEM8(0x6B)
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#define PCMSK1 _SFR_MEM8(0x6C)
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/* Reserved [0x6D] */
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#define TIMSK0 _SFR_MEM8(0x6E)
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#define TIMSK1 _SFR_MEM8(0x6F)
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/* Reserved [0x70..0x7F] */
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#define TCCR1A _SFR_MEM8(0x80)
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#define TCCR1B _SFR_MEM8(0x81)
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#define TCCR1C _SFR_MEM8(0x82)
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/* Reserved [0x83] */
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/* Combine TCNT1L and TCNT1H */
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#define TCNT1 _SFR_MEM16(0x84)
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#define TCNT1L _SFR_MEM8(0x84)
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#define TCNT1H _SFR_MEM8(0x85)
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/* Combine ICR1L and ICR1H */
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#define ICR1 _SFR_MEM16(0x86)
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#define ICR1L _SFR_MEM8(0x86)
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#define ICR1H _SFR_MEM8(0x87)
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/* Combine OCR1AL and OCR1AH */
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#define OCR1A _SFR_MEM16(0x88)
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#define OCR1AL _SFR_MEM8(0x88)
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#define OCR1AH _SFR_MEM8(0x89)
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/* Combine OCR1BL and OCR1BH */
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#define OCR1B _SFR_MEM16(0x8A)
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#define OCR1BL _SFR_MEM8(0x8A)
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#define OCR1BH _SFR_MEM8(0x8B)
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/* Combine OCR1CL and OCR1CH */
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#define OCR1C _SFR_MEM16(0x8C)
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#define OCR1CL _SFR_MEM8(0x8C)
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#define OCR1CH _SFR_MEM8(0x8D)
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/* Reserved [0x8E..0xC7] */
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#define UCSR1A _SFR_MEM8(0xC8)
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#define UCSR1B _SFR_MEM8(0XC9)
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#define UCSR1C _SFR_MEM8(0xCA)
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#define UCSR1D _SFR_MEM8(0xCB)
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/* Combine UBRR1L and UBRR1H */
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#define UBRR1 _SFR_MEM16(0xCC)
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#define UBRR1L _SFR_MEM8(0xCC)
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#define UBRR1H _SFR_MEM8(0xCD)
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#define UDR1 _SFR_MEM8(0XCE)
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/* Reserved [0xCF] */
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#define CKSEL0 _SFR_MEM8(0XD0)
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#define CKSEL1 _SFR_MEM8(0XD1)
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#define CKSTA _SFR_MEM8(0XD2)
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/* Reserved [0xD3..0xD7] */
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#define USBCON _SFR_MEM8(0XD8)
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/* Reserved [0xD9..0xDA] */
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/* Combine UDPADDL and UDPADDH */
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#define UDPADD _SFR_MEM16(0xDB)
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#define UDPADDL _SFR_MEM8(0xDB)
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#define UDPADDH _SFR_MEM8(0xDC)
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/* Reserved [0xDD..0xDF] */
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#define UDCON _SFR_MEM8(0XE0)
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#define UDINT _SFR_MEM8(0XE1)
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#define UDIEN _SFR_MEM8(0XE2)
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#define UDADDR _SFR_MEM8(0XE3)
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/* Combine UDFNUML and UDFNUMH */
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#define UDFNUM _SFR_MEM16(0xE4)
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#define UDFNUML _SFR_MEM8(0xE4)
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#define UDFNUMH _SFR_MEM8(0xE5)
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#define UDMFN _SFR_MEM8(0XE6)
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/* Reserved [0xE7] */
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#define UEINTX _SFR_MEM8(0XE8)
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#define UENUM _SFR_MEM8(0XE9)
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#define UERST _SFR_MEM8(0XEA)
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#define UECONX _SFR_MEM8(0XEB)
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#define UECFG0X _SFR_MEM8(0XEC)
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#define UECFG1X _SFR_MEM8(0XED)
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#define UESTA0X _SFR_MEM8(0XEE)
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#define UESTA1X _SFR_MEM8(0XEF)
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#define UEIENX _SFR_MEM8(0XF0)
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#define UEDATX _SFR_MEM8(0XF1)
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#define UEBCLX _SFR_MEM8(0xF2)
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/* Reserved [0xF3] */
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#define UEINT _SFR_MEM8(0XF4)
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/* Reserved [0xF5..0xF9] */
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#define PS2CON _SFR_MEM8(0XFA)
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#define UPOE _SFR_MEM8(0XFB)
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/* Reserved [0xFC..0xFF] */
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/* Interrupt vectors */
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/* External Interrupt Request 0 */
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#define INT0_vect _VECTOR(1)
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/* External Interrupt Request 1 */
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#define INT1_vect _VECTOR(2)
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/* External Interrupt Request 2 */
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#define INT2_vect _VECTOR(3)
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/* External Interrupt Request 3 */
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#define INT3_vect _VECTOR(4)
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/* External Interrupt Request 4 */
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#define INT4_vect _VECTOR(5)
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/* External Interrupt Request 5 */
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#define INT5_vect _VECTOR(6)
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/* External Interrupt Request 6 */
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#define INT6_vect _VECTOR(7)
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/* External Interrupt Request 7 */
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#define INT7_vect _VECTOR(8)
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/* Pin Change Interrupt Request 0 */
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#define PCINT0_vect _VECTOR(9)
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/* Pin Change Interrupt Request 1 */
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#define PCINT1_vect _VECTOR(10)
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/* USB General Interrupt Request */
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#define USB_GEN_vect _VECTOR(11)
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/* USB Endpoint/Pipe Interrupt Communication Request */
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#define USB_COM_vect _VECTOR(12)
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/* Watchdog Time-out Interrupt */
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#define WDT_vect _VECTOR(13)
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/* Timer/Counter2 Capture Event */
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#define TIMER1_CAPT_vect _VECTOR(14)
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/* Timer/Counter2 Compare Match B */
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#define TIMER1_COMPA_vect _VECTOR(15)
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/* Timer/Counter2 Compare Match B */
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#define TIMER1_COMPB_vect _VECTOR(16)
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/* Timer/Counter2 Compare Match C */
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#define TIMER1_COMPC_vect _VECTOR(17)
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/* Timer/Counter1 Overflow */
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#define TIMER1_OVF_vect _VECTOR(18)
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/* Timer/Counter0 Compare Match A */
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#define TIMER0_COMPA_vect _VECTOR(19)
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/* Timer/Counter0 Compare Match B */
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#define TIMER0_COMPB_vect _VECTOR(20)
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/* Timer/Counter0 Overflow */
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#define TIMER0_OVF_vect _VECTOR(21)
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/* SPI Serial Transfer Complete */
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#define SPI_STC_vect _VECTOR(22)
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/* USART1, Rx Complete */
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#define USART1_RX_vect _VECTOR(23)
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/* USART1 Data register Empty */
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#define USART1_UDRE_vect _VECTOR(24)
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/* USART1, Tx Complete */
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#define USART1_TX_vect _VECTOR(25)
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/* Analog Comparator */
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#define ANALOG_COMP_vect _VECTOR(26)
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#define EE_READY_vect _VECTOR(27)
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/* Store Program Memory Read */
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#define SPM_READY_vect _VECTOR(28)
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#define _VECTORS_SIZE 116
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#endif /* _AVR_IOUSBXX2_H_ */
added
removed
include/avr/iousbxx2.h
