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Viewing changes to usrp/fpga/megacells/addsub16.v

  • Committer: Package Import Robot
  • Author(s): A. Maitland Bottoms
  • Date: 2012-02-26 21:26:16 UTC
  • mfrom: (1.1.4)
  • Revision ID: package-import@ubuntu.com-20120226212616-vsfkbi1158xshdql
Tags: 3.5.1-1
http://bugs.debian.org/642716
http://bugs.debian.org/645332
http://bugs.debian.org/394849
http://bugs.debian.org/616832
http://bugs.debian.org/590048
http://bugs.debian.org/642580
* new upstream version, re-packaged from scratch with modern tools
    closes: #642716, #645332, #394849, #616832, #590048, #642580,
    #647018, #557050, #559640, #631863
* CMake build

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usrp/fpga/megacells/addsub16.v
1
 
// megafunction wizard: %LPM_ADD_SUB%CBX%
2
 
// GENERATION: STANDARD
3
 
// VERSION: WM1.0
4
 
// MODULE: lpm_add_sub 
5
 
 
6
 
// ============================================================
7
 
// File Name: addsub16.v
8
 
// Megafunction Name(s):
9
 
//                      lpm_add_sub
10
 
// ============================================================
11
 
// ************************************************************
12
 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
13
 
// ************************************************************
14
 
 
15
 
 
16
 
//Copyright (C) 1991-2003 Altera Corporation
17
 
//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
18
 
//support information,  device programming or simulation file,  and any other
19
 
//associated  documentation or information  provided by  Altera  or a partner
20
 
//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
21
 
//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
22
 
//other  use  of such  megafunction  design,  netlist,  support  information,
23
 
//device programming or simulation file,  or any other  related documentation
24
 
//or information  is prohibited  for  any  other purpose,  including, but not
25
 
//limited to  modification,  reverse engineering,  de-compiling, or use  with
26
 
//any other  silicon devices,  unless such use is  explicitly  licensed under
27
 
//a separate agreement with  Altera  or a megafunction partner.  Title to the
28
 
//intellectual property,  including patents,  copyrights,  trademarks,  trade
29
 
//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
30
 
//support  information,  device programming or simulation file,  or any other
31
 
//related documentation or information provided by  Altera  or a megafunction
32
 
//partner, remains with Altera, the megafunction partner, or their respective
33
 
//licensors. No other licenses, including any licenses needed under any third
34
 
//party's intellectual property, are provided herein.
35
 
 
36
 
 
37
 
//lpm_add_sub DEVICE_FAMILY=Cyclone LPM_PIPELINE=1 LPM_WIDTH=16 aclr add_sub clken clock dataa datab result
38
 
//VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ  VERSION_END
39
 
 
40
 
//synthesis_resources = lut 17 
41
 
module  addsub16_add_sub_gp9
42
 
        ( 
43
 
        aclr,
44
 
        add_sub,
45
 
        clken,
46
 
        clock,
47
 
        dataa,
48
 
        datab,
49
 
        result) /* synthesis synthesis_clearbox=1 */;
50
 
        input   aclr;
51
 
        input   add_sub;
52
 
        input   clken;
53
 
        input   clock;
54
 
        input   [15:0]  dataa;
55
 
        input   [15:0]  datab;
56
 
        output   [15:0]  result;
57
 
 
58
 
        wire  [0:0]   wire_add_sub_cella_0cout;
59
 
        wire  [0:0]   wire_add_sub_cella_1cout;
60
 
        wire  [0:0]   wire_add_sub_cella_2cout;
61
 
        wire  [0:0]   wire_add_sub_cella_3cout;
62
 
        wire  [0:0]   wire_add_sub_cella_4cout;
63
 
        wire  [0:0]   wire_add_sub_cella_5cout;
64
 
        wire  [0:0]   wire_add_sub_cella_6cout;
65
 
        wire  [0:0]   wire_add_sub_cella_7cout;
66
 
        wire  [0:0]   wire_add_sub_cella_8cout;
67
 
        wire  [0:0]   wire_add_sub_cella_9cout;
68
 
        wire  [0:0]   wire_add_sub_cella_10cout;
69
 
        wire  [0:0]   wire_add_sub_cella_11cout;
70
 
        wire  [0:0]   wire_add_sub_cella_12cout;
71
 
        wire  [0:0]   wire_add_sub_cella_13cout;
72
 
        wire  [0:0]   wire_add_sub_cella_14cout;
73
 
        wire  [15:0]   wire_add_sub_cella_dataa;
74
 
        wire  [15:0]   wire_add_sub_cella_datab;
75
 
        wire  [15:0]   wire_add_sub_cella_regout;
76
 
        wire  wire_strx_lcell1_cout;
77
 
 
78
 
        stratix_lcell   add_sub_cella_0
79
 
        ( 
80
 
        .aclr(aclr),
81
 
        .cin(wire_strx_lcell1_cout),
82
 
        .clk(clock),
83
 
        .cout(wire_add_sub_cella_0cout[0:0]),
84
 
        .dataa(wire_add_sub_cella_dataa[0:0]),
85
 
        .datab(wire_add_sub_cella_datab[0:0]),
86
 
        .ena(clken),
87
 
        .inverta((~ add_sub)),
88
 
        .regout(wire_add_sub_cella_regout[0:0]));
89
 
        defparam
90
 
                add_sub_cella_0.cin_used = "true",
91
 
                add_sub_cella_0.lut_mask = "96e8",
92
 
                add_sub_cella_0.operation_mode = "arithmetic",
93
 
                add_sub_cella_0.sum_lutc_input = "cin",
94
 
                add_sub_cella_0.lpm_type = "stratix_lcell";
95
 
        stratix_lcell   add_sub_cella_1
96
 
        ( 
97
 
        .aclr(aclr),
98
 
        .cin(wire_add_sub_cella_0cout[0:0]),
99
 
        .clk(clock),
100
 
        .cout(wire_add_sub_cella_1cout[0:0]),
101
 
        .dataa(wire_add_sub_cella_dataa[1:1]),
102
 
        .datab(wire_add_sub_cella_datab[1:1]),
103
 
        .ena(clken),
104
 
        .inverta((~ add_sub)),
105
 
        .regout(wire_add_sub_cella_regout[1:1]));
106
 
        defparam
107
 
                add_sub_cella_1.cin_used = "true",
108
 
                add_sub_cella_1.lut_mask = "96e8",
109
 
                add_sub_cella_1.operation_mode = "arithmetic",
110
 
                add_sub_cella_1.sum_lutc_input = "cin",
111
 
                add_sub_cella_1.lpm_type = "stratix_lcell";
112
 
        stratix_lcell   add_sub_cella_2
113
 
        ( 
114
 
        .aclr(aclr),
115
 
        .cin(wire_add_sub_cella_1cout[0:0]),
116
 
        .clk(clock),
117
 
        .cout(wire_add_sub_cella_2cout[0:0]),
118
 
        .dataa(wire_add_sub_cella_dataa[2:2]),
119
 
        .datab(wire_add_sub_cella_datab[2:2]),
120
 
        .ena(clken),
121
 
        .inverta((~ add_sub)),
122
 
        .regout(wire_add_sub_cella_regout[2:2]));
123
 
        defparam
124
 
                add_sub_cella_2.cin_used = "true",
125
 
                add_sub_cella_2.lut_mask = "96e8",
126
 
                add_sub_cella_2.operation_mode = "arithmetic",
127
 
                add_sub_cella_2.sum_lutc_input = "cin",
128
 
                add_sub_cella_2.lpm_type = "stratix_lcell";
129
 
        stratix_lcell   add_sub_cella_3
130
 
        ( 
131
 
        .aclr(aclr),
132
 
        .cin(wire_add_sub_cella_2cout[0:0]),
133
 
        .clk(clock),
134
 
        .cout(wire_add_sub_cella_3cout[0:0]),
135
 
        .dataa(wire_add_sub_cella_dataa[3:3]),
136
 
        .datab(wire_add_sub_cella_datab[3:3]),
137
 
        .ena(clken),
138
 
        .inverta((~ add_sub)),
139
 
        .regout(wire_add_sub_cella_regout[3:3]));
140
 
        defparam
141
 
                add_sub_cella_3.cin_used = "true",
142
 
                add_sub_cella_3.lut_mask = "96e8",
143
 
                add_sub_cella_3.operation_mode = "arithmetic",
144
 
                add_sub_cella_3.sum_lutc_input = "cin",
145
 
                add_sub_cella_3.lpm_type = "stratix_lcell";
146
 
        stratix_lcell   add_sub_cella_4
147
 
        ( 
148
 
        .aclr(aclr),
149
 
        .cin(wire_add_sub_cella_3cout[0:0]),
150
 
        .clk(clock),
151
 
        .cout(wire_add_sub_cella_4cout[0:0]),
152
 
        .dataa(wire_add_sub_cella_dataa[4:4]),
153
 
        .datab(wire_add_sub_cella_datab[4:4]),
154
 
        .ena(clken),
155
 
        .inverta((~ add_sub)),
156
 
        .regout(wire_add_sub_cella_regout[4:4]));
157
 
        defparam
158
 
                add_sub_cella_4.cin_used = "true",
159
 
                add_sub_cella_4.lut_mask = "96e8",
160
 
                add_sub_cella_4.operation_mode = "arithmetic",
161
 
                add_sub_cella_4.sum_lutc_input = "cin",
162
 
                add_sub_cella_4.lpm_type = "stratix_lcell";
163
 
        stratix_lcell   add_sub_cella_5
164
 
        ( 
165
 
        .aclr(aclr),
166
 
        .cin(wire_add_sub_cella_4cout[0:0]),
167
 
        .clk(clock),
168
 
        .cout(wire_add_sub_cella_5cout[0:0]),
169
 
        .dataa(wire_add_sub_cella_dataa[5:5]),
170
 
        .datab(wire_add_sub_cella_datab[5:5]),
171
 
        .ena(clken),
172
 
        .inverta((~ add_sub)),
173
 
        .regout(wire_add_sub_cella_regout[5:5]));
174
 
        defparam
175
 
                add_sub_cella_5.cin_used = "true",
176
 
                add_sub_cella_5.lut_mask = "96e8",
177
 
                add_sub_cella_5.operation_mode = "arithmetic",
178
 
                add_sub_cella_5.sum_lutc_input = "cin",
179
 
                add_sub_cella_5.lpm_type = "stratix_lcell";
180
 
        stratix_lcell   add_sub_cella_6
181
 
        ( 
182
 
        .aclr(aclr),
183
 
        .cin(wire_add_sub_cella_5cout[0:0]),
184
 
        .clk(clock),
185
 
        .cout(wire_add_sub_cella_6cout[0:0]),
186
 
        .dataa(wire_add_sub_cella_dataa[6:6]),
187
 
        .datab(wire_add_sub_cella_datab[6:6]),
188
 
        .ena(clken),
189
 
        .inverta((~ add_sub)),
190
 
        .regout(wire_add_sub_cella_regout[6:6]));
191
 
        defparam
192
 
                add_sub_cella_6.cin_used = "true",
193
 
                add_sub_cella_6.lut_mask = "96e8",
194
 
                add_sub_cella_6.operation_mode = "arithmetic",
195
 
                add_sub_cella_6.sum_lutc_input = "cin",
196
 
                add_sub_cella_6.lpm_type = "stratix_lcell";
197
 
        stratix_lcell   add_sub_cella_7
198
 
        ( 
199
 
        .aclr(aclr),
200
 
        .cin(wire_add_sub_cella_6cout[0:0]),
201
 
        .clk(clock),
202
 
        .cout(wire_add_sub_cella_7cout[0:0]),
203
 
        .dataa(wire_add_sub_cella_dataa[7:7]),
204
 
        .datab(wire_add_sub_cella_datab[7:7]),
205
 
        .ena(clken),
206
 
        .inverta((~ add_sub)),
207
 
        .regout(wire_add_sub_cella_regout[7:7]));
208
 
        defparam
209
 
                add_sub_cella_7.cin_used = "true",
210
 
                add_sub_cella_7.lut_mask = "96e8",
211
 
                add_sub_cella_7.operation_mode = "arithmetic",
212
 
                add_sub_cella_7.sum_lutc_input = "cin",
213
 
                add_sub_cella_7.lpm_type = "stratix_lcell";
214
 
        stratix_lcell   add_sub_cella_8
215
 
        ( 
216
 
        .aclr(aclr),
217
 
        .cin(wire_add_sub_cella_7cout[0:0]),
218
 
        .clk(clock),
219
 
        .cout(wire_add_sub_cella_8cout[0:0]),
220
 
        .dataa(wire_add_sub_cella_dataa[8:8]),
221
 
        .datab(wire_add_sub_cella_datab[8:8]),
222
 
        .ena(clken),
223
 
        .inverta((~ add_sub)),
224
 
        .regout(wire_add_sub_cella_regout[8:8]));
225
 
        defparam
226
 
                add_sub_cella_8.cin_used = "true",
227
 
                add_sub_cella_8.lut_mask = "96e8",
228
 
                add_sub_cella_8.operation_mode = "arithmetic",
229
 
                add_sub_cella_8.sum_lutc_input = "cin",
230
 
                add_sub_cella_8.lpm_type = "stratix_lcell";
231
 
        stratix_lcell   add_sub_cella_9
232
 
        ( 
233
 
        .aclr(aclr),
234
 
        .cin(wire_add_sub_cella_8cout[0:0]),
235
 
        .clk(clock),
236
 
        .cout(wire_add_sub_cella_9cout[0:0]),
237
 
        .dataa(wire_add_sub_cella_dataa[9:9]),
238
 
        .datab(wire_add_sub_cella_datab[9:9]),
239
 
        .ena(clken),
240
 
        .inverta((~ add_sub)),
241
 
        .regout(wire_add_sub_cella_regout[9:9]));
242
 
        defparam
243
 
                add_sub_cella_9.cin_used = "true",
244
 
                add_sub_cella_9.lut_mask = "96e8",
245
 
                add_sub_cella_9.operation_mode = "arithmetic",
246
 
                add_sub_cella_9.sum_lutc_input = "cin",
247
 
                add_sub_cella_9.lpm_type = "stratix_lcell";
248
 
        stratix_lcell   add_sub_cella_10
249
 
        ( 
250
 
        .aclr(aclr),
251
 
        .cin(wire_add_sub_cella_9cout[0:0]),
252
 
        .clk(clock),
253
 
        .cout(wire_add_sub_cella_10cout[0:0]),
254
 
        .dataa(wire_add_sub_cella_dataa[10:10]),
255
 
        .datab(wire_add_sub_cella_datab[10:10]),
256
 
        .ena(clken),
257
 
        .inverta((~ add_sub)),
258
 
        .regout(wire_add_sub_cella_regout[10:10]));
259
 
        defparam
260
 
                add_sub_cella_10.cin_used = "true",
261
 
                add_sub_cella_10.lut_mask = "96e8",
262
 
                add_sub_cella_10.operation_mode = "arithmetic",
263
 
                add_sub_cella_10.sum_lutc_input = "cin",
264
 
                add_sub_cella_10.lpm_type = "stratix_lcell";
265
 
        stratix_lcell   add_sub_cella_11
266
 
        ( 
267
 
        .aclr(aclr),
268
 
        .cin(wire_add_sub_cella_10cout[0:0]),
269
 
        .clk(clock),
270
 
        .cout(wire_add_sub_cella_11cout[0:0]),
271
 
        .dataa(wire_add_sub_cella_dataa[11:11]),
272
 
        .datab(wire_add_sub_cella_datab[11:11]),
273
 
        .ena(clken),
274
 
        .inverta((~ add_sub)),
275
 
        .regout(wire_add_sub_cella_regout[11:11]));
276
 
        defparam
277
 
                add_sub_cella_11.cin_used = "true",
278
 
                add_sub_cella_11.lut_mask = "96e8",
279
 
                add_sub_cella_11.operation_mode = "arithmetic",
280
 
                add_sub_cella_11.sum_lutc_input = "cin",
281
 
                add_sub_cella_11.lpm_type = "stratix_lcell";
282
 
        stratix_lcell   add_sub_cella_12
283
 
        ( 
284
 
        .aclr(aclr),
285
 
        .cin(wire_add_sub_cella_11cout[0:0]),
286
 
        .clk(clock),
287
 
        .cout(wire_add_sub_cella_12cout[0:0]),
288
 
        .dataa(wire_add_sub_cella_dataa[12:12]),
289
 
        .datab(wire_add_sub_cella_datab[12:12]),
290
 
        .ena(clken),
291
 
        .inverta((~ add_sub)),
292
 
        .regout(wire_add_sub_cella_regout[12:12]));
293
 
        defparam
294
 
                add_sub_cella_12.cin_used = "true",
295
 
                add_sub_cella_12.lut_mask = "96e8",
296
 
                add_sub_cella_12.operation_mode = "arithmetic",
297
 
                add_sub_cella_12.sum_lutc_input = "cin",
298
 
                add_sub_cella_12.lpm_type = "stratix_lcell";
299
 
        stratix_lcell   add_sub_cella_13
300
 
        ( 
301
 
        .aclr(aclr),
302
 
        .cin(wire_add_sub_cella_12cout[0:0]),
303
 
        .clk(clock),
304
 
        .cout(wire_add_sub_cella_13cout[0:0]),
305
 
        .dataa(wire_add_sub_cella_dataa[13:13]),
306
 
        .datab(wire_add_sub_cella_datab[13:13]),
307
 
        .ena(clken),
308
 
        .inverta((~ add_sub)),
309
 
        .regout(wire_add_sub_cella_regout[13:13]));
310
 
        defparam
311
 
                add_sub_cella_13.cin_used = "true",
312
 
                add_sub_cella_13.lut_mask = "96e8",
313
 
                add_sub_cella_13.operation_mode = "arithmetic",
314
 
                add_sub_cella_13.sum_lutc_input = "cin",
315
 
                add_sub_cella_13.lpm_type = "stratix_lcell";
316
 
        stratix_lcell   add_sub_cella_14
317
 
        ( 
318
 
        .aclr(aclr),
319
 
        .cin(wire_add_sub_cella_13cout[0:0]),
320
 
        .clk(clock),
321
 
        .cout(wire_add_sub_cella_14cout[0:0]),
322
 
        .dataa(wire_add_sub_cella_dataa[14:14]),
323
 
        .datab(wire_add_sub_cella_datab[14:14]),
324
 
        .ena(clken),
325
 
        .inverta((~ add_sub)),
326
 
        .regout(wire_add_sub_cella_regout[14:14]));
327
 
        defparam
328
 
                add_sub_cella_14.cin_used = "true",
329
 
                add_sub_cella_14.lut_mask = "96e8",
330
 
                add_sub_cella_14.operation_mode = "arithmetic",
331
 
                add_sub_cella_14.sum_lutc_input = "cin",
332
 
                add_sub_cella_14.lpm_type = "stratix_lcell";
333
 
        stratix_lcell   add_sub_cella_15
334
 
        ( 
335
 
        .aclr(aclr),
336
 
        .cin(wire_add_sub_cella_14cout[0:0]),
337
 
        .clk(clock),
338
 
        .dataa(wire_add_sub_cella_dataa[15:15]),
339
 
        .datab(wire_add_sub_cella_datab[15:15]),
340
 
        .ena(clken),
341
 
        .inverta((~ add_sub)),
342
 
        .regout(wire_add_sub_cella_regout[15:15]));
343
 
        defparam
344
 
                add_sub_cella_15.cin_used = "true",
345
 
                add_sub_cella_15.lut_mask = "9696",
346
 
                add_sub_cella_15.operation_mode = "normal",
347
 
                add_sub_cella_15.sum_lutc_input = "cin",
348
 
                add_sub_cella_15.lpm_type = "stratix_lcell";
349
 
        assign
350
 
                wire_add_sub_cella_dataa = datab,
351
 
                wire_add_sub_cella_datab = dataa;
352
 
        stratix_lcell   strx_lcell1
353
 
        ( 
354
 
        .cout(wire_strx_lcell1_cout),
355
 
        .dataa(1'b0),
356
 
        .datab((~ add_sub)),
357
 
        .inverta((~ add_sub)));
358
 
        defparam
359
 
                strx_lcell1.cin_used = "false",
360
 
                strx_lcell1.lut_mask = "00cc",
361
 
                strx_lcell1.operation_mode = "arithmetic",
362
 
                strx_lcell1.lpm_type = "stratix_lcell";
363
 
        assign
364
 
                result = wire_add_sub_cella_regout;
365
 
endmodule //addsub16_add_sub_gp9
366
 
//VALID FILE
367
 
 
368
 
 
369
 
module addsub16 (
370
 
        add_sub,
371
 
        dataa,
372
 
        datab,
373
 
        clock,
374
 
        aclr,
375
 
        clken,
376
 
        result)/* synthesis synthesis_clearbox = 1 */;
377
 
 
378
 
        input     add_sub;
379
 
        input   [15:0]  dataa;
380
 
        input   [15:0]  datab;
381
 
        input     clock;
382
 
        input     aclr;
383
 
        input     clken;
384
 
        output  [15:0]  result;
385
 
 
386
 
        wire [15:0] sub_wire0;
387
 
        wire [15:0] result = sub_wire0[15:0];
388
 
 
389
 
        addsub16_add_sub_gp9    addsub16_add_sub_gp9_component (
390
 
                                .dataa (dataa),
391
 
                                .add_sub (add_sub),
392
 
                                .datab (datab),
393
 
                                .clken (clken),
394
 
                                .aclr (aclr),
395
 
                                .clock (clock),
396
 
                                .result (sub_wire0));
397
 
 
398
 
endmodule
399
 
 
400
 
// ============================================================
401
 
// CNX file retrieval info
402
 
// ============================================================
403
 
// Retrieval info: PRIVATE: nBit NUMERIC "16"
404
 
// Retrieval info: PRIVATE: Function NUMERIC "2"
405
 
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
406
 
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
407
 
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
408
 
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
409
 
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
410
 
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
411
 
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
412
 
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
413
 
// Retrieval info: PRIVATE: Latency NUMERIC "1"
414
 
// Retrieval info: PRIVATE: aclr NUMERIC "1"
415
 
// Retrieval info: PRIVATE: clken NUMERIC "1"
416
 
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
417
 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
418
 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
419
 
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
420
 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
421
 
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
422
 
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
423
 
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
424
 
// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub
425
 
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
426
 
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL dataa[15..0]
427
 
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL datab[15..0]
428
 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
429
 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
430
 
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
431
 
// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
432
 
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
433
 
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
434
 
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
435
 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
436
 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
437
 
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
438
 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all