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Viewing changes to usrp/fpga/sdr_lib/hb/ram16_2sum.v

  • Committer: Package Import Robot
  • Author(s): A. Maitland Bottoms
  • Date: 2012-02-26 21:26:16 UTC
  • mfrom: (1.1.4)
  • Revision ID: package-import@ubuntu.com-20120226212616-vsfkbi1158xshdql
Tags: 3.5.1-1
http://bugs.debian.org/642716
http://bugs.debian.org/645332
http://bugs.debian.org/394849
http://bugs.debian.org/616832
http://bugs.debian.org/590048
http://bugs.debian.org/642580
* new upstream version, re-packaged from scratch with modern tools
    closes: #642716, #645332, #394849, #616832, #590048, #642580,
    #647018, #557050, #559640, #631863
* CMake build

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usrp/fpga/sdr_lib/hb/ram16_2sum.v
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module ram16_2sum (input clock, input write, 
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                   input [3:0] wr_addr, input [15:0] wr_data,
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                   input [3:0] rd_addr1, input [3:0] rd_addr2,
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                   output reg [15:0] sum);
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   reg signed [15:0]      ram_array [0:15];
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   reg signed [15:0]      a,b;
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   wire signed [16:0]     sum_int;
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   always @(posedge clock)
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     if(write)
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       ram_array[wr_addr] <= #1 wr_data;
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   always @(posedge clock)
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     begin
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        a <= #1 ram_array[rd_addr1];
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        b <= #1 ram_array[rd_addr2];
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     end
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   assign sum_int = {a[15],a} + {b[15],b};
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   always @(posedge clock)
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     sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]);
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endmodule // ram16_2sum