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* Copyright 2007,2008,2009 Free Software Foundation, Inc.
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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#include "app_common_v2.h"
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#include "buffer_pool.h"
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#include "memcpy_wa.h"
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#include "print_rmon_regs.h"
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volatile bool link_is_up = false; // eth handler sets this
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int cpu_tx_buf_dest_port = PORT_ETH;
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// If this is non-zero, this dbsm could be writing to the ethernet
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dbsm_t *ac_could_be_sending_to_eth;
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static unsigned char exp_seqno __attribute__((unused)) = 0;
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sync_to_pps(const op_generic_t *p)
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timesync_regs->sync_on_next_pps = 1;
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//putstr("SYNC to PPS\n");
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sync_every_pps(const op_generic_t *p)
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timesync_regs->tick_control |= TSC_TRIGGER_EVERYPPS;
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timesync_regs->tick_control &= ~TSC_TRIGGER_EVERYPPS;
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config_mimo_cmd(const op_config_mimo_t *p)
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clocks_mimo_config(p->flags);
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set_reply_hdr(u2_eth_packet_t *reply_pkt, u2_eth_packet_t const *cmd_pkt)
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reply_pkt->ehdr.dst = cmd_pkt->ehdr.src;
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reply_pkt->ehdr.ethertype = U2_ETHERTYPE;
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reply_pkt->thdr.flags = 0;
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reply_pkt->thdr.fifo_status = 0; // written by protocol engine
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reply_pkt->thdr.seqno = 0; // written by protocol engine
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reply_pkt->thdr.ack = 0; // written by protocol engine
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u2p_set_word0(&reply_pkt->fixed, 0, CONTROL_CHAN);
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reply_pkt->fixed.timestamp = timer_regs->time;
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send_reply(unsigned char *reply, size_t reply_len)
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// wait for buffer to become idle
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hal_set_leds(0x4, 0x4);
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while((buffer_pool_status->status & BPS_IDLE(CPU_TX_BUF)) == 0)
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hal_set_leds(0x0, 0x4);
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// copy reply into CPU_TX_BUF
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memcpy_wa(buffer_ram(CPU_TX_BUF), reply, reply_len);
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// wait until nobody else is sending to the ethernet
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if (ac_could_be_sending_to_eth){
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hal_set_leds(0x8, 0x8);
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dbsm_wait_for_opening(ac_could_be_sending_to_eth);
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hal_set_leds(0x0, 0x8);
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printf("sending_reply to port %d, len = %d\n", cpu_tx_buf_dest_port, (int)reply_len);
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print_buffer(buffer_ram(CPU_TX_BUF), reply_len/4);
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bp_send_from_buf(CPU_TX_BUF, cpu_tx_buf_dest_port, 1, 0, reply_len/4);
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// wait for it to complete (not long, it's a small pkt)
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while((buffer_pool_status->status & (BPS_DONE(CPU_TX_BUF) | BPS_ERROR(CPU_TX_BUF))) == 0)
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bp_clear_buf(CPU_TX_BUF);
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op_id_cmd(const op_generic_t *p,
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void *reply_payload, size_t reply_payload_space)
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op_id_reply_t *r = (op_id_reply_t *) reply_payload;
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if (reply_payload_space < sizeof(*r)) // no room
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// Build reply subpacket
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r->opcode = OP_ID_REPLY;
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r->len = sizeof(op_id_reply_t);
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r->addr = *ethernet_mac_addr();
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r->hw_rev = (u2_hw_rev_major << 8) | u2_hw_rev_minor;
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// r->fpga_md5sum = ; // FIXME
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// r->sw_md5sum = ; // FIXME
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config_tx_v2_cmd(const op_config_tx_v2_t *p,
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void *reply_payload, size_t reply_payload_space)
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op_config_tx_reply_v2_t *r = (op_config_tx_reply_v2_t *) reply_payload;
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if (reply_payload_space < sizeof(*r))
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struct tune_result tune_result;
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memset(&tune_result, 0, sizeof(tune_result));
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if (p->valid & CFGV_GAIN){
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ok &= db_set_gain(tx_dboard, p->gain);
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if (p->valid & CFGV_FREQ){
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bool was_streaming = is_streaming();
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u2_fxpt_freq_t f = u2_fxpt_freq_from_hilo(p->freq_hi, p->freq_lo);
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bool tune_ok = db_tune(tx_dboard, f, &tune_result);
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print_tune_result("Tx", tune_ok, f, &tune_result);
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if (p->valid & CFGV_INTERP_DECIM){
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int interp = p->interp;
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interp = interp >> 1;
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interp = interp >> 1;
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if (interp < MIN_CIC_INTERP || interp > MAX_CIC_INTERP)
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dsp_tx_regs->interp_rate = (hb1<<9) | (hb2<<8) | interp;
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// printf("Interp: %d, register %d\n", p->interp, (hb1<<9) | (hb2<<8) | interp);
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if (p->valid & CFGV_SCALE_IQ){
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dsp_tx_regs->scale_iq = p->scale_iq;
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// Build reply subpacket
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r->opcode = OP_CONFIG_TX_REPLY_V2;
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r->inverted = tune_result.inverted;
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r->baseband_freq_hi = u2_fxpt_freq_hi(tune_result.baseband_freq);
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r->baseband_freq_lo = u2_fxpt_freq_lo(tune_result.baseband_freq);
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r->duc_freq_hi = u2_fxpt_freq_hi(tune_result.dxc_freq);
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r->duc_freq_lo = u2_fxpt_freq_lo(tune_result.dxc_freq);
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r->residual_freq_hi = u2_fxpt_freq_hi(tune_result.residual_freq);
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r->residual_freq_lo = u2_fxpt_freq_lo(tune_result.residual_freq);
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config_rx_v2_cmd(const op_config_rx_v2_t *p,
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void *reply_payload, size_t reply_payload_space)
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op_config_rx_reply_v2_t *r = (op_config_rx_reply_v2_t *) reply_payload;
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if (reply_payload_space < sizeof(*r))
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struct tune_result tune_result;
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memset(&tune_result, 0, sizeof(tune_result));
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if (p->valid & CFGV_GAIN){
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ok &= db_set_gain(rx_dboard, p->gain);
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if (p->valid & CFGV_FREQ){
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bool was_streaming = is_streaming();
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u2_fxpt_freq_t f = u2_fxpt_freq_from_hilo(p->freq_hi, p->freq_lo);
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bool tune_ok = db_tune(rx_dboard, f, &tune_result);
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print_tune_result("Rx", tune_ok, f, &tune_result);
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if (p->valid & CFGV_INTERP_DECIM){
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int decim = p->decim;
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if (decim < MIN_CIC_DECIM || decim > MAX_CIC_DECIM)
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dsp_rx_regs->decim_rate = (hb1<<9) | (hb2<<8) | decim;
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// printf("Decim: %d, register %d\n", p->decim, (hb1<<9) | (hb2<<8) | decim);
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if (p->valid & CFGV_SCALE_IQ){
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dsp_rx_regs->scale_iq = p->scale_iq;
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// Build reply subpacket
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r->opcode = OP_CONFIG_RX_REPLY_V2;
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r->inverted = tune_result.inverted;
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r->baseband_freq_hi = u2_fxpt_freq_hi(tune_result.baseband_freq);
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r->baseband_freq_lo = u2_fxpt_freq_lo(tune_result.baseband_freq);
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r->ddc_freq_hi = u2_fxpt_freq_hi(tune_result.dxc_freq);
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r->ddc_freq_lo = u2_fxpt_freq_lo(tune_result.dxc_freq);
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r->residual_freq_hi = u2_fxpt_freq_hi(tune_result.residual_freq);
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r->residual_freq_lo = u2_fxpt_freq_lo(tune_result.residual_freq);
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read_time_cmd(const op_generic_t *p,
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void *reply_payload, size_t reply_payload_space)
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op_read_time_reply_t *r = (op_read_time_reply_t *) reply_payload;
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if (reply_payload_space < sizeof(*r))
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r->opcode = OP_READ_TIME_REPLY;
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r->time = timer_regs->time;
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fill_db_info(u2_db_info_t *p, const struct db_base *db)
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p->freq_min_hi = u2_fxpt_freq_hi(db->freq_min);
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p->freq_min_lo = u2_fxpt_freq_lo(db->freq_min);
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p->freq_max_hi = u2_fxpt_freq_hi(db->freq_max);
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p->freq_max_lo = u2_fxpt_freq_lo(db->freq_max);
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p->gain_min = db->gain_min;
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p->gain_max = db->gain_max;
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p->gain_step_size = db->gain_step_size;
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dboard_info_cmd(const op_generic_t *p,
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void *reply_payload, size_t reply_payload_space)
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op_dboard_info_reply_t *r = (op_dboard_info_reply_t *) reply_payload;
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if (reply_payload_space < sizeof(*r))
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r->opcode = OP_DBOARD_INFO_REPLY;
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fill_db_info(&r->tx_db_info, tx_dboard);
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fill_db_info(&r->rx_db_info, rx_dboard);
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peek_cmd(const op_peek_t *p,
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void *reply_payload, size_t reply_payload_space)
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op_generic_t *r = (op_generic_t *) reply_payload;
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//putstr("peek: addr="); puthex32(p->addr);
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//printf(" bytes=%u\n", p->bytes);
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if ((reply_payload_space < (sizeof(*r) + p->bytes)) ||
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p->bytes > MAX_SUBPKT_LEN - sizeof(op_generic_t)) {
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putstr("peek: insufficient reply packet space\n");
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return 0; // FIXME do partial read?
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r->opcode = OP_PEEK_REPLY;
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r->len = sizeof(*r)+p->bytes;
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memcpy_wa(reply_payload+sizeof(*r), (void *)p->addr, p->bytes);
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poke_cmd(const op_poke_t *p)
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int bytes = p->len - sizeof(*p);
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//putstr("poke: addr="); puthex32(p->addr);
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//printf(" bytes=%u\n", bytes);
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uint8_t *src = (uint8_t *)p + sizeof(*p);
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memcpy_wa((void *)p->addr, src, bytes);
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set_lo_offset_cmd(const op_freq_t *p)
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u2_fxpt_freq_t f = u2_fxpt_freq_from_hilo(p->freq_hi, p->freq_lo);
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if (p->opcode == OP_SET_TX_LO_OFFSET)
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return db_set_lo_offset(tx_dboard, f);
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return db_set_lo_offset(rx_dboard, f);
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gpio_read_cmd(const op_gpio_t *p,
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void *reply_payload, size_t reply_payload_space)
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op_gpio_read_reply_t *r = (op_gpio_read_reply_t *) reply_payload;
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if (reply_payload_space < sizeof(*r)) // no room
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// Build reply subpacket
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r->opcode = OP_GPIO_READ_REPLY;
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r->len = sizeof(op_gpio_read_reply_t);
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r->value = hal_gpio_read(p->bank);
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generic_reply(const op_generic_t *p,
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void *reply_payload, size_t reply_payload_space,
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op_generic_t *r = (op_generic_t *) reply_payload;
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if (reply_payload_space < sizeof(*r))
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r->opcode = p->opcode | OP_REPLY_BIT;
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add_eop(void *reply_payload, size_t reply_payload_space)
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op_generic_t *r = (op_generic_t *) reply_payload;
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if (reply_payload_space < sizeof(*r))
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handle_control_chan_frame(u2_eth_packet_t *pkt, size_t len)
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unsigned char reply[sizeof(u2_eth_packet_t) + 4 * sizeof(u2_subpkt_t)] _AL4;
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unsigned char *reply_payload = &reply[sizeof(u2_eth_packet_t)];
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int reply_payload_space = sizeof(reply) - sizeof(u2_eth_packet_t);
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memset(reply, 0, sizeof(reply));
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set_reply_hdr((u2_eth_packet_t *) reply, pkt);
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// point to beginning of payload (subpackets)
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unsigned char *payload = ((unsigned char *) pkt) + sizeof(u2_eth_packet_t);
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int payload_len = len - sizeof(u2_eth_packet_t);
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size_t subpktlen = 0;
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while (payload_len >= sizeof(op_generic_t)){
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const op_generic_t *gp = (const op_generic_t *) payload;
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// printf("\nopcode = %d\n", gp->opcode);
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case OP_EOP: // end of subpackets
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goto end_of_subpackets;
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subpktlen = op_id_cmd(gp, reply_payload, reply_payload_space);
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case OP_CONFIG_TX_V2:
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subpktlen = config_tx_v2_cmd((op_config_tx_v2_t *) payload, reply_payload, reply_payload_space);
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case OP_CONFIG_RX_V2:
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subpktlen = config_rx_v2_cmd((op_config_rx_v2_t *) payload, reply_payload, reply_payload_space);
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case OP_START_RX_STREAMING:
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start_rx_streaming_cmd(&pkt->ehdr.src, (op_start_rx_streaming_t *) payload);
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case OP_BURN_MAC_ADDR:
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ok = ethernet_set_mac_addr(&((op_burn_mac_addr_t *)payload)->addr);
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ok = config_mimo_cmd((op_config_mimo_t *) payload);
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subpktlen = read_time_cmd(gp, reply_payload, reply_payload_space);
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subpktlen = dboard_info_cmd(gp, reply_payload, reply_payload_space);
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sync_to_pps((op_generic_t *) payload);
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subpktlen = peek_cmd((op_peek_t *)payload, reply_payload, reply_payload_space);
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ok = poke_cmd((op_poke_t *)payload);
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case OP_SET_TX_LO_OFFSET:
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case OP_SET_RX_LO_OFFSET:
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ok = set_lo_offset_cmd((op_freq_t *)payload);
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case OP_SYNC_EVERY_PPS:
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ok = sync_every_pps((op_generic_t *) payload);
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case OP_GPIO_SET_DDR:
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hal_gpio_set_ddr(((op_gpio_t *)payload)->bank,
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((op_gpio_t *)payload)->value,
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((op_gpio_t *)payload)->mask);
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case OP_GPIO_SET_SELS:
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hal_gpio_set_sels(((op_gpio_set_sels_t *)payload)->bank,
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(char *)(&((op_gpio_set_sels_t *)payload)->sels));
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subpktlen = gpio_read_cmd((op_gpio_t *) payload, reply_payload, reply_payload_space);
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hal_gpio_write(((op_gpio_t *)payload)->bank,
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((op_gpio_t *)payload)->value,
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((op_gpio_t *)payload)->mask);
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dsp_rx_regs->gpio_stream_enable = (uint32_t)((op_gpio_t *)payload)->value;
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// Add new opcode handlers here
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subpktlen = generic_reply(gp, reply_payload, reply_payload_space, ok);
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printf("app_common_v2: unhandled opcode = %d\n", gp->opcode);
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int t = (gp->len + 3) & ~3; // bump to a multiple of 4
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subpktlen = (subpktlen + 3) & ~3; // bump to a multiple of 4
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reply_payload += subpktlen;
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reply_payload_space -= subpktlen;
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// add the EOP marker
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subpktlen = add_eop(reply_payload, reply_payload_space);
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subpktlen = (subpktlen + 3) & ~3; // bump to a multiple of 4
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reply_payload += subpktlen;
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reply_payload_space -= subpktlen;
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send_reply(reply, reply_payload - reply);
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* Called when an ethernet packet is received.
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* Return true if we handled it here, otherwise
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* it'll be passed on to the DSP Tx pipe
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eth_pkt_inspector(dbsm_t *sm, int bufno)
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u2_eth_packet_t *pkt = (u2_eth_packet_t *) buffer_ram(bufno);
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size_t byte_len = (buffer_pool_status->last_line[bufno] - 3) * 4;
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//static size_t last_len = 0;
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// hal_toggle_leds(0x1);
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// inspect rcvd frame and figure out what do do.
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if (pkt->ehdr.ethertype != U2_ETHERTYPE)
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return true; // ignore, probably bogus PAUSE frame from MAC
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int chan = u2p_chan(&pkt->fixed);
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handle_control_chan_frame(pkt, byte_len);
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return true; // we handled the packet
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if (byte_len != last_len){
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printf("Len: %d last: %d\n", byte_len, last_len);
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if((pkt->thdr.seqno) == exp_seqno){
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//printf("S%d %d ",exp_seqno,pkt->thdr.seqno);
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exp_seqno = pkt->thdr.seqno + 1;
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return false; // pass it on to Tx DSP
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* Called when eth phy state changes (w/ interrupts disabled)
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link_changed_callback(int speed)
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link_is_up = speed != 0;
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hal_set_leds(link_is_up ? LED_RJ45 : 0x0, LED_RJ45);
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printf("\neth link changed: speed = %d\n", speed);
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print_tune_result(char *msg, bool tune_ok,
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u2_fxpt_freq_t target_freq, struct tune_result *r)
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printf("db_tune %s %s\n", msg, tune_ok ? "true" : "false");
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putstr(" target_freq "); print_fxpt_freq(target_freq); newline();
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putstr(" baseband_freq "); print_fxpt_freq(r->baseband_freq); newline();
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putstr(" dxc_freq "); print_fxpt_freq(r->dxc_freq); newline();
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putstr(" residual_freq "); print_fxpt_freq(r->residual_freq); newline();
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printf(" inverted %s\n", r->inverted ? "true" : "false");