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* EM - Execution Monitor.
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* Copyright (C) 2006-2013 Oracle Corporation
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* This file is part of VirtualBox Open Source Edition (OSE), as
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* available from http://www.virtualbox.org. This file is free software;
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* you can redistribute it and/or modify it under the terms of the GNU
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* General Public License (GPL) as published by the Free Software
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* Foundation, in version 2 as it comes in the "COPYING" file of the
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* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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* The contents of this file may alternatively be used under the terms
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* of the Common Development and Distribution License Version 1.0
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* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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* VirtualBox OSE distribution, in which case the provisions of the
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* CDDL are applicable instead of those of the GPL.
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* You may elect to license modified versions of this file under the
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* terms and conditions of either the GPL or the CDDL or both.
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#ifndef ___VBox_vmm_em_h
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#define ___VBox_vmm_em_h
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#include <VBox/types.h>
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#include <VBox/vmm/trpm.h>
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/** @defgroup grp_em The Execution Monitor / Manager API
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/** Enable to allow V86 code to run in raw mode. */
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* The Execution Manager State.
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* @remarks This is used in the saved state!
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/** Not yet started. */
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/** Raw-mode execution. */
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/** Hardware accelerated raw-mode execution. */
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/** Executing in IEM. */
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/** Recompiled mode execution. */
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/** Execution is halted. (waiting for interrupt) */
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/** Application processor execution is halted. (waiting for startup IPI (SIPI)) */
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/** Execution is suspended. */
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/** The VM is terminating. */
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/** Guest debug event from raw-mode is being processed. */
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EMSTATE_DEBUG_GUEST_RAW,
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/** Guest debug event from hardware accelerated mode is being processed. */
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EMSTATE_DEBUG_GUEST_HM,
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/** Guest debug event from interpreted execution mode is being processed. */
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EMSTATE_DEBUG_GUEST_IEM,
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/** Guest debug event from recompiled-mode is being processed. */
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EMSTATE_DEBUG_GUEST_REM,
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/** Hypervisor debug event being processed. */
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/** The VM has encountered a fatal error. (And everyone is panicing....) */
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EMSTATE_GURU_MEDITATION,
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/** Executing in IEM, falling back on REM if we cannot switch back to HM or
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* RAW after a short while. */
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/** Just a hack to ensure that we get a 32-bit integer. */
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EMSTATE_MAKE_32BIT_HACK = 0x7fffffff
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* EMInterpretInstructionCPU execution modes.
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/** Only supervisor code (CPL=0). */
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EMCODETYPE_SUPERVISOR,
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/** User-level code only. */
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/** Supervisor and user-level code (use with great care!). */
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/** Just a hack to ensure that we get a 32-bit integer. */
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EMCODETYPE_32BIT_HACK = 0x7fffffff
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VMM_INT_DECL(EMSTATE) EMGetState(PVMCPU pVCpu);
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VMM_INT_DECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState);
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/** @name Callback handlers for instruction emulation functions.
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* These are placed here because IOM wants to use them as well.
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typedef DECLCALLBACK(uint32_t) FNEMULATEPARAM2UINT32(void *pvParam1, uint64_t val2);
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typedef FNEMULATEPARAM2UINT32 *PFNEMULATEPARAM2UINT32;
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typedef DECLCALLBACK(uint32_t) FNEMULATEPARAM2(void *pvParam1, size_t val2);
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typedef FNEMULATEPARAM2 *PFNEMULATEPARAM2;
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typedef DECLCALLBACK(uint32_t) FNEMULATEPARAM3(void *pvParam1, uint64_t val2, size_t val3);
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typedef FNEMULATEPARAM3 *PFNEMULATEPARAM3;
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typedef DECLCALLBACK(int) FNEMULATELOCKPARAM2(void *pvParam1, uint64_t val2, RTGCUINTREG32 *pf);
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typedef FNEMULATELOCKPARAM2 *PFNEMULATELOCKPARAM2;
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typedef DECLCALLBACK(int) FNEMULATELOCKPARAM3(void *pvParam1, uint64_t val2, size_t cb, RTGCUINTREG32 *pf);
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typedef FNEMULATELOCKPARAM3 *PFNEMULATELOCKPARAM3;
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* Checks if raw ring-3 execute mode is enabled.
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* @returns true if enabled.
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* @returns false if disabled.
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* @param pVM The VM to operate on.
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#define EMIsRawRing3Enabled(pVM) (!(pVM)->fRecompileUser)
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* Checks if raw ring-0 execute mode is enabled.
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* @returns true if enabled.
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* @returns false if disabled.
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* @param pVM The VM to operate on.
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#define EMIsRawRing0Enabled(pVM) (!(pVM)->fRecompileSupervisor)
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#ifdef VBOX_WITH_RAW_RING1
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* Checks if raw ring-1 execute mode is enabled.
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* @returns true if enabled.
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* @returns false if disabled.
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* @param pVM The VM to operate on.
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# define EMIsRawRing1Enabled(pVM) ((pVM)->fRawRing1Enabled)
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# define EMIsRawRing1Enabled(pVM) false
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* Checks if execution with hardware assisted virtualization is enabled.
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* @returns true if enabled.
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* @returns false if disabled.
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* @param pVM The VM to operate on.
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#define EMIsHwVirtExecutionEnabled(pVM) (!(pVM)->fRecompileSupervisor && !(pVM)->fRecompileUser)
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* Checks if execution of supervisor code should be done in the
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* @returns true if enabled.
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* @returns false if disabled.
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* @param pVM The VM to operate on.
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#define EMIsSupervisorCodeRecompiled(pVM) ((pVM)->fRecompileSupervisor)
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VMMDECL(void) EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC);
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VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu);
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VMM_INT_DECL(int) EMInterpretDisasCurrent(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pCpu, unsigned *pcbInstr);
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VMM_INT_DECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
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PDISCPUSTATE pDISState, unsigned *pcbInstr);
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VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPU pVCpu, PCPUMCTXCORE pCoreCtx, RTGCPTR pvFault);
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VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionEx(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbWritten);
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VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstructionDisasState(PVMCPU pVCpu, PDISCPUSTATE pDis, PCPUMCTXCORE pCoreCtx,
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RTGCPTR pvFault, EMCODETYPE enmCodeType);
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VMM_INT_DECL(int) EMInterpretIretV86ForPatm(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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VMM_INT_DECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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VMM_INT_DECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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VMM_INT_DECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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VMM_INT_DECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
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VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC);
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VMM_INT_DECL(VBOXSTRICTRC) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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VMM_INT_DECL(int) EMInterpretMonitor(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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VMM_INT_DECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen);
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VMM_INT_DECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx);
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VMM_INT_DECL(int) EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen);
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VMM_INT_DECL(int) EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx);
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VMM_INT_DECL(int) EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data);
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VMM_INT_DECL(int) EMInterpretCLTS(PVM pVM, PVMCPU pVCpu);
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VMM_INT_DECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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VMM_INT_DECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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VMM_INT_DECL(bool) EMShouldContinueAfterHalt(PVMCPU pVCpu, PCPUMCTX pCtx);
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VMM_INT_DECL(bool) EMMonitorWaitShouldContinue(PVMCPU pVCpu, PCPUMCTX pCtx);
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VMM_INT_DECL(int) EMMonitorWaitPrepare(PVMCPU pVCpu, uint64_t rax, uint64_t rcx, uint64_t rdx, RTGCPHYS GCPhys);
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VMM_INT_DECL(int) EMMonitorWaitPerform(PVMCPU pVCpu, uint64_t rax, uint64_t rcx);
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/** @name Assembly routines
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VMMDECL(uint32_t) EMEmulateCmp(uint32_t u32Param1, uint64_t u64Param2, size_t cb);
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VMMDECL(uint32_t) EMEmulateAnd(void *pvParam1, uint64_t u64Param2, size_t cb);
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VMMDECL(uint32_t) EMEmulateInc(void *pvParam1, size_t cb);
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VMMDECL(uint32_t) EMEmulateDec(void *pvParam1, size_t cb);
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VMMDECL(uint32_t) EMEmulateOr(void *pvParam1, uint64_t u64Param2, size_t cb);
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VMMDECL(int) EMEmulateLockOr(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
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VMMDECL(uint32_t) EMEmulateXor(void *pvParam1, uint64_t u64Param2, size_t cb);
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VMMDECL(int) EMEmulateLockXor(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
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VMMDECL(uint32_t) EMEmulateAdd(void *pvParam1, uint64_t u64Param2, size_t cb);
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VMMDECL(int) EMEmulateLockAnd(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
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VMMDECL(uint32_t) EMEmulateSub(void *pvParam1, uint64_t u64Param2, size_t cb);
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VMMDECL(uint32_t) EMEmulateAdcWithCarrySet(void *pvParam1, uint64_t u64Param2, size_t cb);
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VMMDECL(uint32_t) EMEmulateBtr(void *pvParam1, uint64_t u64Param2);
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VMMDECL(int) EMEmulateLockBtr(void *pvParam1, uint64_t u64Param2, RTGCUINTREG32 *pf);
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VMMDECL(uint32_t) EMEmulateBts(void *pvParam1, uint64_t u64Param2);
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VMMDECL(uint32_t) EMEmulateBtc(void *pvParam1, uint64_t u64Param2);
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VMMDECL(uint32_t) EMEmulateCmpXchg(void *pvParam1, uint64_t *pu32Param2, uint64_t u32Param3, size_t cbSize);
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VMMDECL(uint32_t) EMEmulateLockCmpXchg(void *pvParam1, uint64_t *pu64Param2, uint64_t u64Param3, size_t cbSize);
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VMMDECL(uint32_t) EMEmulateCmpXchg8b(void *pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX);
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VMMDECL(uint32_t) EMEmulateLockCmpXchg8b(void *pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX);
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VMMDECL(uint32_t) EMEmulateXAdd(void *pvParam1, void *pvParam2, size_t cbOp);
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VMMDECL(uint32_t) EMEmulateLockXAdd(void *pvParam1, void *pvParam2, size_t cbOp);
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/** @name REM locking routines
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VMMDECL(void) EMRemUnlock(PVM pVM);
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VMMDECL(void) EMRemLock(PVM pVM);
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VMMDECL(bool) EMRemIsLockOwner(PVM pVM);
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VMM_INT_DECL(int) EMRemTryLock(PVM pVM);
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/** @name EM_ONE_INS_FLAGS_XXX - flags for EMR3HmSingleInstruction (et al).
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/** Return when CS:RIP changes or some other important event happens.
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* This means running whole REP and LOOP $ sequences for instance. */
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#define EM_ONE_INS_FLAGS_RIP_CHANGE RT_BIT_32(0)
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/** Mask of valid flags. */
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#define EM_ONE_INS_FLAGS_MASK UINT32_C(0x00000001)
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/** @defgroup grp_em_r3 The EM Host Context Ring-3 API
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* Command argument for EMR3RawSetMode().
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* It's possible to extend this interface to change several
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* execution modes at once should the need arise.
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typedef enum EMEXECPOLICY
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/** The customary invalid zero entry. */
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EMEXECPOLICY_INVALID = 0,
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/** Whether to recompile ring-0 code or execute it in raw/hm. */
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EMEXECPOLICY_RECOMPILE_RING0,
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/** Whether to recompile ring-3 code or execute it in raw/hm. */
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EMEXECPOLICY_RECOMPILE_RING3,
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/** Whether to only use IEM for execution. */
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EMEXECPOLICY_IEM_ALL,
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/** End of valid value (not included). */
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/** The customary 32-bit type blowup. */
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EMEXECPOLICY_32BIT_HACK = 0x7fffffff
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VMMR3DECL(int) EMR3SetExecutionPolicy(PUVM pUVM, EMEXECPOLICY enmPolicy, bool fEnforce);
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VMMR3DECL(int) EMR3QueryExecutionPolicy(PUVM pUVM, EMEXECPOLICY enmPolicy, bool *pfEnforced);
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VMMR3_INT_DECL(int) EMR3Init(PVM pVM);
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VMMR3_INT_DECL(void) EMR3Relocate(PVM pVM);
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VMMR3_INT_DECL(void) EMR3ResetCpu(PVMCPU pVCpu);
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VMMR3_INT_DECL(void) EMR3Reset(PVM pVM);
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VMMR3_INT_DECL(int) EMR3Term(PVM pVM);
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VMMR3DECL(DECLNORETURN(void)) EMR3FatalError(PVMCPU pVCpu, int rc);
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VMMR3_INT_DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu);
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VMMR3_INT_DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu);
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VMMR3_INT_DECL(int) EMR3NotifyResume(PVM pVM);
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VMMR3_INT_DECL(int) EMR3NotifySuspend(PVM pVM);
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VMMR3_INT_DECL(VBOXSTRICTRC) EMR3HmSingleInstruction(PVM pVM, PVMCPU pVCpu, uint32_t fFlags);
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#endif /* IN_RING3 */