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Subj: H316 Simulator Usage
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The following copyright notice applies to both the SIMH source and binary:
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Original code published in 1993-2004, written by Robert M Supnik
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Copyright (c) 1993-2004, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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This memorandum documents the Honeywell 316/516 simulator.
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The H316 requires the following files:
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The Honeywell 316/516 simulator is configured as follows:
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CPU H316/H516 CPU with 16/32KW memory
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PTR 316/516-50 paper tape reader
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PTP 316/516-52 paper tape punch
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TTY 316/516-33 console terminal
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CLK 316/516-12 real time clock
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LPT 316/516 line printer
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FHD 4400 fixed head disk
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DP 4623/4653/4720 disk pack controller with eight drives
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MT 4100 seven track magtape with four drives
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The H316/H516 simulator implements several unique stop conditions:
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- decode of an undefined instruction, and STOP_INST is et
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- reference to an undefined I/O device, and STOP_DEV is set
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- more than INDMAX indirect references are detected during
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memory reference address decoding
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- DMA/DMC direction does not agree with I/O device operation
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- a write operation is initiated on a write locked magtape
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unit (hangs the real system)
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- a disk write overruns the specified record size (destroys
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the rest of the track on the real system)
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- a disk track has an illegal format
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The H316/H516 loader is not implemented.
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CPU options include choice of instruction set, memory size, DMC option,
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and number of DMA channels.
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SET CPU HSA high speed arithmetic instructions
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SET CPU NOHSA no high speed arithmetic instructions
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SET CPU 4K set memory size = 4K
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SET CPU 8K set memory size = 8K
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SET CPU 12K set memory size = 12K
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SET CPU 16K set memory size = 16K
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SET CPU 24K set memory size = 24K
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SET CPU 32K set memory size = 32K
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SET CPU DMC enable DMC option
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SET CPU NODMC disable DMC option
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SET CPU DMA=n set number of DMA channels to n (0-4)
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If memory size is being reduced, and the memory being truncated contains
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non-zero data, the simulator asks for confirmation. Data in the truncated
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portion of memory is lost. Initial memory size is 32K. The HSA and DMC
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options are enabled, and four DMA channels are configured.
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The CPU includes special show commands to display the state of the DMA
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SHOW CPU DMAn show DMA channel n
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CPU registers include the visible state of the processor as well as the
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control registers for the interrupt system.
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PME 1 previous mode extend flag
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EXT_OFF 1 extend off pending flag
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DP 1 double precision flag
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SS1..4 1 sense switches 1..4
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ION 1 interrupts enabled
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INODEF 1 interrupts not deferred
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INTREQ 16 interrupt requests
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DEVRDY 16 device ready flags (read only)
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DEVENB 16 device interrupt enable flags (read only)
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CHREQ 20 DMA/DMC channel requests
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DMAAD[0:3] 16 DMA channel current address, channels 1-4
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DMAWC[0:3] 15 DMA channel word count, channels 1-4
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DMAEOR[0:3] 1 DMA end of range flag, channels 1-4
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STOP_INST 1 stop on undefined instruction
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STOP_DEV 1 stop on undefined device
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INDMAX 1 indirect address limit
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PCQ[0:63] 15 PC prior to last JMP, JSB, or interrupt;
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most recent PC change first
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WRU 8 interrupt character
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2.2 Programmed I/O Devices
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2.2.1 316/516-50 Paper Tape Reader (PTR)
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The paper tape reader (PTR) reads data from a disk file. The POS
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register specifies the number of the next data item to be read.
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Thus, by changing POS, the user can backspace or advance the reader.
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The paper tape reader supports the BOOT command. BOOT PTR copies the
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absolute binary loader into memory and starts it running.
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The paper tape reader implements these registers:
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BUF 8 last data item processed
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INTREQ 1 device interrupt request
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ENABLE 1 device interrupts enabled
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POS 32 position in the input or output file
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TIME 24 time from I/O initiation to interrupt
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STOP_IOE 1 stop on I/O error
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Error handling is as follows:
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error STOP_IOE processed as
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not attached 1 report error and stop
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end of file 1 report error and stop
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0 out of tape or paper
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OS I/O error x report error and stop
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2.2.2 316/516-52 Paper Tape Punch (PTP)
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The paper tape punch (PTP) writes data to a disk file. The POS
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register specifies the number of the next data item to be written.
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Thus, by changing POS, the user can backspace or advance the punch.
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The paper tape punch implements these registers:
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BUF 8 last data item processed
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INTREQ 1 device interrupt request
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ENABLE 1 device interrupts enabled
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POWER 1 device powered up
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POS 32 position in the input or output file
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TIME 24 time from I/O initiation to interrupt
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PWRTIME 24 time from I/O request to power up
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STOP_IOE 1 stop on I/O error
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Error handling is as follows:
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error STOP_IOE processed as
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not attached 1 report error and stop
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OS I/O error x report error and stop
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2.2.3 316/516-33 Console Teletype (TTY)
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The Teletype units (TTY0, TTY1) can be set to one of three modes:
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KSR, 7B, or 8B. In KSR mode, lower case input and output characters
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are automatically converted to upper case, and the high order bit is
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forced to one on input. In 7B mode, input and output characters are
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masked to 7 bits. In 8B mode, characters are not modified. Changing
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the mode of either unit changes both. The default mode is KSR.
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The Teletype reads from the console keyboard and writes to the
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simulator console window. It implements these registers:
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BUF 8 last data item processed
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MODE 1 read/write mode
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INTREQ 1 device interrupt request
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ENABLE 1 device interrupts enabled
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KPOS 32 number of characters input
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KTIME 24 keyboard polling interval
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TPOS 32 number of characters output
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TTIME 24 time from I/O initiation to interrupt
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2.2.4 316/516-12 Real Time Clock (CLK)
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The real time clock (CLK) frequency can be adjusted as follows:
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SET CLK 60HZ set frequency to 60Hz
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SET CLK 50HZ set frequency to 50Hz
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The clock implements these registers:
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INTREQ 1 device interrupt request
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ENABLE 1 device interrupts enabled
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TIME 24 clock interval
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The real-time clock autocalibrates; the clock interval is adjusted up or
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down so that the clock tracks actual elapsed time.
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2.3 316/516 Line Printer (LPT)
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The line printer (LPT) writes data to a disk file. The POS register
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specifies the number of the next data item to be written. Thus,
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by changing POS, the user can backspace or advance the printer.
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The line printer can be connected to the IO bus, a DMC channel, or
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SET LPT IOBUS connect to IO bus
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SET LPT DMC=n connect to DMC channel n (1-16)
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SET LPT DMA=n connect to DMA channel n (1-4)
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By default, the line printer is connected to the IO bus.
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The line printer implements these registers:
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WDPOS 6 word position in current scan
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DRPOS 6 drum position
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CRPOS 1 carriage position
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PRDN 1 print done flag
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EOR 1 (DMA/DMC) end of range flag
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DMA 1 transfer using DMA/DMC
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INTREQ 1 device interrupt request
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ENABLE 1 device interrupt enable
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SVCST 2 service state
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SVCCH 2 service channel
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POS 32 number of characters output
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XTIME 24 delay between transfers
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ETIME 24 delay at end of scan
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PTIME 24 delay for shuttle/line advance
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STOP_IOE 1 stop on I/O error
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Error handling is as follows:
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error STOP_IOE processed as
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not attached 1 report error and stop
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OS I/O error x report error and stop
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2.4 4400 Fixed Head Disk (FHD)
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Fixed head disk options include the ability to set the number of
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surfaces to a fixed value between 1 and 16, or to autosize the number
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of surfaces from the attached file:
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SET FHD 1S one surface (98K)
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SET FHD 2S two platters (196K)
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SET FHD 16S sixteen surfaces (1568K)
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SET FHD AUTOSIZE autosized on attach
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The default is one surface.
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The fixed head disk can be connected to the IO bus, a DMC channel, or
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SET FHD IOBUS connect to IO bus
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SET FHD DMC=n connect to DMC channel n (1-16)
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SET FHD DMA=n connect to DMA channel n (1-4)
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By default, the fixed head disk is connected to the IO bus.
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The fixed head disk implements these registers:
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CW1 16 control word 1 (read write, surface, track)
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CW2 16 control word 2 (character address)
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BUSY 1 controller busy flag
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RDY 1 transfer ready flag
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DTE 1 data transfer error flag
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ACE 1 access error flag
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EOR 1 (DMA/DMC) end of range
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DMA 1 transfer using DMA/DMC
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CSUM 1 transfer parity checksum
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INTREQ 1 device interrupt request
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ENABLE 1 device interrupt enable
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TIME 24 delay between words
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STOP_IOE 1 stop on I/O error
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The fixed head disk does not support the BOOT command.
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Error handling is as follows:
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error STOP_IOE processed as
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not attached 1 report error and stop
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Fixed head disk data files are buffered in memory; therefore, end of file
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and OS I/O errors cannot occur.
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2.5 4100 7-track Magnetic Tape (MT)
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Magnetic tape options include the ability to make units write enabled or
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SET MTn LOCKED set unit n write locked
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SET MTn WRITEENABLED set unit n write enabled
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Units can be set ONLINE or OFFLINE, and WRITEENABLED or write LOCKED.
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The magtape controller can be connected to the IO bus, a DMC channel, or
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SET MT IOBUS connect to IO bus
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SET MT DMC=n connect to DMC channel n (1-16)
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SET MT DMA=n connect to DMA channel n (1-4)
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By default, the magtape controller is connected to the IO bus.
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The magnetic tape controller implements these registers:
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BUSY 1 controller busy flag
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RDY 1 transfer ready flag
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EOF 1 end of file flag
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EOR 1 (DMA/DMC) end of range
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DMA 1 transfer using DMA/DMC
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MDIRQ 1 motion done interrupt request
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INTREQ 1 device interrupt request
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ENABLE 1 device interrupt enable
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DBUF[0:65535] 8 transfer buffer
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BPTR 17 transfer buffer pointer
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BMAX 17 transfer size (reads)
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CTIME 24 start/stop time
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XTIME 24 delay between words
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POS[0:3] 32 position, units 0-3
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STOP_IOE 1 stop on I/O error
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Error handling is as follows:
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not attached tape not ready; if STOP_IOE, stop
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OS I/O error parity error; if STOP_IOE, stop
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2.6 4623/4651/4720 Disk Packs (DP)
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The disk controller can be configured as a 4623, supporting 10 surface
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disk packs; a 4651, supporting 2 surface disk packs; or a 4720, supporting
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20 surface disk packs:
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SET DP 4623 controller is 4623
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SET DP 4651 controller is 4651
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SET DP 4720 controller is 4720
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The default is 4651. All disk packs on the controller must be of the
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same type. Units can be set ONLINE or OFFLINE, and WRITEENABLED or
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The disk pack controller can be connected to a DMC channel or a DMA
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channel; it cannot be connected to the IO bus:
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SET DP DMC=n connect to DMC channel n (1-16)
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SET DP DMA=n connect to DMA channel n (1-4)
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The disk pack controller supports variable track formatting. Each track
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can contain between 1 and 103 records, with a minimum size of 1 word and
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a maximum size of 1893 words. Record addresses are unconstrained. The
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simulator provides a command to perform a simple, fixed record size format
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SET DPn FORMAT=k format unit n with k words per record
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SET -R DPn FORMAT=k format unit n with k records per track
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Record addresses can either be geometric (cylinder/track/sector) or simple
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sequential starting from 0:
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SET DPn FORMAT=k format with geometric record addresses
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SET -S DPn FORMAT=k format with sequential record addresses
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Geometric address have the cylinder number in bits<1:8>, the head number in
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bits<9:13>, and the sector number in bits <14:16>.
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A summary of the current format, and its validity, can be obtained with
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SHOW DPn FORMAT display format of unit n
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To accomodate the variable formatting, each track is allocated 2048 words
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in the data file. A record consists of a three word header, the data, and
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word 0 record length in words, not including header/trailer
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word 1 record address
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word 2 number of extension words used (0-4)
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word 3 start of data record
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word 3+n-1 end of data record
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word 3+n..7+n record trailer: up to four extension words,
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A record can "grow" by up to four words without disrupting the track formatting;
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writing more than four extra words destroys the formatting of the rest of the
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track and causes a simulator error.
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The disk pack controller implements these registers:
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FNC 4 controller function
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CW1 16 command word 1
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CW2 16 command word 2
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CSUM 16 record checksum
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BUSY 1 controller busy
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EOR 1 (DMA/DMC) end of range
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DEFINT 1 seek deferred interrupt pending
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INTREQ 1 interrupt request
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ENABLE 1 interrupt enable
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TBUF[0:2047] 16 track buffer
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RPTR 11 pointer to start of record in track buffer
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WPTR 11 pointer to current word in record
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BCTR 15 bit counter for formatting
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STIME 24 seek time, per cylinder
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XTIME 24 transfer time, per word
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BTIME 24 controller busy time
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Error handling is as follows:
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not attached pack off line; if STOP_IOE, stop
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OS I/O error data error; if STOP_IOE, stop
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2.7 Symbolic Display and Input
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The H316/H516 simulator implements symbolic display and input. Display is
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controlled by command line switches:
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-a display as ASCII character
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-c display as two character string
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-m display instruction mnemonics
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Input parsing is controlled by the first character typed in or by command
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' or -a ASCII character
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" or -c two character sixbit string
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alphabetic instruction mnemonic
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Instruction input uses standard H316/H516 assembler syntax. There are six
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instruction classes: memory reference, I/O, control, shift, skip, and
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Memory reference instructions have the format
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memref{*} {C/Z} address{,1}
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where * signifies indirect, C a current sector reference, Z a sector zero
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reference, and 1 indexed. The address is an octal number in the range 0 -
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077777; if C or Z is specified, the address is a page offset in the range
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0 - 0777. Normally, C is not needed; the simulator figures out from the
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address what mode to use. However, when referencing memory outside the CPU,
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there is no valid PC, and C must be used to specify current sector addressing.
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I/O instructions have the format
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The pulse+device is an octal number in the range 0 - 01777.
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Control and operate instructions consist of a single opcode
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Shift instructions have the format
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where n is an octal number in the range 0-77.
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Skip instructions have the format
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sub-op sub-op sub-op...
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The simulator checks that the combination of sub-opcodes is legal.
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H316/h316_doc.txt
