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/* pdp1_drm.c: PDP-1 drum simulator
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Copyright (c) 1993-2004, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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drp Type 23 parallel drum
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drm Type 24 serial drum
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08-Dec-03 RMS Added parallel drum support
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Fixed bug in DBL/DCN decoding
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26-Oct-03 RMS Cleaned up buffer copy code
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23-Jul-03 RMS Fixed incorrect logical, missing activate
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05-Dec-02 RMS Cloned from pdp18b_drm.c
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#include "pdp1_defs.h"
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/* Serial drum constants */
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#define DRM_NUMWDS 256 /* words/sector */
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#define DRM_NUMSC 2 /* sectors/track */
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#define DRM_NUMTR 256 /* tracks/drum */
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#define DRM_NUMWDT (DRM_NUMWDS * DRM_NUMSC) /* words/track */
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#define DRM_SIZE (DRM_NUMTR * DRM_NUMWDT) /* words/drum */
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#define DRM_SMASK ((DRM_NUMTR * DRM_NUMSC) - 1) /* sector mask */
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/* Parallel drum constants */
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#define DRP_NUMWDT 4096 /* words/track */
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#define DRP_NUMTK 32 /* tracks/drum */
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#define DRP_SIZE (DRP_NUMWDT * DRP_NUMTK) /* words/drum */
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#define DRP_V_RWE 17 /* read/write enable */
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#define DRP_V_FLD 12 /* drum field */
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#define DRP_TAMASK 07777 /* track address */
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#define DRP_WCMASK 07777 /* word count */
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#define DRP_MAINCM 07777 /* mem addr incr */
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#define DRP_GETRWE(x) (((x) >> DRP_V_RWE) & 1)
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#define DRP_GETRWF(x) (((x) >> DRP_V_FLD) & DRP_M_FLD)
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/* Parameters in the unit descriptor */
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#define FUNC u4 /* function */
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#define DRM_READ 000 /* read */
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#define DRM_WRITE 010 /* write */
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#define DRP_RW 000 /* read/write */
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#define DRP_BRK 001 /* break on address */
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#define GET_POS(x) ((int) fmod (sim_gtime() / ((double) (x)), \
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((double) DRM_NUMWDT)))
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extern int32 iosta, sbs;
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extern int32 stop_inst;
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/* Serial drum variables */
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uint32 drm_da = 0; /* track address */
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uint32 drm_ma = 0; /* memory address */
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uint32 drm_err = 0; /* error flag */
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uint32 drm_wlk = 0; /* write lock */
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int32 drm_time = 4; /* inter-word time */
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int32 drm_stopioe = 1; /* stop on error */
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/* Parallel drum variables */
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uint32 drp_rde = 0; /* read enable */
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uint32 drp_wre = 0; /* write enable */
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uint32 drp_rdf = 0; /* read field */
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uint32 drp_wrf = 0; /* write field */
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uint32 drp_ta = 0; /* track address */
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uint32 drp_wc = 0; /* word count */
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uint32 drp_ma = 0; /* memory address */
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uint32 drp_err = 0; /* error */
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int32 drp_time = 2; /* inter-word time */
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int32 drp_stopioe = 1; /* stop on error */
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/* Forward declarations */
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t_stat drm_svc (UNIT *uptr);
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t_stat drm_reset (DEVICE *dptr);
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t_stat drp_svc (UNIT *uptr);
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t_stat drp_reset (DEVICE *dptr);
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/* DRM data structures
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drm_dev DRM device descriptor
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drm_unit DRM unit descriptor
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drm_reg DRM register list
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{ UDATA (&drm_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF,
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{ ORDATA (DA, drm_da, 9) },
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{ ORDATA (MA, drm_ma, 16) },
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{ FLDATA (DONE, iosta, IOS_V_DRM) },
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{ FLDATA (ERR, drm_err, 0) },
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{ ORDATA (WLK, drm_wlk, 32) },
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{ DRDATA (TIME, drm_time, 24), REG_NZ + PV_LEFT },
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{ FLDATA (STOP_IOE, drm_stopioe, 0) },
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"DRM", &drm_unit, drm_reg, NULL,
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NULL, NULL, &drm_reset,
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/* DRP data structures
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drp_dev DRP device descriptor
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drp_unit DRP unit descriptor
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drp_reg DRP register list
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{ UDATA (&drp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF,
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{ ORDATA (TA, drp_ta, 12) },
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{ ORDATA (RDF, drp_rdf, 5) },
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{ FLDATA (RDE, drp_rde, 0) },
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{ FLDATA (WRF, drp_wrf, 5) },
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{ FLDATA (WRE, drp_wre, 0) },
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{ ORDATA (MA, drp_ma, 16) },
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{ ORDATA (WC, drp_wc, 12) },
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{ FLDATA (BUSY, iosta, IOS_V_DRP) },
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{ FLDATA (ERR, drp_err, 0) },
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{ DRDATA (TIME, drp_time, 24), REG_NZ + PV_LEFT },
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{ FLDATA (STOP_IOE, drp_stopioe, 0) },
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"DRP", &drp_unit, drp_reg, NULL,
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NULL, NULL, &drp_reset,
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NULL, DEV_DISABLE | DEV_DIS };
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int32 drm (int32 IR, int32 dev, int32 dat)
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int32 pulse = (IR >> 6) & 037;
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if ((drm_dev.flags & DEV_DIS) == 0) { /* serial enabled? */
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if ((pulse != 001) && (pulse != 011)) /* invalid pulse? */
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return (stop_inst << IOT_V_REASON) | dat; /* stop if requested */
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switch (dev) { /* switch on device */
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case 061: /* DWR, DRD */
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drm_ma = dat & AMASK; /* load mem addr */
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drm_unit.FUNC = pulse & DRM_WRITE; /* save function */
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case 062: /* DBL, DCN */
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if ((pulse & 010) == 0) /* DBL? */
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drm_da = dat & DRM_SMASK; /* load sector # */
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iosta = iosta & ~IOS_DRM; /* clear flags */
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t = ((drm_da % DRM_NUMSC) * DRM_NUMWDS) - GET_POS (drm_time);
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if (t <= 0) t = t + DRM_NUMWDT; /* wrap around? */
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sim_activate (&drm_unit, t); /* start operation */
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if (pulse == 011) return (stop_inst << IOT_V_REASON) | dat;
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if (iosta & IOS_DRM) return (dat | IOT_SKP); /* skip if done */
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case 064: /* DSE, DSP */
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if ((drm_err == 0) || (pulse & 010)) /* no error, par test? */
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return (dat | IOT_SKP);
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return dat; } /* end if serial */
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if ((drp_dev.flags & DEV_DIS) == 0) { /* parallel enabled? */
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switch (dev) { /* switch on device */
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case 061: /* DIA, DBA */
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drp_err = 0; /* clear error */
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iosta = iosta & ~IOS_DRP; /* not busy */
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drp_rde = DRP_GETRWE (dat); /* set read enable */
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drp_rdf = DRP_GETRWF (dat); /* set read field */
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drp_ta = dat & DRP_TAMASK; /* set track addr */
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if (IR & 02000) { /* DBA? */
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t = drp_ta - GET_POS (drp_time); /* delta words */
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if (t <= 0) t = t + DRP_NUMWDT; /* wrap around? */
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sim_activate (&drp_unit, t); /* start operation */
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drp_unit.FUNC = DRP_BRK; } /* mark as break */
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else drp_unit.FUNC = DRP_RW; /* no, read/write */
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case 062: /* DWC, DRA */
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if (IR & 02000) dat = GET_POS (drp_time) | /* DRA, get position */
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(drp_err? 0400000: 0);
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drp_wre = DRP_GETRWE (dat); /* set write enable */
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drp_wrf = DRP_GETRWF (dat); /* set write field */
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drp_wc = dat & DRP_WCMASK; } /* set word count */
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drp_ma = dat & AMASK; /* set mem address */
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t = drp_ta - GET_POS (drp_time); /* delta words */
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if (t <= 0) t = t + DRP_NUMWDT; /* wrap around? */
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sim_activate (&drp_unit, t); /* start operation */
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iosta = iosta | IOS_DRP; /* set busy */
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case 064: /* not assigned */
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return (stop_inst << IOT_V_REASON) | dat; /* stop if requested */
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return dat; } /* end if parallel */
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return (stop_inst << IOT_V_REASON) | dat; /* stop if requested */
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/* Serial unit service - this code assumes the entire drum is buffered */
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t_stat drm_svc (UNIT *uptr)
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uint32 *fbuf = uptr->filebuf;
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if ((uptr->flags & UNIT_BUF) == 0) { /* not buf? abort */
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drm_err = 1; /* set error */
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iosta = iosta | IOS_DRM; /* set done */
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sbs = sbs | SB_RQ; /* req intr */
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return IORETURN (drm_stopioe, SCPE_UNATT); }
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da = drm_da * DRM_NUMWDS; /* compute dev addr */
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for (i = 0; i < DRM_NUMWDS; i++, da++) { /* do transfer */
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if (uptr->FUNC == DRM_READ) { /* read? */
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if (MEM_ADDR_OK (drm_ma)) /* if !nxm */
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M[drm_ma] = fbuf[da]; } /* read word */
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if ((drm_wlk >> (drm_da >> 4)) & 1) drm_err = 1;
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else { /* not locked */
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fbuf[da] = M[drm_ma]; /* write word */
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if (da >= uptr->hwmark) uptr->hwmark = da + 1; } }
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drm_ma = (drm_ma + 1) & AMASK; } /* incr mem addr */
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drm_da = (drm_da + 1) & DRM_SMASK; /* incr dev addr */
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iosta = iosta | IOS_DRM; /* set done */
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sbs = sbs | SB_RQ; /* req intr */
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t_stat drm_reset (DEVICE *dptr)
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if ((drm_dev.flags & DEV_DIS) == 0)
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drp_dev.flags = drp_dev.flags | DEV_DIS;
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drm_da = drm_ma = drm_err = 0;
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iosta = iosta & ~IOS_DRM;
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sim_cancel (&drm_unit);
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/* Parallel unit service - this code assumes the entire drum is buffered */
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t_stat drp_svc (UNIT *uptr)
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uint32 *fbuf = uptr->filebuf;
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if ((uptr->flags & UNIT_BUF) == 0) { /* not buf? abort */
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drp_err = 1; /* set error */
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iosta = iosta & ~IOS_DRP; /* clear busy */
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if (uptr->FUNC) sbs = sbs | SB_RQ; /* req intr */
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return IORETURN (drp_stopioe, SCPE_UNATT); }
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if (uptr->FUNC == DRP_RW) { /* read/write? */
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lim = drp_wc? drp_wc: DRP_TAMASK + 1; /* eff word count */
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for (i = 0; i < lim; i++) { /* do transfer */
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if (drp_wre) /* write enabled? */
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fbuf[(drp_wrf << DRP_V_FLD) | drp_ta] = M[drp_ma];
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if (drp_rde && MEM_ADDR_OK (drp_ma)) /* read enabled? */
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M[drp_ma] = fbuf[(drp_rdf << DRP_V_FLD) | drp_ta];
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drp_ta = (drp_ta + 1) & DRP_TAMASK; /* incr track addr */
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drp_ma = ((drp_ma & ~DRP_MAINCM) | ((drp_ma + 1) & DRP_MAINCM));
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iosta = iosta & ~IOS_DRP; /* clear busy */
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if (uptr->FUNC) sbs = sbs | SB_RQ; /* req intr */
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t_stat drp_reset (DEVICE *dptr)
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if ((drp_dev.flags & DEV_DIS) == 0)
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drm_dev.flags = drm_dev.flags | DEV_DIS;
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drp_rde = drp_rdf = drp_wre = drp_wrf = 0;
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iosta = iosta & ~IOS_DRP;
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sim_cancel (&drp_unit);
added
removed
PDP1/pdp1_drm.c
