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/* sds_drm.c: SDS 940 Project Genie drum simulator
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Copyright (c) 2002-2004, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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The drum is buffered in memory.
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Note: the Project Genie documentation and the actual monitor sources disagree
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on the I/O instruction definitions for the drum. The simulator follows the
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monitor sources, as follows:
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DCC OP 00230404B RESET DRUM CHANNEL
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DSC OP 00230204B START DRUM CHANNEL (NO CHAIN)
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DRA OP 00230504B READ DRUM TIMING COUNTER INTO 21B
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DSR OP 04030204B SKIP IF DRUM NOT BUSY
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DSE OP 04037404B SKIP IF NO DRUM ERROR
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#define DRM_N_WD 11 /* word addr width */
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#define DRM_V_WD 0 /* position */
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#define DRM_M_WD ((1 << DRM_N_WD) - 1) /* word mask */
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#define DRM_NUMWD (1 << DRM_N_WD) /* words/sector */
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#define DRM_NUMGP 236 /* gap/sector */
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#define DRM_PHYWD (DRM_NUMWD + DRM_NUMGP) /* phys wds/sector */
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#define DRM_N_SC 3 /* sect addr width */
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#define DRM_V_SC (DRM_N_WD) /* position */
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#define DRM_M_SC ((1 << DRM_N_SC) - 1) /* sector mask */
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#define DRM_NUMSC (1 << DRM_N_SC) /* sectors/track */
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#define DRM_N_TR 7 /* track addr width */
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#define DRM_V_TR (DRM_N_WD+DRM_N_SC) /* position */
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#define DRM_M_TR ((1 << DRM_N_TR) - 1) /* track mask */
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#define DRM_NUMTR 84 /* tracks/drum */
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#define DRM_N_ADDR (DRM_N_WD+DRM_N_SC+DRM_N_TR) /* drum addr width */
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#define DRM_SWMASK ((1 << (DRM_N_WD+DRM_N_SC)) - 1)/* sector+word mask */
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#define DRM_DAMASK ((1 << DRM_N_ADDR) - 1) /* drum addr mask */
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#define DRM_SIZE (DRM_NUMTR*DRM_NUMSC*DRM_NUMWD) /* words/disk */
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#define DRM_WCMASK 037777 /* wc mask */
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#define DRM_GETSC(x) (((x) >> DRM_V_SC) & DRM_M_SC)
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#define DRM_ADAT (1 << (DRM_N_WD + DRM_N_SC)) /* data flag */
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#define DRM_SFET 0 /* fetch state */
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#define DRM_SFCA 1 /* fetch CA */
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#define DRM_SFDA 2 /* fetch DA */
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#define DRM_SXFR 3 /* xfer */
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#define DRM_V_OP 21 /* drum op */
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#define DRM_GETOP(x) (((x) >> DRM_V_OP) & DRM_M_OP)
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#define DRM_GETRW(x) (((x) >> DRM_V_RW) & 1)
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#define DRM_OXF 0 /* xfer */
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#define DRM_OCX 1 /* cond xfer */
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#define DRM_OBR 2 /* branch */
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#define DRM_ORS 3 /* reset error */
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#define DRM_END 4 /* end prog */
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#define DRM_EIE 5 /* end int if err */
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#define DRM_EIU 7 /* end int uncond */
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#define GET_TWORD(x) ((int32) fmod (sim_gtime() / ((double) (x)), \
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((double) (DRM_NUMSC * DRM_PHYWD))))
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extern uint32 M[]; /* memory */
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extern uint32 alert, int_req;
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extern int32 stop_invins, stop_invdev, stop_inviop;
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uint32 drm_da = 0; /* disk address */
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uint32 drm_ca = 0; /* core address */
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uint32 drm_wc = 0; /* word count */
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int32 drm_par = 0; /* cumulative par */
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int32 drm_err = 0; /* error */
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int32 drm_rw = 0; /* read/write */
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int32 drm_sta = 0; /* drum state */
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int32 drm_ftime = 3; /* time to fetch */
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int32 drm_xtime = 1; /* time to xfr */
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int32 drm_stopioe = 1; /* stop on error */
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t_stat drm (uint32 fnc, uint32 inst, uint32 *dat);
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t_stat drm_svc (UNIT *uptr);
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t_stat drm_reset (DEVICE *dptr);
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/* DRM data structures
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drm_dev device descriptor
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drm_unit unit descriptor
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drm_reg register list
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DIB drm_dib = { -1, DEV3_GDRM, 0, NULL, &drm };
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{ UDATA (&drm_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF,
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{ ORDATA (DA, drm_da, DRM_N_ADDR) },
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{ ORDATA (CA, drm_ca, 16) },
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{ ORDATA (WC, drm_wc, 14) },
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{ ORDATA (PAR, drm_par, 12) },
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{ FLDATA (RW, drm_rw, 0) },
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{ FLDATA (ERR, drm_err, 0) },
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{ ORDATA (STA, drm_sta, 2) },
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{ DRDATA (FTIME, drm_ftime, 24), REG_NZ + PV_LEFT },
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{ DRDATA (XTIME, drm_xtime, 24), REG_NZ + PV_LEFT },
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{ FLDATA (STOP_IOE, drm_stopioe, 0) },
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"DRM", &drm_unit, drm_reg, NULL,
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1, 8, DRM_N_ADDR, 1, 8, 24,
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NULL, NULL, &drm_reset,
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&drm_dib, DEV_DISABLE | DEV_DIS };
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/* Drum routine - EOM/SKS 3xx04 */
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t_stat drm (uint32 fnc, uint32 inst, uint32 *dat)
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int32 t, op = inst & 07700;
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case IO_CONN: /* connect */
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if (op == 00400) return drm_reset (&drm_dev); /* EOM 404 = reset */
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if (op == 00500) { /* EOM 504 = read DA */
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if (sim_is_active (&drm_unit)) return SCPE_OK; /* must be idle */
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t = GET_TWORD (drm_xtime); /* get position */
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if (t < DRM_NUMGP) M[DRM_AD] = DRM_NUMWD - t; /* in gap? */
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else M[DRM_AD] = (t - DRM_NUMGP) | DRM_ADAT; } /* in data */
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else if (op == 00200) { /* EOM 204 = start */
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if (sim_is_active (&drm_unit)) return SCPE_OK; /* must be idle */
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drm_sta = DRM_SFET; /* state = fetch */
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sim_activate (&drm_unit, drm_ftime); } /* activate */
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case IO_SKS: /* SKS */
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if (((op == 07400) && !drm_err) || /* 37404: no err */
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((op == 00200) && !sim_is_active (&drm_unit))) /* 30204: idle */
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return SCPE_IERR; } /* can't get here */
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t_stat drm_svc (UNIT *uptr)
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uint32 *fbuf = uptr->filebuf;
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if (drm_sta != DRM_SXFR) { /* fetch drum prog? */
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dpc = M[DRM_PC]; /* get drum PC */
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dwd = M[dpc & PAMASK]; /* get drum inst */
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M[DRM_PC] = (dpc + 1) & PAMASK; /* update drum PC */
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if (drm_sta == DRM_SFCA) { /* fetch core addr? */
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drm_rw = DRM_GETRW (dwd); /* set op */
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drm_ca = dwd & PAMASK; /* set core addr */
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drm_sta = DRM_SFDA; } /* next is disk addr */
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else if (drm_sta == DRM_SFDA) { /* fetch disk addr? */
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drm_da = dwd & DRM_DAMASK; /* set disk addr */
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drm_sta = DRM_SXFR; /* next is xfer */
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drm_par = 0; /* init parity */
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rda = (drm_da & DRM_SWMASK) + (DRM_GETSC (drm_da) * DRM_NUMGP);
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t = rda - GET_TWORD (drm_xtime); /* difference */
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if (t <= 0) t = t + (DRM_NUMSC * DRM_PHYWD); /* add trk lnt */
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sim_activate (&drm_unit, t * drm_xtime); } /* activate */
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switch (DRM_GETOP (dwd)) {
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case DRM_OCX: /* cond xfr */
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if (drm_err) { /* error? */
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int_req = int_req | INT_DRM; /* req int */
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return SCPE_OK; } /* done */
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case DRM_OXF: /* transfer */
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drm_wc = dwd & DRM_WCMASK; /* save wc */
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drm_sta = DRM_SFCA; /* next state */
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case DRM_OBR: /* branch */
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M[DRM_PC] = dwd & PAMASK; /* new drum PC */
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case DRM_END: /* end */
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case DRM_EIE: /* end, int if err */
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if (!drm_err) return SCPE_OK;
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case DRM_EIU: /* end, int uncond */
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int_req = int_req | INT_DRM;
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return SCPE_OK; } /* end switch */
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sim_activate (uptr, drm_ftime); /* fetch next word */
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else { /* transfer word */
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if ((uptr->flags & UNIT_BUF) == 0) { /* not buffered? */
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drm_err = 1; /* error */
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CRETIOE (drm_stopioe, SCPE_UNATT); }
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if (drm_rw) { /* write? */
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dwd = M[drm_ca]; /* get mem word */
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fbuf[drm_da] = dwd; /* write to drum */
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if (drm_da >= uptr->hwmark) uptr->hwmark = drm_da + 1; }
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dwd = fbuf[drm_da]; /* get drum word */
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M[drm_ca] = dwd; } /* write to mem */
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drm_da = drm_da + 1; /* inc drum addr */
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if (drm_da >= DRM_SIZE) drm_da = 0; /* wrap */
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drm_ca = (drm_ca + 1) & PAMASK; /* inc core addr */
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drm_wc = (drm_wc - 1) & DRM_WCMASK; /* dec word cnt */
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drm_par = drm_par ^ (dwd >> 12); /* parity */
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drm_par = ((drm_par << 1) | (drm_par >> 11)) & 07777;
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drm_par = drm_par ^ (dwd & 07777);
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if (drm_wc) { /* more to do */
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if (drm_da & DRM_M_WD) sim_activate (uptr, drm_xtime);
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else sim_activate (uptr, drm_xtime * DRM_NUMGP); }
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#if defined (DRM_PAR)
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if ((drm_da & DRM_M_WD) && drm_rw) { /* wr end mid sector? */
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M[drm_da] = drm_par << 12; /* clobber data */
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if (drm_da >= uptr->hwmark) uptr->hwmark = drm_da + 1; }
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drm_sta = DRM_SFET; /* back to fetch */
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sim_activate (uptr, drm_ftime); /* schedule */
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} /* end else end xfr */
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t_stat drm_reset (DEVICE *dptr)
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drm_da = 0; /* clear state */
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int_req = int_req & ~INT_DRM; /* clear intr */
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sim_cancel (&drm_unit); /* deactivate */
added
removed
SDS/sds_drm.c
