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Viewing changes to src/cmd/5g/peep.c

  • Committer: Package Import Robot
  • Author(s): James Page
  • Date: 2013-08-20 14:06:23 UTC
  • mfrom: (14.1.23 saucy-proposed)
  • Revision ID: package-import@ubuntu.com-20130820140623-b414jfxi3m0qkmrq
Tags: 2:1.1.2-2ubuntu1
https://launchpad.net/bugs/1211749
https://launchpad.net/bugs/1202027
* Merge from Debian unstable (LP: #1211749, #1202027). Remaining changes:
  - 016-armhf-elf-header.patch: Use correct ELF header for armhf binaries.
  - d/control,control.cross: Update Breaks/Replaces for Ubuntu
    versions to ensure smooth upgrades, regenerate control file.

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src/cmd/5g/peep.c
1
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// Inferno utils/5c/peep.c
2
 
// http://code.google.com/p/inferno-os/source/browse/utils/5g/peep.c
 
2
// http://code.google.com/p/inferno-os/source/browse/utils/5c/peep.c
3
3
//
4
4
//      Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
5
5
//      Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
49
49
        int t;
50
50
 
51
51
        p1 = nil;
52
 
        USED(p1);               // ... in unreachable code...
53
52
/*
54
53
 * complete R structure
55
54
 */
77
76
                case AGLOBL:
78
77
                case ANAME:
79
78
                case ASIGNAME:
 
79
                case ALOCALS:
 
80
                case ATYPE:
80
81
                        p = p->link;
81
82
                }
82
83
        }
120
121
                        }
121
122
                        break;
122
123
 
123
 
#ifdef  NOTDEF
 
124
#ifdef NOTDEF
124
125
                        if(p->scond == C_SCOND_NONE)
125
126
                        if(regtyp(&p->to))
126
127
                        if(isdconst(&p->from)) {
133
134
        if(t)
134
135
                goto loop1;
135
136
 
136
 
return;
137
137
 
138
 
#ifdef  NOTDEF
139
138
        for(r=firstr; r!=R; r=r->link) {
140
139
                p = r->prog;
141
140
                switch(p->as) {
142
 
//              case AEOR:
143
 
//                      /*
144
 
//                       * EOR -1,x,y => MVN x,y
145
 
//                       */
146
 
//                      if(isdconst(&p->from) && p->from.offset == -1) {
147
 
//                              p->as = AMVN;
148
 
//                              p->from.type = D_REG;
149
 
//                              if(p->reg != NREG)
150
 
//                                      p->from.reg = p->reg;
151
 
//                              else
152
 
//                                      p->from.reg = p->to.reg;
153
 
//                              p->reg = NREG;
154
 
//                      }
155
 
//                      break;
 
141
                case AEOR:
 
142
                        /*
 
143
                         * EOR -1,x,y => MVN x,y
 
144
                         */
 
145
                        if(isdconst(&p->from) && p->from.offset == -1) {
 
146
                                p->as = AMVN;
 
147
                                p->from.type = D_REG;
 
148
                                if(p->reg != NREG)
 
149
                                        p->from.reg = p->reg;
 
150
                                else
 
151
                                        p->from.reg = p->to.reg;
 
152
                                p->reg = NREG;
 
153
                        }
 
154
                        break;
156
155
 
157
156
                case AMOVH:
158
157
                case AMOVHU:
161
160
                        /*
162
161
                         * look for MOVB x,R; MOVB R,R
163
162
                         */
 
163
                        r1 = r->link;
164
164
                        if(p->to.type != D_REG)
165
165
                                break;
166
166
                        if(r1 == R)
175
175
                        excise(r1);
176
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                        break;
177
177
                }
178
 
                r1 = r->link;
179
178
        }
180
179
 
181
 
//      for(r=firstr; r!=R; r=r->link) {
182
 
//              p = r->prog;
183
 
//              switch(p->as) {
184
 
//              case AMOVW:
185
 
//              case AMOVB:
186
 
//              case AMOVBU:
187
 
//                      if(p->from.type == D_OREG && p->from.offset == 0)
188
 
//                              xtramodes(r, &p->from);
189
 
//                      else
190
 
//                      if(p->to.type == D_OREG && p->to.offset == 0)
191
 
//                              xtramodes(r, &p->to);
192
 
//                      else
193
 
//                              continue;
194
 
//                      break;
 
180
        for(r=firstr; r!=R; r=r->link) {
 
181
                p = r->prog;
 
182
                switch(p->as) {
 
183
                case AMOVW:
 
184
                case AMOVB:
 
185
                case AMOVBU:
 
186
                        if(p->from.type == D_OREG && p->from.offset == 0)
 
187
                                xtramodes(r, &p->from);
 
188
                        else
 
189
                        if(p->to.type == D_OREG && p->to.offset == 0)
 
190
                                xtramodes(r, &p->to);
 
191
                        else
 
192
                                continue;
 
193
                        break;
195
194
//              case ACMP:
196
195
//                      /*
197
196
//                       * elide CMP $0,x if calculation of x can set condition codes
259
258
//                      r2->prog->as = t;
260
259
//                      excise(r);
261
260
//                      continue;
262
 
//              }
263
 
//      }
 
261
                }
 
262
        }
264
263
 
265
 
        predicate();
266
 
#endif
 
264
//      predicate();
267
265
}
268
266
 
 
267
/*
 
268
 * uniqp returns a "unique" predecessor to instruction r.
 
269
 * If the instruction is the first one or has multiple
 
270
 * predecessors due to jump, R is returned.
 
271
 */
269
272
Reg*
270
273
uniqp(Reg *r)
271
274
{
738
741
        return 1;
739
742
}
740
743
 
 
744
/*
 
745
 * findpre returns the last instruction mentioning v
 
746
 * before r. It must be a set, and there must be
 
747
 * a unique path from that instruction to r.
 
748
 */
741
749
Reg*
742
750
findpre(Reg *r, Adr *v)
743
751
{
758
766
        return R;
759
767
}
760
768
 
 
769
/*
 
770
 * findinc finds ADD instructions with a constant
 
771
 * argument which falls within the immed_12 range.
 
772
 */
761
773
Reg*
762
774
findinc(Reg *r, Reg *r2, Adr *v)
763
775
{
848
860
        return findu1(r, v);
849
861
}
850
862
 
 
863
/*
 
864
 * xtramodes enables the ARM post increment and
 
865
 * shift offset addressing modes to transform
 
866
 *   MOVW   0(R3),R1
 
867
 *   ADD    $4,R3,R3
 
868
 * into
 
869
 *   MOVW.P 4(R3),R1
 
870
 * and 
 
871
 *   ADD    R0,R1
 
872
 *   MOVBU  0(R1),R0
 
873
 * into 
 
874
 *   MOVBU  R0<<0(R1),R0
 
875
 */
851
876
int
852
877
xtramodes(Reg *r, Adr *a)
853
878
{
856
881
        Adr v;
857
882
 
858
883
        p = r->prog;
859
 
        if(debug['h'] && p->as == AMOVB && p->from.type == D_OREG)      /* byte load */
860
 
                return 0;
861
884
        v = *a;
862
885
        v.type = D_REG;
863
886
        r1 = findpre(r, &v);
866
889
                if(p1->to.type == D_REG && p1->to.reg == v.reg)
867
890
                switch(p1->as) {
868
891
                case AADD:
 
892
                        if(p1->scond & C_SBIT)
 
893
                                // avoid altering ADD.S/ADC sequences.
 
894
                                break;
869
895
                        if(p1->from.type == D_REG ||
870
896
                           (p1->from.type == D_SHIFT && (p1->from.offset&(1<<4)) == 0 &&
871
897
                            (p->as != AMOVB || (a == &p->from && (p1->from.offset&~0xf) == 0))) ||
1032
1058
                return 0;
1033
1059
 
1034
1060
        case AMULLU:    /* read, read, write, write */
 
1061
        case AMULL:
1035
1062
        case AMULA:
1036
1063
        case AMVN:
1037
1064
                return 2;
1135
1162
                return 0;
1136
1163
 
1137
1164
        case ARET:      /* funny */
1138
 
                if(v->type == D_REG)
1139
 
                if(v->reg == REGRET)
1140
 
                        return 2;
1141
 
                if(v->type == D_FREG)
1142
 
                if(v->reg == FREGRET)
1143
 
                        return 2;
 
1165
                if(s != A)
 
1166
                        return 1;
 
1167
                return 3;
1144
1168
 
1145
1169
        case ABL:       /* funny */
1146
1170
                if(v->type == D_REG) {
1152
1176
                if(v->type == D_FREG)
1153
1177
                        if(v->reg <= FREGEXT && v->reg > exfregoffset)
1154
1178
                                return 2;
 
1179
                if(p->from.type == D_REG && v->type == D_REG && p->from.reg == v->reg)
 
1180
                        return 2;
1155
1181
 
1156
1182
                if(s != A) {
1157
1183
                        if(copysub(&p->to, v, s, 1))
1167
1193
                        if(v->reg == (uchar)REGARG)
1168
1194
                                return 3;
1169
1195
                return 0;
 
1196
 
 
1197
        case ALOCALS:   /* funny */
 
1198
                return 0;
1170
1199
        }
1171
1200
}
1172
1201
 
1213
1242
                        if(a->reg == v->reg)
1214
1243
                                return 1;
1215
1244
                } else
1216
 
                if(a->type == D_REGREG) {
 
1245
                if(a->type == D_REGREG || a->type == D_REGREG2) {
1217
1246
                        if(a->reg == v->reg)
1218
1247
                                return 1;
1219
1248
                        if(a->offset == v->reg)
1276
1305
                        if((a->offset&(1<<4)) && (a->offset>>8) == v->reg)
1277
1306
                                a->offset = (a->offset&~(0xf<<8))|(s->reg<<8);
1278
1307
                } else
1279
 
                if(a->type == D_REGREG) {
 
1308
                if(a->type == D_REGREG || a->type == D_REGREG2) {
1280
1309
                        if(a->offset == v->reg)
1281
1310
                                a->offset = s->reg;
1282
1311
                        if(a->reg == v->reg)