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Viewing changes to books/centaur/vl/systest/flopcode/compare.v

  • Committer: Package Import Robot
  • Author(s): Camm Maguire
  • Date: 2015-01-16 10:35:45 UTC
  • mfrom: (3.3.26 sid)
  • Revision ID: package-import@ubuntu.com-20150116103545-prehe9thgo79o8w8
Tags: 7.0-1
New upstream release

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books/centaur/vl/systest/flopcode/compare.v
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//
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// Original author: Jared Davis <jared@centtech.com>
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`include "spec.v"
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`ifdef SYSTEM_VERILOG_MODE
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 `include "impl.sv"
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`else
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 `include "impl.v"
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`endif
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// Using a global random seed seems like a good idea -- When each instance of
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// randomBit2 had its own seed, they seemed to just always produce the same
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// values on NCVerilog, which was terrible.
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  wire allok = &{okf, okg, okwf, okwg};
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`ifndef VL_SYSTEST_VCS
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  always @(allok)
 
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`else
 
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  // On VCS we seem to get some spurious fails if we just do allok... well, we
 
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  // can at least check on clock transitions.
 
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  always @(posedge clk or negedge clk)
 
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`endif
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    begin
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      if (allok !== 1'b1)
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        $display("failure at time %d", $time);