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(name (cat "VL_" (natstr width) "_BIT_" (natstr nedges) "_EDGE_FLOP"))
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(vl-occform-mkport "q" :vl-output width))
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;; Note: no reg declaration for q, because the actual regs will live in
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;; the submodule instances.
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;; input [width-1:0] d0, d1, ..., d{n-1};
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(vl-occform-mkports "d" 0 nedges :dir :vl-input :width width))
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;; input clk0, clk1, ..., clk{n-1};
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(vl-occform-mkports "clk" 0 nedges :dir :vl-input :width 1))
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(primitive (vl-make-1-bit-n-edge-flop nedges))