420
420
#define ELF_ARCH EM_PPC
422
/* Feature masks for the Aux Vector Hardware Capabilities (AT_HWCAP).
423
See arch/powerpc/include/asm/cputable.h. */
425
PPC_FEATURE_32 = 0x80000000,
426
PPC_FEATURE_64 = 0x40000000,
427
PPC_FEATURE_601_INSTR = 0x20000000,
428
PPC_FEATURE_HAS_ALTIVEC = 0x10000000,
429
PPC_FEATURE_HAS_FPU = 0x08000000,
430
PPC_FEATURE_HAS_MMU = 0x04000000,
431
PPC_FEATURE_HAS_4xxMAC = 0x02000000,
432
PPC_FEATURE_UNIFIED_CACHE = 0x01000000,
433
PPC_FEATURE_HAS_SPE = 0x00800000,
434
PPC_FEATURE_HAS_EFP_SINGLE = 0x00400000,
435
PPC_FEATURE_HAS_EFP_DOUBLE = 0x00200000,
436
PPC_FEATURE_NO_TB = 0x00100000,
437
PPC_FEATURE_POWER4 = 0x00080000,
438
PPC_FEATURE_POWER5 = 0x00040000,
439
PPC_FEATURE_POWER5_PLUS = 0x00020000,
440
PPC_FEATURE_CELL = 0x00010000,
441
PPC_FEATURE_BOOKE = 0x00008000,
442
PPC_FEATURE_SMT = 0x00004000,
443
PPC_FEATURE_ICACHE_SNOOP = 0x00002000,
444
PPC_FEATURE_ARCH_2_05 = 0x00001000,
445
PPC_FEATURE_PA6T = 0x00000800,
446
PPC_FEATURE_HAS_DFP = 0x00000400,
447
PPC_FEATURE_POWER6_EXT = 0x00000200,
448
PPC_FEATURE_ARCH_2_06 = 0x00000100,
449
PPC_FEATURE_HAS_VSX = 0x00000080,
450
PPC_FEATURE_PSERIES_PERFMON_COMPAT = 0x00000040,
452
PPC_FEATURE_TRUE_LE = 0x00000002,
453
PPC_FEATURE_PPC_LE = 0x00000001,
456
#define ELF_HWCAP get_elf_hwcap()
458
static uint32_t get_elf_hwcap(void)
460
CPUState *e = thread_env;
461
uint32_t features = 0;
463
/* We don't have to be terribly complete here; the high points are
464
Altivec/FP/SPE support. Anything else is just a bonus. */
465
#define GET_FEATURE(flag, feature) \
466
do {if (e->insns_flags & flag) features |= feature; } while(0)
467
GET_FEATURE(PPC_64B, PPC_FEATURE_64);
468
GET_FEATURE(PPC_FLOAT, PPC_FEATURE_HAS_FPU);
469
GET_FEATURE(PPC_ALTIVEC, PPC_FEATURE_HAS_ALTIVEC);
470
GET_FEATURE(PPC_SPE, PPC_FEATURE_HAS_SPE);
471
GET_FEATURE(PPC_SPE_SINGLE, PPC_FEATURE_HAS_EFP_SINGLE);
472
GET_FEATURE(PPC_SPE_DOUBLE, PPC_FEATURE_HAS_EFP_DOUBLE);
473
GET_FEATURE(PPC_BOOKE, PPC_FEATURE_BOOKE);
474
GET_FEATURE(PPC_405_MAC, PPC_FEATURE_HAS_4xxMAC);
423
481
* We need to put in some extra aux table entries to tell glibc what
424
482
* the cache block size is, so it can use the dcbz instruction safely.
513
571
#endif /* TARGET_MIPS */
573
#ifdef TARGET_MICROBLAZE
575
#define ELF_START_MMAP 0x80000000
577
#define elf_check_arch(x) ( (x) == EM_XILINX_MICROBLAZE )
579
#define ELF_CLASS ELFCLASS32
580
#define ELF_DATA ELFDATA2MSB
581
#define ELF_ARCH EM_MIPS
583
static inline void init_thread(struct target_pt_regs *regs, struct image_info *infop)
585
regs->pc = infop->entry;
586
regs->r1 = infop->start_stack;
590
#define USE_ELF_CORE_DUMP
591
#define ELF_EXEC_PAGESIZE 4096
593
#endif /* TARGET_MICROBLAZE */
515
595
#ifdef TARGET_SH4
517
597
#define ELF_START_MMAP 0x80000000