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Viewing changes to target-ppc/cpu.h

  • Committer: Riku Voipio
  • Date: 2009-06-08 15:31:58 UTC
  • mfrom: (6281.2.366)
  • mto: This revision was merged to the branch mainline in revision 6452.
  • Revision ID: git-v1:759b334a9739814df2883aa4c41b1c0f5670e90a
Merge commit 'gnu/master' into test

Epic merge

Conflicts:
        Makefile
        block.c
        block.h
        configure
        hw/boards.h
        hw/flash.h
        hw/integratorcp.c
        hw/nand.c
        hw/omap2.c
        hw/omap_i2c.c
        hw/sd.c
        hw/smc91c111.c
        hw/tsc2005.c
        hw/tusb6010.c
        hw/usb-musb.c
        linux-user/syscall.c
        target-arm/machine.c
        target-arm/translate.c

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Lines of Context:
target-ppc/cpu.h
37
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#if defined(TARGET_PPCEMB)
38
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/* Specific definitions for PowerPC embedded */
39
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/* BookE have 36 bits physical address space */
40
 
#define TARGET_PHYS_ADDR_BITS 64
41
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#if defined(CONFIG_USER_ONLY)
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/* It looks like a lot of Linux programs assume page size
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 * is 4kB long. This is evil, but we have to deal with it...
642
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    powerpc_input_t bus_model;
643
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    int bfd_mach;
644
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    uint32_t flags;
 
644
    uint64_t insns_flags;
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646
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    int error_code;
647
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    uint32_t pending_interrupts;
1320
1320
#define SPR_E500_SVR          (0x3FF)
1321
1321
 
1322
1322
/*****************************************************************************/
 
1323
/* PowerPC Instructions types definitions                                    */
 
1324
enum {
 
1325
    PPC_NONE           = 0x0000000000000000ULL,
 
1326
    /* PowerPC base instructions set                                         */
 
1327
    PPC_INSNS_BASE     = 0x0000000000000001ULL,
 
1328
    /*   integer operations instructions                                     */
 
1329
#define PPC_INTEGER PPC_INSNS_BASE
 
1330
    /*   flow control instructions                                           */
 
1331
#define PPC_FLOW    PPC_INSNS_BASE
 
1332
    /*   virtual memory instructions                                         */
 
1333
#define PPC_MEM     PPC_INSNS_BASE
 
1334
    /*   ld/st with reservation instructions                                 */
 
1335
#define PPC_RES     PPC_INSNS_BASE
 
1336
    /*   spr/msr access instructions                                         */
 
1337
#define PPC_MISC    PPC_INSNS_BASE
 
1338
    /* Deprecated instruction sets                                           */
 
1339
    /*   Original POWER instruction set                                      */
 
1340
    PPC_POWER          = 0x0000000000000002ULL,
 
1341
    /*   POWER2 instruction set extension                                    */
 
1342
    PPC_POWER2         = 0x0000000000000004ULL,
 
1343
    /*   Power RTC support                                                   */
 
1344
    PPC_POWER_RTC      = 0x0000000000000008ULL,
 
1345
    /*   Power-to-PowerPC bridge (601)                                       */
 
1346
    PPC_POWER_BR       = 0x0000000000000010ULL,
 
1347
    /* 64 bits PowerPC instruction set                                       */
 
1348
    PPC_64B            = 0x0000000000000020ULL,
 
1349
    /*   New 64 bits extensions (PowerPC 2.0x)                               */
 
1350
    PPC_64BX           = 0x0000000000000040ULL,
 
1351
    /*   64 bits hypervisor extensions                                       */
 
1352
    PPC_64H            = 0x0000000000000080ULL,
 
1353
    /*   New wait instruction (PowerPC 2.0x)                                 */
 
1354
    PPC_WAIT           = 0x0000000000000100ULL,
 
1355
    /*   Time base mftb instruction                                          */
 
1356
    PPC_MFTB           = 0x0000000000000200ULL,
 
1357
 
 
1358
    /* Fixed-point unit extensions                                           */
 
1359
    /*   PowerPC 602 specific                                                */
 
1360
    PPC_602_SPEC       = 0x0000000000000400ULL,
 
1361
    /*   isel instruction                                                    */
 
1362
    PPC_ISEL           = 0x0000000000000800ULL,
 
1363
    /*   popcntb instruction                                                 */
 
1364
    PPC_POPCNTB        = 0x0000000000001000ULL,
 
1365
    /*   string load / store                                                 */
 
1366
    PPC_STRING         = 0x0000000000002000ULL,
 
1367
 
 
1368
    /* Floating-point unit extensions                                        */
 
1369
    /*   Optional floating point instructions                                */
 
1370
    PPC_FLOAT          = 0x0000000000010000ULL,
 
1371
    /* New floating-point extensions (PowerPC 2.0x)                          */
 
1372
    PPC_FLOAT_EXT      = 0x0000000000020000ULL,
 
1373
    PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
 
1374
    PPC_FLOAT_FRES     = 0x0000000000080000ULL,
 
1375
    PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
 
1376
    PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
 
1377
    PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
 
1378
    PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
 
1379
 
 
1380
    /* Vector/SIMD extensions                                                */
 
1381
    /*   Altivec support                                                     */
 
1382
    PPC_ALTIVEC        = 0x0000000001000000ULL,
 
1383
    /*   PowerPC 2.03 SPE extension                                          */
 
1384
    PPC_SPE            = 0x0000000002000000ULL,
 
1385
    /*   PowerPC 2.03 SPE single-precision floating-point extension          */
 
1386
    PPC_SPE_SINGLE     = 0x0000000004000000ULL,
 
1387
    /*   PowerPC 2.03 SPE double-precision floating-point extension          */
 
1388
    PPC_SPE_DOUBLE     = 0x0000000008000000ULL,
 
1389
 
 
1390
    /* Optional memory control instructions                                  */
 
1391
    PPC_MEM_TLBIA      = 0x0000000010000000ULL,
 
1392
    PPC_MEM_TLBIE      = 0x0000000020000000ULL,
 
1393
    PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
 
1394
    /*   sync instruction                                                    */
 
1395
    PPC_MEM_SYNC       = 0x0000000080000000ULL,
 
1396
    /*   eieio instruction                                                   */
 
1397
    PPC_MEM_EIEIO      = 0x0000000100000000ULL,
 
1398
 
 
1399
    /* Cache control instructions                                            */
 
1400
    PPC_CACHE          = 0x0000000200000000ULL,
 
1401
    /*   icbi instruction                                                    */
 
1402
    PPC_CACHE_ICBI     = 0x0000000400000000ULL,
 
1403
    /*   dcbz instruction with fixed cache line size                         */
 
1404
    PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
 
1405
    /*   dcbz instruction with tunable cache line size                       */
 
1406
    PPC_CACHE_DCBZT    = 0x0000001000000000ULL,
 
1407
    /*   dcba instruction                                                    */
 
1408
    PPC_CACHE_DCBA     = 0x0000002000000000ULL,
 
1409
    /*   Freescale cache locking instructions                                */
 
1410
    PPC_CACHE_LOCK     = 0x0000004000000000ULL,
 
1411
 
 
1412
    /* MMU related extensions                                                */
 
1413
    /*   external control instructions                                       */
 
1414
    PPC_EXTERN         = 0x0000010000000000ULL,
 
1415
    /*   segment register access instructions                                */
 
1416
    PPC_SEGMENT        = 0x0000020000000000ULL,
 
1417
    /*   PowerPC 6xx TLB management instructions                             */
 
1418
    PPC_6xx_TLB        = 0x0000040000000000ULL,
 
1419
    /* PowerPC 74xx TLB management instructions                              */
 
1420
    PPC_74xx_TLB       = 0x0000080000000000ULL,
 
1421
    /*   PowerPC 40x TLB management instructions                             */
 
1422
    PPC_40x_TLB        = 0x0000100000000000ULL,
 
1423
    /*   segment register access instructions for PowerPC 64 "bridge"        */
 
1424
    PPC_SEGMENT_64B    = 0x0000200000000000ULL,
 
1425
    /*   SLB management                                                      */
 
1426
    PPC_SLBI           = 0x0000400000000000ULL,
 
1427
 
 
1428
    /* Embedded PowerPC dedicated instructions                               */
 
1429
    PPC_WRTEE          = 0x0001000000000000ULL,
 
1430
    /* PowerPC 40x exception model                                           */
 
1431
    PPC_40x_EXCP       = 0x0002000000000000ULL,
 
1432
    /* PowerPC 405 Mac instructions                                          */
 
1433
    PPC_405_MAC        = 0x0004000000000000ULL,
 
1434
    /* PowerPC 440 specific instructions                                     */
 
1435
    PPC_440_SPEC       = 0x0008000000000000ULL,
 
1436
    /* BookE (embedded) PowerPC specification                                */
 
1437
    PPC_BOOKE          = 0x0010000000000000ULL,
 
1438
    /* mfapidi instruction                                                   */
 
1439
    PPC_MFAPIDI        = 0x0020000000000000ULL,
 
1440
    /* tlbiva instruction                                                    */
 
1441
    PPC_TLBIVA         = 0x0040000000000000ULL,
 
1442
    /* tlbivax instruction                                                   */
 
1443
    PPC_TLBIVAX        = 0x0080000000000000ULL,
 
1444
    /* PowerPC 4xx dedicated instructions                                    */
 
1445
    PPC_4xx_COMMON     = 0x0100000000000000ULL,
 
1446
    /* PowerPC 40x ibct instructions                                         */
 
1447
    PPC_40x_ICBT       = 0x0200000000000000ULL,
 
1448
    /* rfmci is not implemented in all BookE PowerPC                         */
 
1449
    PPC_RFMCI          = 0x0400000000000000ULL,
 
1450
    /* rfdi instruction                                                      */
 
1451
    PPC_RFDI           = 0x0800000000000000ULL,
 
1452
    /* DCR accesses                                                          */
 
1453
    PPC_DCR            = 0x1000000000000000ULL,
 
1454
    /* DCR extended accesse                                                  */
 
1455
    PPC_DCRX           = 0x2000000000000000ULL,
 
1456
    /* user-mode DCR access, implemented in PowerPC 460                      */
 
1457
    PPC_DCRUX          = 0x4000000000000000ULL,
 
1458
};
 
1459
 
 
1460
/*****************************************************************************/
1323
1461
/* Memory access type :
1324
1462
 * may be needed for precise access rights control and precise exceptions.
1325
1463
 */