1
/*====================================================================
2
* Project: Board Support Package (BSP)
4
* Function: Standard definitions for Sharp LH7A404 (ARM922T)
6
* Copyright HighTec EDV-Systeme GmbH 1982-2006
7
*====================================================================*/
12
/* general register definition macro */
13
#define __REG32(x) ((volatile unsigned int *)(x))
14
#define __REG16(x) ((volatile unsigned short *)(x))
15
#define __REG8(x) ((volatile unsigned char *)(x))
22
#define LH7A404_CS0_BASE (0x00000000) /* SMC CS0 */
23
#define LH7A404_CS1_BASE (0x10000000) /* SMC CS1 */
24
#define LH7A404_CS2_BASE (0x20000000) /* SMC CS2 */
25
#define LH7A404_CS3_BASE (0x30000000) /* SMC CS3 */
26
#define LH7A404_PCMCIA0_BASE (0x40000000) /* PC Card/CF Slot 0 */
27
#define LH7A404_PCMCIA1_BASE (0x50000000) /* PC Card/CF Slot 1 */
28
#define LH7A404_CS6_BASE (0x60000000) /* SMC CS6 */
29
#define LH7A404_CS7_BASE (0x70000000) /* SMC CS7 */
30
#define LH7A404_APB_BASE (0x80000000) /* Advanced Peripheral Bus (APB) */
31
#define LH7A404_AHB_BASE (0x80002000) /* Advanced High-Performance Bus (AHB) */
33
#define LH7A404_ESRAM_BASE (0xB0000000) /* Embedded SRAM */
35
#define LH7A404_SDCSC0_BASE (0xC0000000) /* SDRAM CS0 */
36
#define LH7A404_SDCSC1_BASE (0xD0000000) /* SDRAM CS1 */
37
#define LH7A404_SDCSC2_BASE (0xE0000000) /* SDRAM CS2 */
38
#define LH7A404_SDCSC3_BASE (0xF0000000) /* SDRAM CS3 */
41
/*************************/
42
/* Module base addresses */
43
/*************************/
45
#define APB_BASE LH7A404_APB_BASE
47
#define LH7A404_AC97_BASE (APB_BASE + 0x0000) /* AC97 Controller */
48
#define LH7A404_MMC_BASE (APB_BASE + 0x0100) /* Multimedia Card Controller */
49
#define LH7A404_USB_BASE (APB_BASE + 0x0200) /* USB Client */
50
#define LH7A404_SCI_BASE (APB_BASE + 0x0300) /* Smart Card Interface */
51
#define LH7A404_CSC_BASE (APB_BASE + 0x0400) /* Clock/State Controller */
52
#define LH7A404_UART1_BASE (APB_BASE + 0x0600) /* UART1 Controller */
53
#define LH7A404_SIR_BASE (APB_BASE + 0x0600) /* IR Controller, same as UART1 */
54
#define LH7A404_UART2_BASE (APB_BASE + 0x0700) /* UART2 Controller */
55
#define LH7A404_UART3_BASE (APB_BASE + 0x0800) /* UART3 Controller */
56
#define LH7A404_DCDC_BASE (APB_BASE + 0x0900) /* DC to DC Controller */
57
#define LH7A404_ACI_BASE (APB_BASE + 0x0A00) /* Audio Codec Interface */
58
#define LH7A404_SSP_BASE (APB_BASE + 0x0B00) /* Synchronous Serial Port */
59
#define LH7A404_TIMER_BASE (APB_BASE + 0x0C00) /* Timer Controller */
60
#define LH7A404_RTC_BASE (APB_BASE + 0x0D00) /* Real-time Clock */
61
#define LH7A404_GPIO_BASE (APB_BASE + 0x0E00) /* General Purpose IO */
62
#define LH7A404_BMI_BASE (APB_BASE + 0x0F00) /* Battery Monitor Interface */
63
#define LH7A404_ALI_BASE (APB_BASE + 0x1000) /* Advanced LCD Interface */
64
#define LH7A404_PWM_BASE (APB_BASE + 0x1100) /* Pulse Width Modulator */
65
#define LH7A404_KMI_BASE (APB_BASE + 0x1200) /* Keyboard and Mouse Interface */
66
#define LH7A404_ADC_BASE (APB_BASE + 0x1300) /* Analog-to-Digital Converter */
67
#define LH7A404_WDT_BASE (APB_BASE + 0x1400) /* Watchdog Timer */
69
#define AHB_BASE LH7A404_AHB_BASE
71
#define LH7A404_SMC_BASE (AHB_BASE + 0x0000) /* Static Memory Controller */
72
#define LH7A404_SDMC_BASE (AHB_BASE + 0x0400) /* Synchronous Dynamic Memory Controller */
73
#define LH7A404_DMAC_BASE (AHB_BASE + 0x0800) /* DMA Controller */
74
#define LH7A404_CLCDC_BASE (AHB_BASE + 0x1000) /* Color LCD Controller */
76
#define LH7A404_VIC1_BASE (AHB_BASE + 0x6000) /* Vectored Interrupt Controller 1 */
77
#define LH7A404_USBH_BASE (AHB_BASE + 0x7000) /* USB OHCI host controller */
78
#define LH7A404_VIC2_BASE (AHB_BASE + 0x8000) /* Vectored Interrupt Controller 2 */
82
/**************************************/
83
/* Static Memory Controller registers */
84
/**************************************/
86
#define SMC_BASE LH7A404_SMC_BASE
88
#define SMC_BCR0 __REG32(SMC_BASE + 0x00) /* Bank 0 Configuration */
89
#define SMC_BCR1 __REG32(SMC_BASE + 0x04) /* Bank 1 Configuration */
90
#define SMC_BCR2 __REG32(SMC_BASE + 0x08) /* Bank 2 Configuration */
91
#define SMC_BCR3 __REG32(SMC_BASE + 0x0C) /* Bank 3 Configuration */
92
#define SMC_BCR6 __REG32(SMC_BASE + 0x18) /* Bank 6 Configuration */
93
#define SMC_BCR7 __REG32(SMC_BASE + 0x1C) /* Bank 7 Configuration */
94
#define SMC_PC1ATTRIB __REG32(SMC_BASE + 0x20) /* PC Card 1 Attribute Space Config. */
95
#define SMC_PC1COM __REG32(SMC_BASE + 0x24) /* PC Card 1 Common Memory Space Config. */
96
#define SMC_PC1IO __REG32(SMC_BASE + 0x28) /* PC Card 1 I/O Space Configuration */
97
#define SMC_PC2ATTRIB __REG32(SMC_BASE + 0x30) /* PC Card 2 Attribute Space Config. */
98
#define SMC_PC2COM __REG32(SMC_BASE + 0x34) /* PC Card 2 Common Memory Space Config. */
99
#define SMC_PC2IO __REG32(SMC_BASE + 0x38) /* PC Card 2 I/O Space Configuration */
100
#define SMC_PCMCIACON __REG32(SMC_BASE + 0x40) /* PCMCIA Control */
102
/* bitfields in BCRx */
103
#define BCR_IDCY_SHFT 0
104
#define BCR_IDCY_MSK (0x0F << 0) /* Idle Cycle */
105
#define BCR_WST1_SHFT 5
106
#define BCR_WST1_MSK (0x1F << 5) /* Wait State 1 */
107
#define BCR_RBLE (1 << 10) /* Read Byte Lane Enable */
108
#define BCR_WST2_SHFT 11
109
#define BCR_WST2_MSK (0x1F << 11) /* Wait State 2 */
110
#define BCR_WPERR (1 << 25) /* Write Protect Error */
111
#define BCR_WP (1 << 26) /* Write Protect */
112
#define BCR_PME (1 << 27) /* Page Mode Enable */
113
#define BCR_MW_SHFT 28
114
#define BCR_MW_MSK (0x03 << 28) /* Memory Width */
115
#define BCR_MW_8 (0x00 << 28)
116
#define BCR_MW_16 (0x01 << 28)
117
#define BCR_MW_32 (0x02 << 28)
119
/* bitfields in PCxATTRIB */
120
#define PCATTR_PA_SHFT 0
121
#define PCATTR_PA_MSK (0xFF << 0) /* Pre-Charge Delay Time for Attribute Space */
122
#define PCATTR_HT_SHFT 8
123
#define PCATTR_HT_MSK (0x0F << 8) /* Hold Time */
124
#define PCATTR_AA_SHFT 16
125
#define PCATTR_AA_MSK (0xFF << 16) /* Access Time for Attribute Space */
126
#define PCATTR_WA_16 (1 << 31) /* Width of Attribute Address Space (16 bit) */
127
#define PCATTR_WA_8 (0 << 31) /* Width of Attribute Address Space (8 bit) */
129
/* bitfields in PCxCOM */
130
#define PCCOM_PC_SHFT 0
131
#define PCCOM_PC_MSK (0xFF << 0) /* Pre-Charge Delay Time for Common Memory Space */
132
#define PCCOM_HT_SHFT 8
133
#define PCCOM_HT_MSK (0x0F << 8) /* Hold Time */
134
#define PCCOM_AC_SHFT 16
135
#define PCCOM_AC_MSK (0xFF << 16) /* Access Time for Common Memory Space */
136
#define PCCOM_WC_16 (1 << 31) /* Width of Common Memory Address Space (16 bit) */
137
#define PCCOM_WC_8 (0 << 31) /* Width of Common Memory Address Space (8 bit) */
139
/* bitfields in PCxIO */
140
#define PCIO_PI_SHFT 0
141
#define PCIO_PI_MSK (0xFF << 0) /* Pre-Charge Delay Time for I/O Space */
142
#define PCIO_HT_SHFT 8
143
#define PCIO_HT_MSK (0x0F << 8) /* Hold Time */
144
#define PCIO_AI_SHFT 16
145
#define PCIO_AI_MSK (0xFF << 16) /* Access Time for I/O Space */
146
#define PCIO_WI_16 (1 << 31) /* Width of I/O Address Space (16 bit) */
147
#define PCIO_WI_8 (0 << 31) /* Width of I/O Address Space (8 bit) */
149
/* bits in PCMCIACON register */
150
#define PCMCIA_PC12EN (0x03 << 0) /* PC Card 1 and 2 Enable */
151
#define PCMCIA_PC1RST (1 << 2) /* PC Card 1 Reset */
152
#define PCMCIA_PC2RST (1 << 3) /* PC Card 2 Reset */
153
#define PCMCIA_WEN1 (1 << 4) /* Wait State Enable for Card 1 */
154
#define PCMCIA_WEN2 (1 << 5) /* Wait State Enable for Card 2 */
155
#define PCMCIA_MPREG (1 << 9) /* Manual Control of PCREG */
159
/***************************************************/
160
/* Synchronous Dynamic Memory Controller registers */
161
/***************************************************/
163
#define SDMC_BASE LH7A404_SDMC_BASE
165
#define SDMC_GBLCNFG __REG32(SDMC_BASE + 0x04) /* Global Configuration */
166
#define SDMC_RFSHTMR __REG32(SDMC_BASE + 0x08) /* Refresh Timer */
167
#define SDMC_BOOTSTAT __REG32(SDMC_BASE + 0x0C) /* Boot Status */
168
#define SDMC_SDCSC0 __REG32(SDMC_BASE + 0x10) /* Synchr. Domain Chip Select Config. 0 */
169
#define SDMC_SDCSC1 __REG32(SDMC_BASE + 0x14) /* Synchr. Domain Chip Select Config. 1 */
170
#define SDMC_SDCSC2 __REG32(SDMC_BASE + 0x18) /* Synchr. Domain Chip Select Config. 2 */
171
#define SDMC_SDCSC3 __REG32(SDMC_BASE + 0x1C) /* Synchr. Domain Chip Select Config. 3 */
173
/* bits in GBLCNFG register */
174
#define GBLCNFG_INIT (1 << 0) /* Initialize */
175
#define GBLCNFG_MRS (1 << 1) /* Mode Register in Synchronous device */
176
#define GBLCNFG_SMEMBS (1 << 5) /* Synchronous Memory Busy State */
177
#define GBLCNFG_LCR (1 << 6) /* Load Command Register */
178
#define GBLCNFG_CKSD (1 << 30) /* Clock Shutdown */
179
#define GBLCNFG_CKE (1 << 31) /* Clock Enable */
181
/* bits in BOOTSTAT register */
182
#define BOOTSTAT_WIDTH (0x03 << 0) /* Boot Memory Width */
183
#define BOOTSTAT_MEDCHG (1 << 2) /* Media Change [1 = Synchr., 0 = Asynchr. ROM] */
185
/* bits in SDMC_SDCSCx register */
186
#define SDCSC_EBW (1 << 2) /* External Bus Width [1 = 16, 0 = 32 bit] */
187
#define SDCSC_BANKCOUNT (1 << 3) /* Bank Count [0 = 2 , 1 = 4 bank devices] */
188
#define SDCSC_SROM512 (1 << 4) /* SROM Page Depth 512 */
189
#define SDCSC_SROMLL (1 << 5) /* SROM Lookalike */
190
#define SDCSC_2KPAGE (1 << 6) /* 2K Page Depth */
191
#define SDCSC_CASLAT (0x07 << 16) /* Column Address Strobe Latency */
192
#define SDCSC_WBL (1 << 19) /* Write Burst Length */
193
#define SDCSC_RASTOCAS (0x03 << 20) /* Row Address Strobe To Column Address Strobe */
194
#define SDCSC_APEN (1 << 24) /* Auto Precharge Enable */
197
/***********************************/
198
/* Clock/State Controller register */
199
/***********************************/
201
#define CSC_BASE LH7A404_CSC_BASE
203
#define CSC_PWRSR __REG32(CSC_BASE + 0x00) /* Power Reset Register */
204
#define CSC_PWRCNT __REG32(CSC_BASE + 0x04) /* Power Control Register */
205
#define CSC_HALT __REG32(CSC_BASE + 0x08) /* Read to enter Halt */
206
#define CSC_STBY __REG32(CSC_BASE + 0x0C) /* Read to enter Standby */
207
#define CSC_BLEOI __REG32(CSC_BASE + 0x10) /* Battery Low End Of Interrupt reg */
208
#define CSC_MCEOI __REG32(CSC_BASE + 0x14) /* Media Changed End Of Interrupt reg */
209
#define CSC_TEOI __REG32(CSC_BASE + 0x18) /* Tick End Of Interrupt register */
210
#define CSC_STFCLR __REG32(CSC_BASE + 0x1C) /* STatus Flag CLeaR register */
211
#define CSC_CLKSET __REG32(CSC_BASE + 0x20) /* Clock Set register */
212
#define CSC_SCRREG0 __REG32(CSC_BASE + 0x40) /* General purpose storage register 0 */
213
#define CSC_SCRREG1 __REG32(CSC_BASE + 0x44) /* General purpose storage register 1 */
214
#define CSC_USBDRESET __REG32(CSC_BASE + 0x4C) /* USB Device Reset register */
215
#define CSC_BMAR __REG32(CSC_BASE + 0x54) /* Bus Master Arbitration Register */
216
#define CSC_BOOTCLR __REG32(CSC_BASE + 0x58) /* Boot ROM Clear Register */
218
/* Bits in Power Reset Register */
219
#define CSC_PWRSR_RTCDIV_MSK 0x0000003F /* Real Time Clock Divisor */
220
#define CSC_PWRSR_MCDR (1 << 6) /* Media Change Direct Read */
221
#define CSC_PWRSR_DCDET (1 << 7) /* Direct Current Detect */
222
#define CSC_PWRSR_WUDR (1 << 8) /* Wakeup Direct */
223
#define CSC_PWRSR_WUON (1 << 9) /* Wake Up On */
224
#define CSC_PWRSR_NBFLG (1 << 10) /* New Battery Status Flag */
225
#define CSC_PWRSR_RSTFLG (1 << 11) /* User Reset Status Flag */
226
#define CSC_PWRSR_PFFLG (1 << 12) /* Power Fail Status Flag */
227
#define CSC_PWRSR_CLDFLG (1 << 13) /* Cold Start Status Flag */
228
#define CSC_PWRSR_LCKFLG (1 << 14) /* PLL2 Lock Flag */
229
#define CSC_PWRSR_WDTFLG (1 << 15) /* Watchdog Flag */
230
#define CSC_PWRSR_CHIPID_MSK (0xFF << 16) /* Chip Identification */
231
#define CSC_PWRSR_CHIPMAN_MSK (0xFF << 24) /* Chip Manufacturer ID [0x53 = 'S'] */
233
/* Bits in Power Control Register */
234
#define CSC_PWRCNT_WDTSEL (1 << 0) /* Watchdog Timer Reset Select */
235
#define CSC_PWRCNT_WAKEDIS (1 << 1) /* Wakeup Disable */
236
#define CSC_PWRCNT_PGMCLK_MSK (0xFF << 8) /* Program Clock Divisor */
237
#define CSC_PWRCNT_DMAM2PCH1 (1 << 16) /* DMA M2P Clock Enable Channel 1 */
238
#define CSC_PWRCNT_DMAM2PCH0 (1 << 17) /* DMA M2P Clock Enable Channel 0 */
239
#define CSC_PWRCNT_DMAM2PCH3 (1 << 18) /* DMA M2P Clock Enable Channel 3 */
240
#define CSC_PWRCNT_DMAM2PCH2 (1 << 19) /* DMA M2P Clock Enable Channel 2 */
241
#define CSC_PWRCNT_DMAM2PCH5 (1 << 20) /* DMA M2P Clock Enable Channel 5 */
242
#define CSC_PWRCNT_DMAM2PCH4 (1 << 21) /* DMA M2P Clock Enable Channel 4 */
243
#define CSC_PWRCNT_DMAM2PCH7 (1 << 22) /* DMA M2P Clock Enable Channel 7 */
244
#define CSC_PWRCNT_DMAM2PCH6 (1 << 23) /* DMA M2P Clock Enable Channel 6 */
245
#define CSC_PWRCNT_DMAM2PCH9 (1 << 24) /* DMA M2P Clock Enable Channel 9 */
246
#define CSC_PWRCNT_DMAM2PCH8 (1 << 25) /* DMA M2P Clock Enable Channel 8 */
247
#define CSC_PWRCNT_DMAM2MCH0 (1 << 26) /* DMA M2M Clock Enable Channel 0 */
248
#define CSC_PWRCNT_DMAM2MCH1 (1 << 27) /* DMA M2M Clock Enable Channel 1 */
249
#define CSC_PWRCNT_USHEN (1 << 28) /* USB Host Clock Enable */
250
#define CSC_PWRCNT_UARTBAUD (1 << 29) /* UART Baud Clock Source */
252
/* Bits in CLKSET Register */
253
#define CSC_CLKSET_HCLKDIV_SHFT 0
254
#define CSC_CLKSET_HCLKDIV_MSK (0x03 << 0) /* HCLK Divisor */
255
#define CSC_CLKSET_PREDIV_SHFT 2
256
#define CSC_CLKSET_PREDIV_MSK (0x1F << 2) /* Predivisor */
257
#define CSC_CLKSET_MAINDIV1_SHFT 7
258
#define CSC_CLKSET_MAINDIV1_MSK (0x0F << 7) /* Main Divisor 1 */
259
#define CSC_CLKSET_MAINDIV2_SHFT 11
260
#define CSC_CLKSET_MAINDIV2_MSK (0x1F << 11) /* Main Divisor 2 */
261
#define CSC_CLKSET_PCLKDIV_SHFT 16
262
#define CSC_CLKSET_PCLKDIV_MSK (0x03 << 16) /* PCLK Divisor */
263
#define CSC_CLKSET_PS_SHFT 18
264
#define CSC_CLKSET_PS_MSK (0x03 << 18) /* PS Divisor (2^PS) */
265
#define CSC_CLKSET_SMCROM (1 << 24) /* SMC Clock Disable */
267
/* Bits in USB Device Reset Register */
268
#define CSC_USBDRESET_IO (1 << 0) /* Reset USB Device I/O side */
269
#define CSC_USBDRESET_APB (1 << 1) /* Reset USB Device control side */
274
/*******************************************/
275
/* Vectored Interrupt Controller registers */
276
/*******************************************/
278
#define VIC1_BASE LH7A404_VIC1_BASE
280
#define VIC1_IRQSTATUS __REG32(VIC1_BASE + 0x00) /* IRQ Status Register */
281
#define VIC1_FIQSTATUS __REG32(VIC1_BASE + 0x04) /* FIQ Status Register */
282
#define VIC1_RAWINTR __REG32(VIC1_BASE + 0x08) /* Raw Interrupt Status Register */
283
#define VIC1_INTSEL __REG32(VIC1_BASE + 0x0C) /* Interrupt Select Register */
284
#define VIC1_INTEN __REG32(VIC1_BASE + 0x10) /* Interrupt Enable Register */
285
#define VIC1_INTENCLR __REG32(VIC1_BASE + 0x14) /* Interrupt Enable Clear Register */
286
#define VIC1_SOFTINT __REG32(VIC1_BASE + 0x18) /* Software Interrupt Register */
287
#define VIC1_SOFTINTCLR __REG32(VIC1_BASE + 0x1C) /* Software Interrupt Clear Register */
288
#define VIC1_VECTADDR __REG32(VIC1_BASE + 0x30) /* Vector Address Register */
289
#define VIC1_NVADDR __REG32(VIC1_BASE + 0x34) /* Non-vectored Address Register */
290
#define VIC1_VAD0 __REG32(VIC1_BASE + 0x100) /* Vector Address 0 Register */
291
#define VIC1_VECTCNTL0 __REG32(VIC1_BASE + 0x200) /* Vector Control 0 Register */
292
#define VIC1_ITCR __REG32(VIC1_BASE + 0x300) /* Test Control Register */
293
#define VIC1_ITIP1 __REG32(VIC1_BASE + 0x304) /* Test Input Register 1 */
294
#define VIC1_ITIP2 __REG32(VIC1_BASE + 0x308) /* Test Input Register 2 */
295
#define VIC1_ITOP1 __REG32(VIC1_BASE + 0x30C) /* Test Output Register 1 */
296
#define VIC1_ITOP2 __REG32(VIC1_BASE + 0x310) /* Test Output Register 2 */
298
#define VIC2_BASE LH7A404_VIC2_BASE
300
#define VIC2_IRQSTATUS __REG32(VIC2_BASE + 0x00) /* IRQ Status Register */
301
#define VIC2_FIQSTATUS __REG32(VIC2_BASE + 0x04) /* FIQ Status Register */
302
#define VIC2_RAWINTR __REG32(VIC2_BASE + 0x08) /* Raw Interrupt Status Register */
303
#define VIC2_INTSEL __REG32(VIC2_BASE + 0x0C) /* Interrupt Select Register */
304
#define VIC2_INTEN __REG32(VIC2_BASE + 0x10) /* Interrupt Enable Register */
305
#define VIC2_INTENCLR __REG32(VIC2_BASE + 0x14) /* Interrupt Enable Clear Register */
306
#define VIC2_SOFTINT __REG32(VIC2_BASE + 0x18) /* Software Interrupt Register */
307
#define VIC2_SOFTINTCLR __REG32(VIC2_BASE + 0x1C) /* Software Interrupt Clear Register */
308
#define VIC2_VECTADDR __REG32(VIC2_BASE + 0x30) /* Vector Address Register */
309
#define VIC2_NVADDR __REG32(VIC2_BASE + 0x34) /* Non-vectored Address Register */
310
#define VIC2_VAD0 __REG32(VIC2_BASE + 0x100) /* Vector Address 0 Register */
311
#define VIC2_VECTCNTL0 __REG32(VIC2_BASE + 0x200) /* Vector Control 0 Register */
312
#define VIC2_ITCR __REG32(VIC2_BASE + 0x300) /* Test Control Register */
313
#define VIC2_ITIP1 __REG32(VIC2_BASE + 0x304) /* Test Input Register 1 */
314
#define VIC2_ITIP2 __REG32(VIC2_BASE + 0x308) /* Test Input Register 2 */
315
#define VIC2_ITOP1 __REG32(VIC2_BASE + 0x30C) /* Test Output Register 1 */
316
#define VIC2_ITOP2 __REG32(VIC2_BASE + 0x310) /* Test Output Register 2 */
318
#define VIC_CNTL_ENABLE (0x20) /* Enable bit in VECTCNTLx register */
321
/*****************************************/
322
/* Direct Memory Access (DMA) Controller */
323
/*****************************************/
325
#define DMAC_BASE LH7A404_DMAC_BASE
327
#define DMAC_M2PCH0_BASE (DMAC_BASE + 0x0000) /* M2P Channel 0 Registers (Tx) */
328
#define DMAC_M2PCH1_BASE (DMAC_BASE + 0x0040) /* M2P Channel 1 Registers (Rx) */
329
#define DMAC_M2PCH2_BASE (DMAC_BASE + 0x0080) /* M2P Channel 2 Registers (Tx) */
330
#define DMAC_M2PCH3_BASE (DMAC_BASE + 0x00C0) /* M2P Channel 3 Registers (Rx) */
331
#define DMAC_M2MCH0_BASE (DMAC_BASE + 0x0100) /* M2M Channel 0 Registers */
332
#define DMAC_M2MCH1_BASE (DMAC_BASE + 0x0140) /* M2M Channel 0 Registers */
333
#define DMAC_M2PCH5_BASE (DMAC_BASE + 0x0200) /* M2P Channel 5 Registers (Rx) */
334
#define DMAC_M2PCH4_BASE (DMAC_BASE + 0x0240) /* M2P Channel 4 Registers (Tx) */
335
#define DMAC_M2PCH7_BASE (DMAC_BASE + 0x0280) /* M2P Channel 7 Registers (Rx) */
336
#define DMAC_M2PCH6_BASE (DMAC_BASE + 0x02C0) /* M2P Channel 6 Registers (Tx) */
337
#define DMAC_M2PCH9_BASE (DMAC_BASE + 0x0300) /* M2P Channel 9 Registers (Rx) */
338
#define DMAC_M2PCH8_BASE (DMAC_BASE + 0x0340) /* M2P Channel 8 Registers (Tx) */
340
#define DMAC_GCA __REG32(DMAC_BASE + 0x0380) /* Global Channel Arbitration Register */
341
#define DMAC_GIR __REG32(DMAC_BASE + 0x03C0) /* Global Interrupt Register */
344
/************************/
345
/* Color LCD Controller */
346
/************************/
348
#define CLCDC_BASE LH7A404_CLCDC_BASE
350
#define CLCDC_TIMING0 __REG32(CLCDC_BASE + 0x000) /* Horizontal axis panel control */
351
#define CLCDC_TIMING1 __REG32(CLCDC_BASE + 0x004) /* Vertical axis panel control */
352
#define CLCDC_TIMING2 __REG32(CLCDC_BASE + 0x008) /* Clock and signal polarity control */
353
#define CLCDC_UPBASE __REG32(CLCDC_BASE + 0x010) /* Upper panel frame base address */
354
#define CLCDC_LPBASE __REG32(CLCDC_BASE + 0x014) /* Lower panel frame base address */
355
#define CLCDC_INTREN __REG32(CLCDC_BASE + 0x018) /* Interrupt enable mask */
356
#define CLCDC_CONTROL __REG32(CLCDC_BASE + 0x01C) /* LCD panel pixel parameters */
357
#define CLCDC_STATUS __REG32(CLCDC_BASE + 0x020) /* Raw interrupt status */
358
#define CLCDC_INTERRUPT __REG32(CLCDC_BASE + 0x024) /* Final masked interrupts */
359
#define CLCDC_UPCURR __REG32(CLCDC_BASE + 0x028) /* LCD upper panel current address value */
360
#define CLCDC_LPCURR __REG32(CLCDC_BASE + 0x02C) /* LCD lower panel current address value */
361
#define CLCDC_OVERFLOW __REG32(CLCDC_BASE + 0x030) /* SDRAM overflow frame buffer address */
363
/* LCD Palette registers: 256 entries with 16 bit */
364
#define CLCDC_PALETTE_BASE (CLCDC_BASE + 0x300)
366
/* Bits in CLCDC Timing Register 0 */
367
#define CLCDC_TIMING0_PPL_SHFT 2
368
#define CLCDC_TIMING0_PPL_MSK (0x3F << 2) /* Pixels Per Line */
369
#define CLCDC_TIMING0_HSW_SHFT 8
370
#define CLCDC_TIMING0_HSW_MSK (0xFF << 8) /* Horizontal Synchronization Pulse Width */
371
#define CLCDC_TIMING0_HFP_SHFT 16
372
#define CLCDC_TIMING0_HFP_MSK (0xFF << 16) /* Horizontal Front Porch */
373
#define CLCDC_TIMING0_HBP_SHFT 24
374
#define CLCDC_TIMING0_HBP_MSK (0xFF << 24) /* Horizontal Back Porch */
376
/* Bits in CLCDC Timing Register 1 */
377
#define CLCDC_TIMING1_LPP_SHFT 0
378
#define CLCDC_TIMING1_LPP_MSK (0x1FF << 0) /* Lines Per Panel */
379
#define CLCDC_TIMING1_VSW_SHFT 10
380
#define CLCDC_TIMING1_VSW_MSK (0x3F << 10) /* Vertical Synchronization Pulse Width */
381
#define CLCDC_TIMING1_VFP_SHFT 16
382
#define CLCDC_TIMING1_VFP_MSK (0xFF << 16) /* Vertical Front Porch */
383
#define CLCDC_TIMING1_VBP_SHFT 24
384
#define CLCDC_TIMING1_VBP_MSK (0xFF << 24) /* Vertical Back Porch */
386
/* Bits in CLCDC Timing Register 2 */
387
#define CLCDC_TIMING2_PCD_SHFT 0
388
#define CLCDC_TIMING2_PCD_MSK (0x1F << 0) /* Panel Clock Divisor */
389
#define CLCDC_TIMING2_CSEL (1 << 5) /* Clock Select */
390
#define CLCDC_TIMING2_ACB_SHFT 6
391
#define CLCDC_TIMING2_ACB_MSK (0x1F << 6) /* AC Bias Signal Frequency */
392
#define CLCDC_TIMING2_IVS (1 << 11) /* Invert Vertical Synchronization */
393
#define CLCDC_TIMING2_IHS (1 << 12) /* Invert Horizontal Synchronization */
394
#define CLCDC_TIMING2_IPC (1 << 13) /* Invert Panel Clock */
395
#define CLCDC_TIMING2_IOE (1 << 14) /* Invert Output Enable */
396
#define CLCDC_TIMING2_CPL_SHFT 16
397
#define CLCDC_TIMING2_CPL_MSK (0x3FF << 16) /* Clocks Per Line */
398
#define CLCDC_TIMING2_BCD (1 << 26) /* Bypass Pixel Clock Divider */
400
/* Bits in CLCDC Interrupt Enable Register (INTREN) */
401
#define CLCDC_INTREN_FUIEN (1 << 1) /* FIFO Underflow Interrupt Enable */
402
#define CLCDC_INTREN_BUIEN (1 << 2) /* Next Base Update Interrupt Enable */
403
#define CLCDC_INTREN_VCIEN (1 << 3) /* Vertical Compare Interrupt Enable */
404
#define CLCDC_INTREN_MBEIEN (1 << 4) /* Bus Master Error Interrupt Enable */
406
/* Bits in CLCDC Control Register (CONTROL) */
407
#define CLCDC_CONTROL_LCDEN (1 << 0) /* Color LCD Controller Enable */
408
#define CLCDC_CONTROL_BPP_SHFT 1
409
#define CLCDC_CONTROL_BPP_MSK (0x07 << 1) /* Bits Per Pixel */
410
#define CLCDC_CONTROL_BPP_1 (0 << 1)
411
#define CLCDC_CONTROL_BPP_2 (1 << 1)
412
#define CLCDC_CONTROL_BPP_4 (2 << 1)
413
#define CLCDC_CONTROL_BPP_8 (3 << 1)
414
#define CLCDC_CONTROL_BPP_16 (4 << 1)
415
#define CLCDC_CONTROL_BW (1 << 4) /* Monochrome STN LCD */
416
#define CLCDC_CONTROL_TFT (1 << 5) /* TFT LCD */
417
#define CLCDC_CONTROL_MONO8L (1 << 6) /* Monochrome LCD uses 8-bit interface */
418
#define CLCDC_CONTROL_DUAL (1 << 7) /* Dual Panel STN LCD */
419
#define CLCDC_CONTROL_BGR (1 << 8) /* RGB or BGR */
420
#define CLCDC_CONTROL_BEBO (1 << 9) /* Big Endian Byte Ordering */
421
#define CLCDC_CONTROL_BEPO (1 << 10) /* Big Endian Pixel Ordering */
422
#define CLCDC_CONTROL_PWR (1 << 11) /* LCD Power Enable */
423
#define CLCDC_CONTROL_VCI_SHFT 12
424
#define CLCDC_CONTROL_VCI_MSK (0x3 << 12) /* LCD Vertical Compare */
425
#define CLCDC_CONTROL_WATERMARK (1 << 16) /* LCD DMA FIFO Watermark Level */
427
/* Bits in CLCDC Interrupt Status Register (STATUS) */
428
#define CLCDC_STATUS_FUI (1 << 1) /* FIFO Underflow */
429
#define CLCDC_STATUS_BUI (1 << 2) /* LCD Next Base Address Update */
430
#define CLCDC_STATUS_VCI (1 << 3) /* Vertical Compare */
431
#define CLCDC_STATUS_MBEI (1 << 4) /* AMBA AHB Master Bus Error Status */
433
/* Bits in CLCDC Interrupt Register (INTERRUPT) */
434
#define CLCDC_INTERRUPT_FUIM (1 << 1) /* Masked FIFO Underflow Interrupt */
435
#define CLCDC_INTERRUPT_BUIM (1 << 2) /* Masked LCD Next Base Address Update Interrupt */
436
#define CLCDC_INTERRUPT_VCIM (1 << 3) /* Masked Vertical Compare Interrupt */
437
#define CLCDC_INTERRUPT_MBEIM (1 << 4) /* Masked AMBA AHB Master Bus Error Interrupt */
440
/******************************************/
441
/* Advanced LCD Interface (ALI) registers */
442
/******************************************/
444
#define ALI_BASE LH7A404_ALI_BASE
446
#define ALI_SETUP __REG32(ALI_BASE + 0x00) /* ALI Setup Register */
447
#define ALI_CONTROL __REG32(ALI_BASE + 0x04) /* ALI Control Register */
448
#define ALI_TIMING1 __REG32(ALI_BASE + 0x08) /* ALI Timing Register 1 */
449
#define ALI_TIMING2 __REG32(ALI_BASE + 0x0C) /* ALI Timing Register 2 */
451
/* Bits in ALI Setup Register */
452
#define ALI_SETUP_CR_MSK (0x03) /* Conversion Mode Select */
453
#define ALI_SETUP_CR_ACTIVE 0x01 /* Active Mode */
454
#define ALI_SETUP_CR_BYPASS 0x00 /* Bypass Mode (for STN or TFT panels) */
455
#define ALI_SETUP_LBR (1 << 2) /* Left Before Right */
456
#define ALI_SETUP_UBL (1 << 3) /* Upper Before Lower */
457
#define ALI_SETUP_PPL_SHIFT 4
458
#define ALI_SETUP_PPL_MSK (0x1FF << 4) /* Pixels Per Line */
459
#define ALI_SETUP_ALIEN (1 << 13) /* ALI Enable */
461
/* Bits in ALI Control Register */
462
#define ALI_CONTROL_LCDSPSEN (1 << 0) /* LCDSPS Enable (Row Reset) */
463
#define ALI_CONTROL_LCDCLSEN (1 << 1) /* LCDCLS Enable (Gate Driver Clock) */
465
/* Bits in ALI Timing Register 1 */
466
#define ALI_TIMING1_LPDEL_SHFT 0
467
#define ALI_TIMING1_LPDEL_MSK (0x0F << 0) /* LCDLP Delay */
468
#define ALI_TIMING1_REVDEL_SHFT 4
469
#define ALI_TIMING1_REVDEL_MSK (0x0F << 4) /* Polarity-Reversal Delay */
470
#define ALI_TIMING1_PSCLS_SHFT 8
471
#define ALI_TIMING1_PSCLS_MSK (0x0F << 8) /* LCDPS and LCDCLS Delay */
473
/* Bits in ALI Timing Register 2 */
474
#define ALI_TIMING2_PS2CLS2_SHFT 0
475
#define ALI_TIMING2_PS2CLS2_MSK (0x1FF) /* LCDSPL and LCDCLS Delay 2 */
476
#define ALI_TIMING2_SPLDEL_SHFT 9
477
#define ALI_TIMING2_SPLDEL_MSK (0x7F << 9) /* LCDSPL Delay */
481
/*******************************************/
482
/* Synchronous Serial Port (SSP) registers */
483
/*******************************************/
485
#define SSP_BASE LH7A404_SSP_BASE
487
#define SSP_CR0 __REG32(SSP_BASE + 0x00) /* Control Register 0 */
488
#define SSP_CR1 __REG32(SSP_BASE + 0x04) /* Control Register 1 */
489
#define SSP_IIR __REG32(SSP_BASE + 0x08) /* Interrupt Identification Register (RO) */
490
#define SSP_ROEOI __REG32(SSP_BASE + 0x08) /* Receive Overrun End-of-Interrupt (WO) */
491
#define SSP_DR __REG32(SSP_BASE + 0x0C) /* Data Register */
492
#define SSP_CPR __REG32(SSP_BASE + 0x10) /* Clock Prescale Register */
493
#define SSP_SR __REG32(SSP_BASE + 0x14) /* Status Register */
495
/* Bits in SSP Control Register 0 */
496
#define SSP_CR0_DSS (0x0F << 0) /* Data Size Selection */
497
#define SSP_CR0_DSS_16 (0x0F << 0) /* 16 bit */
498
#define SSP_CR0_DSS_15 (0x0E << 0) /* 15 bit */
499
#define SSP_CR0_DSS_14 (0x0D << 0) /* 14 bit */
500
#define SSP_CR0_DSS_13 (0x0C << 0) /* 13 bit */
501
#define SSP_CR0_DSS_12 (0x0B << 0) /* 12 bit */
502
#define SSP_CR0_DSS_11 (0x0A << 0) /* 11 bit */
503
#define SSP_CR0_DSS_10 (0x09 << 0) /* 10 bit */
504
#define SSP_CR0_DSS_9 (0x08 << 0) /* 9 bit */
505
#define SSP_CR0_DSS_8 (0x07 << 0) /* 8 bit */
506
#define SSP_CR0_DSS_7 (0x06 << 0) /* 7 bit */
507
#define SSP_CR0_DSS_6 (0x05 << 0) /* 6 bit */
508
#define SSP_CR0_DSS_5 (0x04 << 0) /* 5 bit */
509
#define SSP_CR0_DSS_4 (0x03 << 0) /* 4 bit */
510
#define SSP_CR0_FRF (0x03 << 4) /* Frame Format */
511
#define SSP_CR0_FRF_MOT (0x00 << 4) /* Motorola SPI frame format */
512
#define SSP_CR0_FRF_TI (0x01 << 4) /* TI synchronous serial frame format */
513
#define SSP_CR0_FRF_NAT (0x02 << 4) /* National MICROWIRE frame format */
514
#define SSP_CR0_SSE (1 << 7) /* SSP Enable */
515
#define SSP_CR0_SCR (0xFF << 8) /* Serial Clock Rate */
517
/* Bits in SSP Control Register 1 */
518
#define SSP_CR1_RXSIEN (1 << 0) /* Receive FIFO Service Interrupt Enable */
519
#define SSP_CR1_TXSIEN (1 << 1) /* Transmit FIFO Service Interrupt Enable */
520
#define SSP_CR1_LBM (1 << 2) /* Loopback Mode */
521
#define SSP_CR1_SPO (1 << 3) /* SPI Polarity */
522
#define SSP_CR1_SPH (1 << 4) /* SPI Phase */
523
#define SSP_CR1_RXOIEN (1 << 5) /* Receive Overrun Interrupt Enable */
524
#define SSP_CR1_FEN (1 << 6) /* FIFO Enable */
525
#define SSP_CR1_TXIIEN (1 << 7) /* Transmit Idle Interrupt Enable */
527
/* Bits in SSP Interrupt Identification Register */
528
#define SSP_IIR_RXSI (1 << 0) /* Receive FIFO Service Request Interrupt */
529
#define SSP_IIR_TXSI (1 << 1) /* Transmit FIFO Service Request Interrupt */
530
#define SSP_IIR_RXOI (1 << 6) /* Receive FIFO Overrun Interrupt */
531
#define SSP_IIR_TXII (1 << 7) /* Transmit Idle Interrupt */
533
/* Bits in SSP Status Register */
534
#define SSP_SR_TNF (1 << 1) /* Transmit FIFO Not Full */
535
#define SSP_SR_RNE (1 << 2) /* Receive FIFO Not Empty */
536
#define SSP_SR_BSY (1 << 3) /* Busy */
537
#define SSP_SR_THE (1 << 4) /* Transmit FIFO Half Empty */
538
#define SSP_SR_RHF (1 << 5) /* Receive FIFO Half Full */
539
#define SSP_SR_ROR (1 << 6) /* Receive Overrun */
540
#define SSP_SR_TFE (1 << 7) /* Transmit FIFO Empty */
541
#define SSP_SR_RFF (1 << 8) /* Receive FIFO Full */
545
/*******************/
546
/* Timer registers */
547
/*******************/
549
#define TIMER_BASE LH7A404_TIMER_BASE
551
#define TIMER_LOAD1 __REG32(TIMER_BASE + 0x00) /* Timer 1 initial value */
552
#define TIMER_VALUE1 __REG32(TIMER_BASE + 0x04) /* Timer 1 current value */
553
#define TIMER_CONTROL1 __REG32(TIMER_BASE + 0x08) /* Timer 1 control word */
554
#define TIMER_EOI1 __REG32(TIMER_BASE + 0x0C) /* Timer 1 interrupt clear */
556
#define TIMER_LOAD2 __REG32(TIMER_BASE + 0x20) /* Timer 2 initial value */
557
#define TIMER_VALUE2 __REG32(TIMER_BASE + 0x24) /* Timer 2 current value */
558
#define TIMER_CONTROL2 __REG32(TIMER_BASE + 0x28) /* Timer 2 control word */
559
#define TIMER_EOI2 __REG32(TIMER_BASE + 0x2C) /* Timer 2 interrupt clear */
561
#define TIMER_BUZZCON __REG32(TIMER_BASE + 0x40) /* Buzzer configuration */
563
#define TIMER_LOAD3 __REG32(TIMER_BASE + 0x80) /* Timer 3 initial value */
564
#define TIMER_VALUE3 __REG32(TIMER_BASE + 0x84) /* Timer 3 current value */
565
#define TIMER_CONTROL3 __REG32(TIMER_BASE + 0x88) /* Timer 3 control word */
566
#define TIMER_EOI3 __REG32(TIMER_BASE + 0x8C) /* Timer 3 interrupt clear */
568
#define TIMER_C_ENABLE (1 << 7)
569
#define TIMER_C_PERIODIC (1 << 6)
570
#define TIMER_C_FREERUNNING (0)
571
#define TIMER_C_2KHZ (0x00) /* 1.994 kHz */
572
#define TIMER_C_508KHZ (0x08) /* 508.469 kHz */
580
Direction of port pin has different meaning for ports
581
Port C,D,G: 0 == output, 1 == input
582
Port A,B,E,F,H: 0 == input, 1 == output
585
#define GPIO_BASE LH7A404_GPIO_BASE
587
#define GPIO_PAD __REG32(GPIO_BASE + 0x00) /* Port A Data register */
588
#define GPIO_PBD __REG32(GPIO_BASE + 0x04) /* Port B Data register */
589
#define GPIO_PCD __REG32(GPIO_BASE + 0x08) /* Port C Data register */
590
#define GPIO_PDD __REG32(GPIO_BASE + 0x0C) /* Port D Data register */
591
#define GPIO_PADD __REG32(GPIO_BASE + 0x10) /* Port A Data Direction register */
592
#define GPIO_PBDD __REG32(GPIO_BASE + 0x14) /* Port B Data Direction register */
593
#define GPIO_PCDD __REG32(GPIO_BASE + 0x18) /* Port C Data Direction register */
594
#define GPIO_PDDD __REG32(GPIO_BASE + 0x1C) /* Port D Data Direction register */
595
#define GPIO_PED __REG32(GPIO_BASE + 0x20) /* Port E Data register */
596
#define GPIO_PEDD __REG32(GPIO_BASE + 0x24) /* Port E Data Direction register */
597
#define GPIO_KBDCTL __REG32(GPIO_BASE + 0x28) /* Keyboard Control register */
598
#define GPIO_PINMUX __REG32(GPIO_BASE + 0x2C) /* Pin Multiplexing register */
599
#define GPIO_PFD __REG32(GPIO_BASE + 0x30) /* Port F Data register */
600
#define GPIO_PFDD __REG32(GPIO_BASE + 0x34) /* Port F Data Direction register */
601
#define GPIO_PGD __REG32(GPIO_BASE + 0x38) /* Port G Data register */
602
#define GPIO_PGDD __REG32(GPIO_BASE + 0x3C) /* Port G Data Direction register */
603
#define GPIO_PHD __REG32(GPIO_BASE + 0x40) /* Port H Data register */
604
#define GPIO_PHDD __REG32(GPIO_BASE + 0x44) /* Port H Data Direction register */
605
#define GPIO_INTTYPE1 __REG32(GPIO_BASE + 0x4C) /* IRQ edge (1) or lvl (0) */
606
#define GPIO_INTTYPE2 __REG32(GPIO_BASE + 0x50) /* IRQ activ hi/lo or rising/falling */
607
#define GPIO_GPIOFEOI __REG32(GPIO_BASE + 0x54) /* GPIOF end of IRQ */
608
#define GPIO_GPIOINTEN __REG32(GPIO_BASE + 0x58) /* GPIOF IRQ enable */
609
#define GPIO_INTSTATUS __REG32(GPIO_BASE + 0x5C) /* GPIOF IRQ latch */
610
#define GPIO_RAWINTSTATUS __REG32(GPIO_BASE + 0x60) /* GPIOF IRQ raw */
611
#define GPIO_GPIODB __REG32(GPIO_BASE + 0x64) /* GPIOF Debounce */
612
#define GPIO_PAPD __REG32(GPIO_BASE + 0x68) /* Port A Pin Data register */
613
#define GPIO_PBPD __REG32(GPIO_BASE + 0x6C) /* Port B Pin Data register */
614
#define GPIO_PCPD __REG32(GPIO_BASE + 0x70) /* Port C Pin Data register */
615
#define GPIO_PDPD __REG32(GPIO_BASE + 0x74) /* Port D Pin Data register */
616
#define GPIO_PEPD __REG32(GPIO_BASE + 0x78) /* Port E Pin Data register */
617
#define GPIO_PFPD __REG32(GPIO_BASE + 0x7C) /* Port F Pin Data register */
618
#define GPIO_PGPD __REG32(GPIO_BASE + 0x80) /* Port G Pin Data register */
619
#define GPIO_PHPD __REG32(GPIO_BASE + 0x84) /* Port H Pin Data register */
621
/* Bits in GPIO_PINMUX */
622
#define GPIO_PINMUX_PEOCON (1 << 0) /* Port E Output Control */
623
#define GPIO_PINMUX_PDOCON (1 << 1) /* Port D Output Control */
624
#define GPIO_PINMUX_CODECON (1 << 2) /* Codec Control (AC97) */
625
#define GPIO_PINMUX_UART3CON (1 << 3) /* UART3 Control */
633
#define UART1_BASE LH7A404_UART1_BASE
635
#define UART1_DATA __REG32(UART1_BASE + 0x00) /* Data Register */
636
#define UART1_FCON __REG32(UART1_BASE + 0x04) /* FIFO Control Register */
637
#define UART1_BRCON __REG32(UART1_BASE + 0x08) /* Baud Rate Control Register */
638
#define UART1_CON __REG32(UART1_BASE + 0x0C) /* Control Register */
639
#define UART1_STATUS __REG32(UART1_BASE + 0x10) /* Status Register */
640
#define UART1_RAWISR __REG32(UART1_BASE + 0x14) /* Raw Interrupt Status Register */
641
#define UART1_INTEN __REG32(UART1_BASE + 0x18) /* Interrupt Mask Register */
642
#define UART1_MISR __REG32(UART1_BASE + 0x1C) /* Masked Interrupt Status Register */
643
#define UART1_RES __REG32(UART1_BASE + 0x20) /* Receive Error Status + Clear Register */
644
#define UART1_EIC __REG32(UART1_BASE + 0x24) /* Error Interrupt Clear Register */
645
#define UART1_DMACR __REG32(UART1_BASE + 0x28) /* DMA Control Register */
647
#define UART2_BASE LH7A404_UART2_BASE
649
#define UART2_DATA __REG32(UART2_BASE + 0x00) /* Data Register */
650
#define UART2_FCON __REG32(UART2_BASE + 0x04) /* FIFO Control Register */
651
#define UART2_BRCON __REG32(UART2_BASE + 0x08) /* Baud Rate Control Register */
652
#define UART2_CON __REG32(UART2_BASE + 0x0C) /* Control Register */
653
#define UART2_STATUS __REG32(UART2_BASE + 0x10) /* Status Register */
654
#define UART2_RAWISR __REG32(UART2_BASE + 0x14) /* Raw Interrupt Status Register */
655
#define UART2_INTEN __REG32(UART2_BASE + 0x18) /* Interrupt Mask Register */
656
#define UART2_MISR __REG32(UART2_BASE + 0x1C) /* Masked Interrupt Status Register */
657
#define UART2_RES __REG32(UART2_BASE + 0x20) /* Receive Error Status + Clear Register */
658
#define UART2_EIC __REG32(UART2_BASE + 0x24) /* Error Interrupt Clear Register */
659
#define UART2_DMACR __REG32(UART2_BASE + 0x28) /* DMA Control Register */
661
#define UART3_BASE LH7A404_UART3_BASE
663
#define UART3_DATA __REG32(UART3_BASE + 0x00) /* Data Register */
664
#define UART3_FCON __REG32(UART3_BASE + 0x04) /* FIFO Control Register */
665
#define UART3_BRCON __REG32(UART3_BASE + 0x08) /* Baud Rate Control Register */
666
#define UART3_CON __REG32(UART3_BASE + 0x0C) /* Control Register */
667
#define UART3_STATUS __REG32(UART3_BASE + 0x10) /* Status Register */
668
#define UART3_RAWISR __REG32(UART3_BASE + 0x14) /* Raw Interrupt Status Register */
669
#define UART3_INTEN __REG32(UART3_BASE + 0x18) /* Interrupt Mask Register */
670
#define UART3_MISR __REG32(UART3_BASE + 0x1C) /* Masked Interrupt Status Register */
671
#define UART3_RES __REG32(UART3_BASE + 0x20) /* Receive Error Status + Clear Register */
672
#define UART3_EIC __REG32(UART3_BASE + 0x24) /* Error Interrupt Clear Register */
673
#define UART3_DMACR __REG32(UART3_BASE + 0x28) /* DMA Control Register */
675
/* Bits in DATA register (error flags on RX) */
676
#define UART_DATA_MSK (0xFF << 0)
677
#define UART_DATA_FE (1 << 8) /* Framing Error */
678
#define UART_DATA_PE (1 << 9) /* Parity Error */
679
#define UART_DATA_OE (1 << 10) /* Overrun Error */
680
#define UART_DATA_BE (1 << 11) /* Break Error */
682
/* Bits in FCON register */
683
#define UART_FCON_BRK (1 << 0) /* Break (Assert Break) */
684
#define UART_FCON_PEN (1 << 1) /* Parity Enable */
685
#define UART_FCON_EPS (1 << 2) /* Even Parity Set */
686
#define UART_FCON_STP2 (1 << 3) /* Stop bits (1 = 2 stop bits, 0 = 1 stop bit) */
687
#define UART_FCON_FEN (1 << 4) /* FIFO Enable */
688
#define UART_FCON_WLEN5 (0 << 5) /* Word Length: 5 bit data */
689
#define UART_FCON_WLEN6 (1 << 5) /* Word Length: 6 bit data */
690
#define UART_FCON_WLEN7 (2 << 5) /* Word Length: 7 bit data */
691
#define UART_FCON_WLEN8 (3 << 5) /* Word Length: 8 bit data */
693
/* Bits in CON register */
694
#define UART_CON_UARTEN (1 << 0) /* UART Enable */
695
#define UART_CON_SIRD (1 << 1) /* Serial Infrared disable (UART1) */
696
#define UART_CON_SIRLP (1 << 2) /* Serial Infrared Low Power (UART1) */
697
#define UART_CON_RXP (1 << 3) /* Receive Polarity */
698
#define UART_CON_TXP (1 << 4) /* Transmit Polarity */
699
#define UART_CON_MXP (1 << 5) /* Modem Transfer Polarity */
700
#define UART_CON_LBE (1 << 6) /* Loopback Enable */
701
#define UART_CON_SIRBD (1 << 7) /* Serial Infrared Blanking Disable (UART1) */
703
/* Bits in STATUS register */
704
#define UART_STATUS_CTS (1 << 0) /* Clear To Send (UART2/3) */
705
#define UART_STATUS_DSR (1 << 1) /* Data Set Ready (UART2/3) */
706
#define UART_STATUS_DCD (1 << 2) /* Data Carrier Detect (UART2/3) */
707
#define UART_STATUS_BUSY (1 << 3) /* UART busy */
708
#define UART_STATUS_RXFE (1 << 4) /* Receive FIFO empty */
709
#define UART_STATUS_TXFF (1 << 5) /* Transmit FIFO full */
710
#define UART_STATUS_RXFF (1 << 6) /* Receive FIFO full */
711
#define UART_STATUS_TXFE (1 << 7) /* Transmit FIFO empty */
713
/* Bits in RAWISR register (Read) */
714
#define UART_RAWISR_RI (1 << 0) /* Receive Interrupt */
715
#define UART_RAWISR_TI (1 << 1) /* Transmit Interrupt */
716
#define UART_RAWISR_MI (1 << 2) /* Modem Status Interrupt */
717
#define UART_RAWISR_RTI (1 << 3) /* Receive Timeout Interrupt */
718
#define UART_RAWISR_FEI (1 << 4) /* Frame Error Interrupt */
719
#define UART_RAWISR_PEI (1 << 5) /* Parity Error Interrupt */
720
#define UART_RAWISR_BEI (1 << 6) /* Break Error Interrupt */
721
#define UART_RAWISR_OEI (1 << 7) /* Overrun Error Interrupt */
723
/* Bits in INTEN register */
724
#define UART_INTEN_REN (1 << 0) /* Receive Interrupt Enable */
725
#define UART_INTEN_TEN (1 << 1) /* Transmit Interrupt Enable */
726
#define UART_INTEN_MEN (1 << 2) /* Modem Status Interrupt Enable */
727
#define UART_INTEN_RTEN (1 << 3) /* Receive Timeout Interrupt Enable */
728
#define UART_INTEN_FEEN (1 << 4) /* Frame Error Interrupt Enable */
729
#define UART_INTEN_PEEN (1 << 5) /* Parity Error Interrupt Enable */
730
#define UART_INTEN_BEEN (1 << 6) /* Break Error Interrupt Enable */
731
#define UART_INTEN_OEEN (1 << 7) /* Overrun Error Interrupt Enable */
733
/* Bits in MISR register */
734
#define UART_MISR_RIM (1 << 0) /* Masked Receive Interrupt */
735
#define UART_MISR_TIM (1 << 1) /* Masked Transmit Interrupt */
736
#define UART_MISR_MIM (1 << 2) /* Masked Modem Status Interrupt */
737
#define UART_MISR_RTIM (1 << 3) /* Masked Receive Timeout Interrupt */
738
#define UART_MISR_FEIM (1 << 4) /* Masked Frame Error Interrupt */
739
#define UART_MISR_PEIM (1 << 5) /* Masked Parity Error Interrupt */
740
#define UART_MISR_BEIM (1 << 6) /* Masked Break Error Interrupt */
741
#define UART_MISR_OEIM (1 << 7) /* Masked Overrun Error Interrupt */
743
/* Bits in RES register */
744
#define UART_RES_FE (1 << 0) /* Frame Error */
745
#define UART_RES_PE (1 << 1) /* Parity Error */
746
#define UART_RES_OE (1 << 2) /* Overrun Error */
747
#define UART_RES_BE (1 << 3) /* Break Error */
749
/* Bits in EIC register */
750
#define UART_EIC_FEIC (1 << 0) /* Masked Frame Error Interrupt Clear */
751
#define UART_EIC_PEIC (1 << 1) /* Masked Parity Error Interrupt Clear */
752
#define UART_EIC_OEIC (1 << 2) /* Masked Overrun Error Interrupt Clear */
753
#define UART_EIC_BEIC (1 << 3) /* Masked Break Error Interrupt Clear */
755
/* Bits in DMACR register */
756
#define UART_DMACR_RDE (1 << 0) /* Receive DMA Enable */
757
#define UART_DMACR_TDE (1 << 1) /* Transmit DMA Enable */
758
#define UART_DMACR_DE (1 << 2) /* DMA On Error */
762
/***********************************/
763
/* MultiMediaCard (MMC) Controller */
764
/***********************************/
766
#define MMC_BASE LH7A404_MMC_BASE
768
#define MMC_CLKC __REG32(MMC_BASE + 0x00) /* Clock control register */
769
#define MMC_STATUS __REG32(MMC_BASE + 0x04) /* Controller status register */
770
#define MMC_RATE __REG32(MMC_BASE + 0x08) /* SD/MMC clock divider register */
771
#define MMC_PREDIV __REG32(MMC_BASE + 0x0C) /* SD/MMC predivide register */
772
#define MMC_CMDCON __REG32(MMC_BASE + 0x14) /* Command control register */
773
#define MMC_RES_TO __REG32(MMC_BASE + 0x18) /* Response timeout register */
774
#define MMC_READ_TO __REG32(MMC_BASE + 0x1C) /* Read timeout register */
775
#define MMC_BLK_LEN __REG32(MMC_BASE + 0x20) /* Block length register */
776
#define MMC_NOB __REG32(MMC_BASE + 0x24) /* Number Of Blocks register */
777
#define MMC_INT_STATUS __REG32(MMC_BASE + 0x28) /* Interrupt status register */
778
#define MMC_EOI __REG32(MMC_BASE + 0x2C) /* End Of Interrupt register */
779
#define MMC_INT_MASK __REG32(MMC_BASE + 0x34) /* Interrupt mask register */
780
#define MMC_CMD __REG32(MMC_BASE + 0x38) /* Command number register */
781
#define MMC_ARGUMENT __REG32(MMC_BASE + 0x3C) /* Command argument register */
782
#define MMC_RES_FIFO __REG32(MMC_BASE + 0x40) /* Response FIFO location */
783
#define MMC_DATA_FIFO __REG32(MMC_BASE + 0x48) /* FIFO data register */
785
/* Bits in MMC_CLKC */
786
#define MMC_CLKC_STOP_CLK (1 << 0) /* Stop Clock */
787
#define MMC_CLKC_START_CLK (1 << 1) /* Start Clock */
789
/* Bits in MMC_STATUS */
790
#define MMC_STATUS_TOREAD (1 << 0) /* Read Timeout */
791
#define MMC_STATUS_TORES (1 << 1) /* Response Timeout */
792
#define MMC_STATUS_CRCWRITE (1 << 2) /* CRC Write Error */
793
#define MMC_STATUS_CRCREAD (1 << 3) /* CRC Read Error */
794
#define MMC_STATUS_CRC (1 << 5) /* Response CRC Error */
795
#define MMC_STATUS_FIFO_EMPTY (1 << 6) /* FIFO Empty */
796
#define MMC_STATUS_FIFO_FULL (1 << 7) /* FIFO Full */
797
#define MMC_STATUS_CLK_DIS (1 << 8) /* Clock Disabled */
798
#define MMC_STATUS_TRANDONE (1 << 11) /* Data Transfer Done */
799
#define MMC_STATUS_DONE (1 << 12) /* Program Done */
800
#define MMC_STATUS_ENDRESP (1 << 13) /* End Command Response */
802
/* Bits in MMC_PREDIV */
803
#define MMC_PREDIV_MMC_PREDIV (0x0F << 0) /* SD/MMC Predivisor */
804
#define MMC_PREDIV_MMC_EN (1 << 4) /* SD/MMC Enable */
805
#define MMC_PREDIV_APB_RD_EN (1 << 5) /* APB Read Enable */
807
/* Bits in MMC_CMDCON */
808
#define MMC_CMDCON_ABORT (1 << 13) /* Abort Transaction */
809
#define MMC_CMDCON_SET_READ_WRITE (1 << 12) /* Set Transaction to Read (0) or Write (1) */
810
#define MMC_CMDCON_MULTI_BLK4_INTEN (1 << 11) /* Multiple Block Interrupt Enable */
811
#define MMC_CMDCON_READ_WAIT_EN (1 << 10) /* Enable Read Wait States */
812
#define MMC_CMDCON_SDIO_EN (1 << 9) /* Enable SD Input/Output */
813
#define MMC_CMDCON_BIG_ENDIAN (1 << 8) /* Enable Big Endian Mode for MMC */
814
#define MMC_CMDCON_WIDE (1 << 7) /* Enable Wide Mode for SD */
815
#define MMC_CMDCON_INITIALIZE (1 << 6) /* Enable 80-bit Initialization Sequence */
816
#define MMC_CMDCON_BUSY (1 << 5) /* Busy Expected */
817
#define MMC_CMDCON_STREAM (1 << 4) /* Stream Mode */
818
#define MMC_CMDCON_WRITE (1 << 3) /* Write Transfer Mode */
819
#define MMC_CMDCON_DATA_EN (1 << 2) /* Data Transfer Enable */
820
#define MMC_CMDCON_RESP_FORMAT_NONE (0 << 0) /* No Response */
821
#define MMC_CMDCON_RESP_FORMAT_R1 (1 << 0) /* Response Format R1 */
822
#define MMC_CMDCON_RESP_FORMAT_R2 (2 << 0) /* Response Format R2 */
823
#define MMC_CMDCON_RESP_FORMAT_R3 (3 << 0) /* Response Format R3 */
825
/* Bits in MMC_INT_STATUS, MMC_EOI + MMC_INT_MASK */
826
#define MMC_INT_SDIO_INT (1 << 5) /* SD Interrupt */
827
#define MMC_INT_BUS_CLOCK_STOPPED (1 << 4) /* Bus Clock Stopped Interrupt */
828
#define MMC_INT_BUF_READY (1 << 3) /* Buffer Ready Interrupt */
829
#define MMC_INT_END_CMD (1 << 2) /* End Command Response Interrupt */
830
#define MMC_INT_DONE (1 << 1) /* Program Done Interrupt */
831
#define MMC_INT_DATA_TRAN (1 << 0) /* Data Transfer Done Interrupt */
834
/*************************************/
835
/* Universal Serial Bus (USB) Device */
836
/*************************************/
838
#define USB_BASE LH7A404_USB_BASE
840
#define USB_FAR __REG32(USB_BASE + 0x00) /* Function Address Register */
841
#define USB_PMR __REG32(USB_BASE + 0x04) /* Power Management Register */
842
#define USB_IIR __REG32(USB_BASE + 0x08) /* IN Interrupt Register Bank */
843
#define USB_OIR __REG32(USB_BASE + 0x10) /* OUT Interrupt Register Bank */
844
#define USB_UIR __REG32(USB_BASE + 0x18) /* USB Interrupt Register Bank */
845
#define USB_IIE __REG32(USB_BASE + 0x1C) /* IN Interrupt Enable Register Bank */
846
#define USB_OIE __REG32(USB_BASE + 0x24) /* OUT Interrupt Enable Register Bank */
847
#define USB_UIE __REG32(USB_BASE + 0x2C) /* USB Interrupt Enable Register Bank */
848
#define USB_FRAME1 __REG32(USB_BASE + 0x30) /* Frame Number1 Register */
849
#define USB_FRAME2 __REG32(USB_BASE + 0x34) /* Frame Number2 Register */
850
#define USB_INDEX __REG32(USB_BASE + 0x38) /* Index Register */
851
#define USB_INMAXP __REG32(USB_BASE + 0x40) /* IN Maximum Packet Size Register */
852
#define USB_INCSR1 __REG32(USB_BASE + 0x44) /* Control and Status Register (EP0,1,3) */
853
#define USB_INCSR2 __REG32(USB_BASE + 0x48) /* IN Control Register (EP1,EP3) */
854
#define USB_OUTMAXP __REG32(USB_BASE + 0x4C) /* OUT Maximum Packet Size Register */
855
#define USB_OUTCSR1 __REG32(USB_BASE + 0x50) /* OUT Control and Status Register */
856
#define USB_OUTCSR2 __REG32(USB_BASE + 0x54) /* OUT Control Register */
857
#define USB_COUNT1 __REG32(USB_BASE + 0x58) /* OUT FIFO Write Count1 Register */
858
#define USB_EP0FIFO __REG32(USB_BASE + 0x80) /* EP0 (Control, 8 Bytes) */
859
#define USB_EP1FIFO __REG32(USB_BASE + 0x84) /* EP1 (IN BULK, 64 Bytes) */
860
#define USB_EP2FIFO __REG32(USB_BASE + 0x88) /* EP2 (OUT BULK, 64 Bytes) */
861
#define USB_EP3FIFO __REG32(USB_BASE + 0x8C) /* EP3 (IN Interrupt, 64 Bytes) */
863
/* Bits in USB_FAR */
864
#define USB_FAR_FUNCTION_ADDR (0x7F << 0) /* Function Address field */
865
#define USB_FAR_ADDR_UPDATE (1 << 7) /* Address Update */
867
/* Bits in USB_PMR */
868
#define USB_PMR_ENABLE_SUSPEND (1 << 0) /* SUSPEND Enable */
869
#define USB_PMR_SUSPEND_MODE (1 << 1) /* SUSPEND Mode active */
870
#define USB_PMR_UC_RESUME (1 << 2) /* UC RESUME */
871
#define USB_PMR_USB_RESET (1 << 3) /* USB RESET active */
872
#define USB_PMR_USB_ENABLE (1 << 4) /* USB Enable */
873
#define USB_PMR_DCP_CTRL (1 << 5) /* DCP Pin Control (0=pulled up, 1=floating) */
875
/* Bits in USB_IIR */
876
#define USB_IIR_EP0 (1 << 0) /* End Point 0 Interrupt */
877
#define USB_IIR_EP1IN (1 << 1) /* End Point 1 IN Interrupt */
878
#define USB_IIR_EP3IN (1 << 3) /* End Point 3 IN Interrupt */
880
/* Bits in USB_OIR */
881
#define USB_OIR_EP2OUT (1 << 2) /* End Point 2 OUT Interrupt */
883
/* Bits in USB_UIR */
884
#define USB_UIR_SUSINT (1 << 0) /* SUSPEND Interrupt */
885
#define USB_UIR_RESINT (1 << 1) /* RESUME Interrupt */
886
#define USB_UIR_URINT (1 << 2) /* USB RESET Interrupt */
888
/* Bits in USB_IIE */
889
#define USB_IIE_EP0EN (1 << 0) /* End Point 0 Interrupt Enable */
890
#define USB_IIE_EP1INEN (1 << 1) /* End Point 1 IN Interrupt Enable */
891
#define USB_IIE_EP3INEN (1 << 3) /* End Point 3 IN Interrupt Enable */
893
/* Bits in USB_OIE */
894
#define USB_OIE_EP2OUTEN (1 << 2) /* End Point 2 OUT Interrupt Enable */
896
/* Bits in USB_UIE */
897
#define USB_UIE_SUSINTEN (1 << 0) /* SUSPEND Interrupt Enable (also RESUME) */
898
#define USB_UIE_URINTEN (1 << 2) /* USB RESET Interrupt Enable */
900
/* Values for USB_INDEX */
901
#define USB_INDEX_EP0 0
902
#define USB_INDEX_EP1 1
903
#define USB_INDEX_EP2 2
904
#define USB_INDEX_EP3 3
906
/* Values for USB_MAXP */
907
#define USB_MAXP_MAXP_8 1
908
#define USB_MAXP_MAXP_16 2
909
#define USB_MAXP_MAXP_24 3
910
#define USB_MAXP_MAXP_32 4
911
#define USB_MAXP_MAXP_40 5
912
#define USB_MAXP_MAXP_48 6
913
#define USB_MAXP_MAXP_56 7
914
#define USB_MAXP_MAXP_64 8
916
/* Bits in USB_INCSR1 */
917
#define USB_INCSR1_IN_PKT_RDY (1 << 0) /* IN Packet Ready */
918
#define USB_INCSR1_FIFO_NE (1 << 1) /* FIFO Not Empty */
919
#define USB_INCSR1_FIFO_FLUSH (1 << 3) /* FIFO Flush Request */
920
#define USB_INCSR1_SEND_STALL (1 << 4) /* Send Stall Handshake to USB */
921
#define USB_INCSR1_SENT_STALL (1 << 5) /* STALL Send Acknowledge */
922
#define USB_INCSR1_CLRTOG (1 << 6) /* Clear Data Toggle */
924
/* Bits in USB_INCSR2 */
925
#define USB_INCSR2_USB_DMA_EN (1 << 4) /* USB DMA Enable */
926
#define USB_INCSR2_AUTO_SET (1 << 7) /* Auto Set IN_PKT_RDY Bit */
928
/* Bits in USB_OUTCSR1 */
929
#define USB_OUTCSR1_OUT_PKT_RDY (1 << 0) /* OUT Packet Ready */
930
#define USB_OUTCSR1_FIFO_FULL (1 << 1) /* FIFO Full */
931
#define USB_OUTCSR1_FIFO_FLUSH (1 << 4) /* Flush OUT FIFO */
932
#define USB_OUTCSR1_SEND_STALL (1 << 5) /* Send Stall Handshake */
933
#define USB_OUTCSR1_SENT_STALL (1 << 6) /* STALL Handshake Sent */
934
#define USB_OUTCSR1_CL_DATATOG (1 << 7) /* Clear Data Toggle Sequence Bit */
936
/* Bits in USB_OUTCSR2 */
937
#define USB_OUTCSR2_USB_DMA_EN (1 << 4) /* USB DMA Enable */
938
#define USB_OUTCSR2_AUTO_CLR (1 << 7) /* Auto Clear OUT_PKT_RDY Bit */
940
/* Bits in EP0CSR (== USB_INCSR1 with USB_INDEX = 0) */
941
#define USB_EP0CSR_OUT_PKT_RDY (1 << 0) /* OUT Packet Ready (RO) */
942
#define USB_EP0CSR_IN_PKT_RDY (1 << 1) /* IN Packet Ready */
943
#define USB_EP0CSR_SENT_STALL (1 << 2) /* Sent STALL Handshake */
944
#define USB_EP0CSR_DATA_END (1 << 3) /* Data End */
945
#define USB_EP0CSR_SETUP_END (1 << 4) /* Setup Ends (RO) */
946
#define USB_EP0CSR_SEND_STALL (1 << 5) /* Send Stall Handshake to USB */
947
#define USB_EP0CSR_CLR_OUT (1 << 6) /* Clear OUT Packet Ready Bit */
948
#define USB_EP0CSR_CLR_SETUP_END (1 << 7) /* Clear Setup End Bit */
951
/***********************/
952
/* USB Host Controller */
953
/***********************/
955
#define USBH_BASE LH7A404_USBH_BASE
957
#define USBH_CMDSTATUS __REG32(USBH_BASE + 0x08)
961
/*******************/
962
/* AC97 Controller */
963
/*******************/
965
#define AC97_BASE LH7A404_AC97_BASE
967
#define AC97_DR1 __REG32(AC97_BASE + 0x00) /* FIFO1 Data Register */
968
#define AC97_RXCR1 __REG32(AC97_BASE + 0x04) /* FIFO1 Receive Control Register */
969
#define AC97_TXCR1 __REG32(AC97_BASE + 0x08) /* FIFO1 Transmit Control Register */
970
#define AC97_SR1 __REG32(AC97_BASE + 0x0C) /* FIFO1 Status Register */
971
#define AC97_RISR1 __REG32(AC97_BASE + 0x10) /* FIFO1 Raw Interrupt Status Register */
972
#define AC97_ISR1 __REG32(AC97_BASE + 0x14) /* FIFO1 Interrupt Status Register */
973
#define AC97_IE1 __REG32(AC97_BASE + 0x18) /* FIFO1 Interrupt Enable Register */
975
#define AC97_DR2 __REG32(AC97_BASE + 0x20) /* FIFO2 Data Register */
976
#define AC97_RXCR2 __REG32(AC97_BASE + 0x24) /* FIFO2 Receive Control Register */
977
#define AC97_TXCR2 __REG32(AC97_BASE + 0x28) /* FIFO2 Transmit Control Register */
978
#define AC97_SR2 __REG32(AC97_BASE + 0x2C) /* FIFO2 Status Register */
979
#define AC97_RISR2 __REG32(AC97_BASE + 0x30) /* FIFO2 Raw Interrupt Status Register */
980
#define AC97_ISR2 __REG32(AC97_BASE + 0x34) /* FIFO2 Interrupt Status Register */
981
#define AC97_IE2 __REG32(AC97_BASE + 0x38) /* FIFO2 Interrupt Enable Register */
983
#define AC97_DR3 __REG32(AC97_BASE + 0x40) /* FIFO3 Data Register */
984
#define AC97_RXCR3 __REG32(AC97_BASE + 0x44) /* FIFO3 Receive Control Register */
985
#define AC97_TXCR3 __REG32(AC97_BASE + 0x48) /* FIFO3 Transmit Control Register */
986
#define AC97_SR3 __REG32(AC97_BASE + 0x4C) /* FIFO3 Status Register */
987
#define AC97_RISR3 __REG32(AC97_BASE + 0x50) /* FIFO3 Raw Interrupt Status Register */
988
#define AC97_ISR3 __REG32(AC97_BASE + 0x54) /* FIFO3 Interrupt Status Register */
989
#define AC97_IE3 __REG32(AC97_BASE + 0x58) /* FIFO3 Interrupt Enable Register */
991
#define AC97_DR4 __REG32(AC97_BASE + 0x60) /* FIFO4 Data Register */
992
#define AC97_RXCR4 __REG32(AC97_BASE + 0x64) /* FIFO4 Receive Control Register */
993
#define AC97_TXCR4 __REG32(AC97_BASE + 0x68) /* FIFO4 Transmit Control Register */
994
#define AC97_SR4 __REG32(AC97_BASE + 0x6C) /* FIFO4 Status Register */
995
#define AC97_RISR4 __REG32(AC97_BASE + 0x70) /* FIFO4 Raw Interrupt Status Register */
996
#define AC97_ISR4 __REG32(AC97_BASE + 0x74) /* FIFO4 Interrupt Status Register */
997
#define AC97_IE4 __REG32(AC97_BASE + 0x78) /* FIFO4 Interrupt Enable Register */
999
#define AC97_S1DATA __REG32(AC97_BASE + 0x80) /* Data Register on Slot 1 */
1000
#define AC97_S2DATA __REG32(AC97_BASE + 0x84) /* Data Register on Slot 2 */
1001
#define AC97_S12DATA __REG32(AC97_BASE + 0x88) /* Data Register on Slot 12 */
1002
#define AC97_RGIS __REG32(AC97_BASE + 0x8C) /* Raw Global Interrupt Status */
1003
#define AC97_GIS __REG32(AC97_BASE + 0x90) /* Global Interrupt Status */
1004
#define AC97_GIEN __REG32(AC97_BASE + 0x94) /* Global Interrupt Enable */
1005
#define AC97_GEOI __REG32(AC97_BASE + 0x98) /* Global Interrupt Clear */
1006
#define AC97_GCR __REG32(AC97_BASE + 0x9C) /* Global Control Register */
1007
#define AC97_RESET __REG32(AC97_BASE + 0xA0) /* Reset Control Register */
1008
#define AC97_SYNC __REG32(AC97_BASE + 0xA4) /* Sync Control Register */
1009
#define AC97_GCIS __REG32(AC97_BASE + 0xA8) /* Global Control FIFO Interrupt Status */
1012
/*******************************/
1013
/* Audio Codec Interface (ACI) */
1014
/*******************************/
1016
#define ACI_BASE LH7A404_ACI_BASE
1018
#define ACI_DATA __REG32(ACI_BASE + 0x00) /* Data Register */
1019
#define ACI_CTL __REG32(ACI_BASE + 0x04) /* Control Register */
1020
#define ACI_STATUS __REG32(ACI_BASE + 0x08) /* Status Register */
1021
#define ACI_EOI __REG32(ACI_BASE + 0x0C) /* End-Of-Interrupt Register */
1022
#define ACI_CLKDIV __REG32(ACI_BASE + 0x10) /* Clock Divider Register */
1024
#define ACI_DATA_MASK 0xFF /* valid bits in Data Register */
1026
/* Bits in Control Register */
1027
#define ACI_CTL_TXEN (1 << 0) /* Transmit Enable */
1028
#define ACI_CTL_RXEN (1 << 1) /* Receive Enable */
1029
#define ACI_CTL_RXIE (1 << 2) /* Receive Interrupt Enable */
1030
#define ACI_CTL_TXIE (1 << 3) /* Transmit Interrupt Enable */
1031
#define ACI_CTL_LB (1 << 4) /* Loopback */
1032
#define ACI_CTL_TXEPCLKEN (1 << 5) /* Transmit FIFO Empty Stop Clock Enable */
1034
/* Bits in Status Register */
1035
#define ACI_STATUS_RXFE (1 << 0) /* Receive FIFO Empty */
1036
#define ACI_STATUS_TXFF (1 << 1) /* Transmit FIFO Full */
1037
#define ACI_STATUS_RXFF (1 << 2) /* Receive FIFO Full */
1038
#define ACI_STATUS_TXFE (1 << 3) /* Transmit FIFO Empty */
1039
#define ACI_STATUS_RXI (1 << 4) /* Receive Interrupt */
1040
#define ACI_STATUS_TXI (1 << 5) /* Transmit Interrupt */
1041
#define ACI_STATUS_RXBUSY (1 << 6) /* Receive Busy */
1042
#define ACI_STATUS_TXBUSY (1 << 7) /* Transmit Busy */
1045
/*******************************/
1046
/* Pulse Width Modulator (PWM) */
1047
/*******************************/
1049
#define PWM_BASE LH7A404_PWM_BASE
1051
#define PWM_TC2 __REG32(PWM_BASE + 0x00) /* PWM2 Terminal Count Register */
1052
#define PWM_DC2 __REG32(PWM_BASE + 0x04) /* PWM2 Duty Cycle Register */
1053
#define PWM_EN2 __REG32(PWM_BASE + 0x08) /* PWM2 Enable Register */
1054
#define PWM_INV2 __REG32(PWM_BASE + 0x0C) /* PWM2 Invert Register */
1055
#define PWM_SYNC2 __REG32(PWM_BASE + 0x10) /* PWM2 Synchronous Register */
1056
#define PWM_TC3 __REG32(PWM_BASE + 0x20) /* PWM3 Terminal Count Register */
1057
#define PWM_DC3 __REG32(PWM_BASE + 0x24) /* PWM3 Duty Cycle Register */
1058
#define PWM_EN3 __REG32(PWM_BASE + 0x28) /* PWM3 Enable Register */
1059
#define PWM_INV3 __REG32(PWM_BASE + 0x2C) /* PWM3 Invert Register */
1061
/* Bits in PWM_ENx Register */
1062
#define PWM_EN_ENABLE (1 << 0) /* PWM Enable */
1064
/* Bits in PWM_INVx Register */
1065
#define PWM_INV_INV (1 << 0) /* Invert PWM Output */
1067
/* Bits in PWM_SYNC2 Register */
1068
#define PWM_SYNC2_MODCE (1 << 0) /* PWM Mode Select */
1069
#define PWM_SYNC2_SOURCE (1 << 1) /* PWM Sync Signal Source */
1073
/*************************************/
1074
/* Analog-to-Digital Converter (ADC) */
1075
/*************************************/
1077
#define ADC_BASE LH7A404_ADC_BASE
1079
#define ADC_HW __REG32(ADC_BASE + 0x00) /* High Word Register */
1080
#define ADC_LW __REG32(ADC_BASE + 0x04) /* Low Word Register */
1081
#define ADC_RR __REG32(ADC_BASE + 0x08) /* Results Register */
1082
#define ADC_IM __REG32(ADC_BASE + 0x0C) /* Interrupt Mask Register */
1083
#define ADC_PC __REG32(ADC_BASE + 0x10) /* Power Configuration Register */
1084
#define ADC_GC __REG32(ADC_BASE + 0x14) /* General Configuration Register */
1085
#define ADC_GS __REG32(ADC_BASE + 0x18) /* General Status Register */
1086
#define ADC_IS __REG32(ADC_BASE + 0x1C) /* Raw Interrupt Status Register */
1087
#define ADC_FS __REG32(ADC_BASE + 0x20) /* FIFO Status Register */
1088
#define ADC_HWCB0 __REG32(ADC_BASE + 0x24) /* High Word Control Bank Register 0 */
1089
#define ADC_HWCB1 __REG32(ADC_BASE + 0x28) /* High Word Control Bank Register 1 */
1090
#define ADC_HWCB2 __REG32(ADC_BASE + 0x2C) /* High Word Control Bank Register 2 */
1091
#define ADC_HWCB3 __REG32(ADC_BASE + 0x30) /* High Word Control Bank Register 3 */
1092
#define ADC_HWCB4 __REG32(ADC_BASE + 0x34) /* High Word Control Bank Register 4 */
1093
#define ADC_HWCB5 __REG32(ADC_BASE + 0x38) /* High Word Control Bank Register 5 */
1094
#define ADC_HWCB6 __REG32(ADC_BASE + 0x3C) /* High Word Control Bank Register 6 */
1095
#define ADC_HWCB7 __REG32(ADC_BASE + 0x40) /* High Word Control Bank Register 7 */
1096
#define ADC_HWCB8 __REG32(ADC_BASE + 0x44) /* High Word Control Bank Register 8 */
1097
#define ADC_HWCB9 __REG32(ADC_BASE + 0x48) /* High Word Control Bank Register 9 */
1098
#define ADC_HWCB10 __REG32(ADC_BASE + 0x4C) /* High Word Control Bank Register 10 */
1099
#define ADC_HWCB11 __REG32(ADC_BASE + 0x50) /* High Word Control Bank Register 11 */
1100
#define ADC_HWCB12 __REG32(ADC_BASE + 0x54) /* High Word Control Bank Register 12 */
1101
#define ADC_HWCB13 __REG32(ADC_BASE + 0x58) /* High Word Control Bank Register 13 */
1102
#define ADC_HWCB14 __REG32(ADC_BASE + 0x5C) /* High Word Control Bank Register 14 */
1103
#define ADC_HWCB15 __REG32(ADC_BASE + 0x60) /* High Word Control Bank Register 15 */
1104
#define ADC_LWCB0 __REG32(ADC_BASE + 0x64) /* Low Word Control Bank Register 0 */
1105
#define ADC_LWCB1 __REG32(ADC_BASE + 0x68) /* Low Word Control Bank Register 1 */
1106
#define ADC_LWCB2 __REG32(ADC_BASE + 0x6C) /* Low Word Control Bank Register 2 */
1107
#define ADC_LWCB3 __REG32(ADC_BASE + 0x70) /* Low Word Control Bank Register 3 */
1108
#define ADC_LWCB4 __REG32(ADC_BASE + 0x74) /* Low Word Control Bank Register 4 */
1109
#define ADC_LWCB5 __REG32(ADC_BASE + 0x78) /* Low Word Control Bank Register 5 */
1110
#define ADC_LWCB6 __REG32(ADC_BASE + 0x7C) /* Low Word Control Bank Register 6 */
1111
#define ADC_LWCB7 __REG32(ADC_BASE + 0x80) /* Low Word Control Bank Register 7 */
1112
#define ADC_LWCB8 __REG32(ADC_BASE + 0x84) /* Low Word Control Bank Register 8 */
1113
#define ADC_LWCB9 __REG32(ADC_BASE + 0x88) /* Low Word Control Bank Register 9 */
1114
#define ADC_LWCB10 __REG32(ADC_BASE + 0x8C) /* Low Word Control Bank Register 10 */
1115
#define ADC_LWCB11 __REG32(ADC_BASE + 0x90) /* Low Word Control Bank Register 11 */
1116
#define ADC_LWCB12 __REG32(ADC_BASE + 0x94) /* Low Word Control Bank Register 12 */
1117
#define ADC_LWCB13 __REG32(ADC_BASE + 0x98) /* Low Word Control Bank Register 13 */
1118
#define ADC_LWCB14 __REG32(ADC_BASE + 0x9C) /* Low Word Control Bank Register 14 */
1119
#define ADC_LWCB15 __REG32(ADC_BASE + 0xA0) /* Low Word Control Bank Register 15 */
1120
#define ADC_IHWCTRL __REG32(ADC_BASE + 0xA4) /* Idle High Word Register */
1121
#define ADC_ILWCTRL __REG32(ADC_BASE + 0xA8) /* Idle Low Word Register */
1122
#define ADC_MIS __REG32(ADC_BASE + 0xAC) /* Masked Interrupt Status Register */
1123
#define ADC_IC __REG32(ADC_BASE + 0xB0) /* Interrupt Clear Register */
1127
/**************************************/
1128
/* Keyboard and Mouse Interface (KMI) */
1129
/**************************************/
1131
#define KMI_BASE LH7A404_KMI_BASE
1133
#define KMI_CR __REG32(KMI_BASE + 0x00) /* KMI Control Register */
1134
#define KMI_STAT __REG32(KMI_BASE + 0x04) /* KMI Status Register */
1135
#define KMI_DATA __REG32(KMI_BASE + 0x08) /* KMI Data Register */
1136
#define KMI_CLKDIV __REG32(KMI_BASE + 0x0C) /* KMI Clock Divider Register */
1137
#define KMI_ISR __REG32(KMI_BASE + 0x10) /* KMI Interrupt Status Register */
1139
/* Bits in KMI Control Register */
1140
#define KMI_CR_FCL (1 << 0) /* Force KMI Clock LOW */
1141
#define KMI_CR_FDL (1 << 1) /* Force KMI Data Line LOW */
1142
#define KMI_CR_KMIEN (1 << 2) /* KMI Enable */
1143
#define KMI_CR_TIE (1 << 3) /* Transmit Interrupt Enable */
1144
#define KMI_CR_RIE (1 << 4) /* Receive Interrupt Enable */
1145
#define KMI_CR_TYPE (1 << 5) /* Keyboard Type: 0 = PS2/AT (with line control bit) */
1147
/* Bits in KMI Status Register */
1148
#define KMI_STAT_DSTAT (1 << 0) /* Data Line Status */
1149
#define KMI_STAT_CLKSTAT (1 << 1) /* Clock Line Status */
1150
#define KMI_STAT_RXPARITY (1 << 2) /* Receive Parity */
1151
#define KMI_STAT_RXBUSY (1 << 3) /* Receive Busy */
1152
#define KMI_STAT_RXFULL (1 << 4) /* Receive Register Full */
1153
#define KMI_STAT_TXBUSY (1 << 5) /* Transmit Busy */
1154
#define KMI_STAT_TXEMPTY (1 << 6) /* Transmit Register Empty */
1156
/* Bits in KMI Data Register */
1157
#define KMI_DATA_MASK (0xFF << 0) /* KMI Data */
1159
/* Bits in KMI Clock Divider Register */
1160
#define KMI_CLKDIV_MASK (0x0F << 0) /* KMI Clock Divisor */
1162
/* Bits in KMI Interrupt Status Register */
1163
#define KMI_ISR_RXI (1 << 0) /* Receive interrupt */
1164
#define KMI_ISR_TXI (1 << 1) /* Transmit interrupt */
1167
#endif /* __LH7A404_H__ */
added
removed
src/plugins/scriptedwizard/resources/arm/files/lpd-lh7a404/h/lh7a404.h
