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Viewing changes to src/gallium/drivers/nouveau/nv30/nv30_screen.c

  • Committer: mmach
  • Date: 2022-09-22 20:02:48 UTC
  • Revision ID: netbit73@gmail.com-20220922200248-7y4wybmdgipuwdiw
2022-09-22 21:17:09

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Lines of Context:
src/gallium/drivers/nouveau/nv30/nv30_screen.c
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   case PIPE_CAP_FS_COORD_PIXEL_CENTER_INTEGER:
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   case PIPE_CAP_TGSI_TEXCOORD:
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   case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 
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   case PIPE_CAP_CLEAR_SCISSORED:
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   case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
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   case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
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   case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
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   case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
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   case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
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   case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
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   case PIPE_CAP_VERTEX_SHADER_SATURATE:
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   case PIPE_CAP_INDEP_BLEND_ENABLE:
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   case PIPE_CAP_INDEP_BLEND_FUNC:
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   case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
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   case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
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   case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
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   case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
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   case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 
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   case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT:
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   case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
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   case PIPE_CAP_VS_LAYER_VIEWPORT:
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   case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
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   case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
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   case PIPE_CAP_SHADER_CAN_READ_OUTPUTS:
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   case PIPE_CAP_NATIVE_FENCE_FD:
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   case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
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   case PIPE_CAP_FBFETCH:
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   case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 
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   case PIPE_CAP_LEGACY_MATH_RULES:
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   case PIPE_CAP_DOUBLES:
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   case PIPE_CAP_INT64:
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   case PIPE_CAP_INT64_DIVMOD:
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   case PIPE_CAP_MAX_GS_INVOCATIONS:
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      return 32;
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   case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 
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   case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
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      return 1 << 27;
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   case PIPE_CAP_VENDOR_ID:
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      return 0x10de;
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      case PIPE_SHADER_CAP_MAX_INPUTS:
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      case PIPE_SHADER_CAP_MAX_OUTPUTS:
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         return 16;
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      case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 
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      case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
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         return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
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      case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
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         return 1;
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      case PIPE_SHADER_CAP_MAX_TEMPS:
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         return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
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      case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
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         return 32;
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      case PIPE_SHADER_CAP_PREFERRED_IR:
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         return (NOUVEAU_DEBUG & NOUVEAU_DEBUG_USE_TGSI) ? PIPE_SHADER_IR_TGSI : PIPE_SHADER_IR_NIR;
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      case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
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      case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
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         return 0;
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      case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 
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      case PIPE_SHADER_CAP_CONT_SUPPORTED:
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      case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
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      case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
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      case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
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      case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
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      case PIPE_SHADER_CAP_INT16:
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      case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
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      case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
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      case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
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      case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
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      case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 
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      case PIPE_SHADER_CAP_DROUND_SUPPORTED:
 
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      case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED:
 
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      case PIPE_SHADER_CAP_LDEXP_SUPPORTED:
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      case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
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      case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
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      case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
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      case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
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      case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
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      case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
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      case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
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         return 0;
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         return 8; /* should be possible to do 10 with nv4x */
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      case PIPE_SHADER_CAP_MAX_OUTPUTS:
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         return 4;
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      case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 
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      case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
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         return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
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      case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
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         return 1;
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      case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
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      case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
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         return 16;
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      case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
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         return 32;
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      case PIPE_SHADER_CAP_PREFERRED_IR:
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         return (NOUVEAU_DEBUG & NOUVEAU_DEBUG_USE_TGSI) ? PIPE_SHADER_IR_TGSI : PIPE_SHADER_IR_NIR;
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      case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 
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      case PIPE_SHADER_CAP_CONT_SUPPORTED:
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      case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
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      case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
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      case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
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      case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
426
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      case PIPE_SHADER_CAP_INT16:
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      case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
428
 
      case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
429
 
      case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
430
 
      case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
431
 
      case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 
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      case PIPE_SHADER_CAP_DROUND_SUPPORTED:
 
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      case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED:
 
422
      case PIPE_SHADER_CAP_LDEXP_SUPPORTED:
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      case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
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      case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
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      case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
435
 
      case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
436
 
      case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
437
426
      case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
438
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      case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
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         return 0;
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   .lower_rotate = true,
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   .lower_uniforms_to_ubo = true,
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   .lower_vector_cmp = true,
 
496
   .force_indirect_unrolling = nir_var_all,
 
497
   .force_indirect_unrolling_sampler = true,
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   .max_unroll_iterations = 32,
 
499
   .no_integers = true,
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   .use_interpolated_input_intrinsics = true,
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};