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Viewing changes to src/gallium/drivers/zink/zink_draw.cpp

  • Committer: mmach
  • Date: 2022-09-22 20:02:48 UTC
  • Revision ID: netbit73@gmail.com-20220922200248-7y4wybmdgipuwdiw
2022-09-22 21:17:09

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Lines of Context:
src/gallium/drivers/zink/zink_draw.cpp
40
40
         stage |= VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT;
41
41
      }
42
42
      zink_resource_buffer_barrier(ctx, res, access, stage);
 
43
      res->obj->unordered_read = false;
43
44
   }
44
45
}
45
46
 
85
86
{
86
87
   struct zink_resource *res = zink_resource(pres);
87
88
   zink_resource_buffer_barrier(ctx, res, flags, pipeline);
 
89
   res->obj->unordered_read = false;
88
90
}
89
91
 
90
92
ALWAYS_INLINE static void
200
202
         ctx->dirty_shader_stages |= prog->stages_present;
201
203
      } else {
202
204
         ctx->dirty_shader_stages |= bits;
203
 
         prog = zink_create_gfx_program(ctx, ctx->gfx_stages, ctx->gfx_pipeline_state.vertices_per_patch + 1);
 
205
         prog = zink_create_gfx_program(ctx, ctx->gfx_stages, ctx->gfx_pipeline_state.dyn_state2.vertices_per_patch);
204
206
         _mesa_hash_table_insert_pre_hashed(ht, hash, prog->shaders, prog);
205
207
      }
206
208
      zink_update_gfx_program(ctx, prog);
323
325
   }
324
326
}
325
327
 
326
 
/*
327
 
   If a synchronization command includes a source stage mask, its first synchronization scope only
328
 
   includes execution of the pipeline stages specified in that mask, and its first access scope only
329
 
   includes memory accesses performed by pipeline stages specified in that mask.
330
 
 
331
 
   If a synchronization command includes a destination stage mask, its second synchronization scope
332
 
   only includes execution of the pipeline stages specified in that mask, and its second access scope
333
 
   only includes memory access performed by pipeline stages specified in that mask.
334
 
 
335
 
   - Chapter 7. Synchronization and Cache Control
336
 
 
337
 
 * thus, all stages must be added to ensure accurate synchronization
338
 
 */
339
 
ALWAYS_INLINE static VkPipelineStageFlags
340
 
find_pipeline_bits(uint32_t *mask)
341
 
{
342
 
   VkPipelineStageFlags pipeline = 0;
343
 
   for (unsigned i = 0; i < ZINK_SHADER_COUNT; i++) {
344
 
      if (mask[i]) {
345
 
         pipeline |= zink_pipeline_flags_from_pipe_stage((enum pipe_shader_type)i);
346
 
      }
347
 
   }
348
 
   return pipeline;
349
 
}
350
 
 
351
328
static void
352
329
update_barriers(struct zink_context *ctx, bool is_compute,
353
330
                struct pipe_resource *index, struct pipe_resource *indirect, struct pipe_resource *indirect_draw_count)
359
336
   ctx->need_barriers[is_compute] = &ctx->update_barriers[is_compute][ctx->barrier_set_idx[is_compute]];
360
337
   set_foreach(need_barriers, he) {
361
338
      struct zink_resource *res = (struct zink_resource *)he->key;
362
 
      bool is_buffer = res->obj->is_buffer;
363
 
      VkPipelineStageFlags pipeline = 0;
364
 
      VkAccessFlags access = 0;
365
 
 
366
 
      if (res == zink_resource(index)) {
367
 
         access |= VK_ACCESS_INDEX_READ_BIT;
368
 
         pipeline |= VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
369
 
      } else if (res == zink_resource(indirect) || res == zink_resource(indirect_draw_count)) {
370
 
         access |= VK_ACCESS_INDIRECT_COMMAND_READ_BIT;
371
 
         pipeline |= VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT;
372
 
      }
373
339
      if (res->bind_count[is_compute]) {
374
 
         if (res->write_bind_count[is_compute])
375
 
            access |= VK_ACCESS_SHADER_WRITE_BIT;
376
 
         if (is_buffer) {
377
 
            unsigned bind_count = res->bind_count[is_compute];
378
 
            if (res->ubo_bind_count[is_compute])
379
 
               access |= VK_ACCESS_UNIFORM_READ_BIT;
380
 
            bind_count -= res->ubo_bind_count[is_compute];
381
 
            if (!is_compute && res->vbo_bind_mask) {
382
 
               access |= VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT;
383
 
               pipeline |= VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
384
 
               bind_count -= res->vbo_bind_count;
385
 
            }
386
 
            if (bind_count)
387
 
               access |= VK_ACCESS_SHADER_READ_BIT;
388
 
            if (!is_compute) {
389
 
               pipeline |= find_pipeline_bits(res->ssbo_bind_mask);
390
 
 
391
 
               if (res->ubo_bind_count[0] && (pipeline & GFX_SHADER_BITS) != GFX_SHADER_BITS)
392
 
                  pipeline |= find_pipeline_bits(res->ubo_bind_mask);
393
 
            }
394
 
         } else {
395
 
            if (res->bind_count[is_compute] != res->write_bind_count[is_compute])
396
 
               access |= VK_ACCESS_SHADER_READ_BIT;
397
 
            if (res->write_bind_count[is_compute])
398
 
               access |= VK_ACCESS_SHADER_WRITE_BIT;
399
 
         }
400
 
         if (is_compute)
401
 
            pipeline = VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT;
402
 
         else {
403
 
            VkPipelineStageFlags gfx_stages = pipeline & ~(VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT);
404
 
            /* images always need gfx stages, and buffers need gfx stages if non-vbo binds exist */
405
 
            bool needs_stages = !is_buffer || (res->bind_count[0] - res->vbo_bind_count > 0);
406
 
            if (gfx_stages != GFX_SHADER_BITS && needs_stages) {
407
 
               gfx_stages |= find_pipeline_bits(res->sampler_binds);
408
 
               if (gfx_stages != GFX_SHADER_BITS) //must be a shader image
409
 
                  gfx_stages |= find_pipeline_bits(res->image_binds);
410
 
               pipeline |= gfx_stages;
411
 
            }
412
 
         }
 
340
         VkPipelineStageFlagBits pipeline = is_compute ? VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT : res->gfx_barrier;
413
341
         if (res->base.b.target == PIPE_BUFFER)
414
 
            zink_resource_buffer_barrier(ctx, res, access, pipeline);
 
342
            zink_resource_buffer_barrier(ctx, res, res->barrier_access[is_compute], pipeline);
415
343
         else {
416
344
            VkImageLayout layout = zink_descriptor_util_image_layout_eval(ctx, res, is_compute);
417
345
            if (layout != res->layout)
418
 
               zink_resource_image_barrier(ctx, res, layout, access, pipeline);
 
346
               zink_resource_image_barrier(ctx, res, layout, res->barrier_access[is_compute], pipeline);
419
347
         }
 
348
         if (zink_resource_access_is_write(res->barrier_access[is_compute]))
 
349
            res->obj->unordered_read = res->obj->unordered_write = false;
 
350
         else
 
351
            res->obj->unordered_read = false;
420
352
         /* always barrier on draw if this resource has either multiple image write binds or
421
353
          * image write binds and image read binds
422
354
          */
514
446
      zink_rebind_all_buffers(ctx);
515
447
   }
516
448
 
 
449
   if (unlikely(ctx->image_rebind_counter < screen->image_rebind_counter)) {
 
450
      ctx->image_rebind_counter = screen->image_rebind_counter;
 
451
      zink_rebind_all_images(ctx);
 
452
   }
 
453
 
517
454
   unsigned index_offset = 0;
518
455
   unsigned index_size = dinfo->index_size;
519
456
   struct pipe_resource *index_buffer = NULL;
546
483
          */
547
484
         for (unsigned i = 0; i < ctx->num_so_targets; i++) {
548
485
            struct zink_so_target *t = (struct zink_so_target *)ctx->so_targets[i];
549
 
            if (t)
550
 
               zink_resource_buffer_barrier(ctx, zink_resource(t->base.buffer),
 
486
            if (t) {
 
487
               struct zink_resource *res = zink_resource(t->base.buffer);
 
488
               zink_resource_buffer_barrier(ctx, res,
551
489
                                            VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT, VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT);
 
490
               res->obj->unordered_read = res->obj->unordered_write = false;
 
491
            }
552
492
         }
553
493
      }
554
494
   }
560
500
   /* ensure synchronization between doing streamout with counter buffer
561
501
    * and using counter buffer for indirect draw
562
502
    */
563
 
   if (so_target && so_target->counter_buffer_valid)
564
 
      zink_resource_buffer_barrier(ctx, zink_resource(so_target->counter_buffer),
 
503
   if (so_target && so_target->counter_buffer_valid) {
 
504
      struct zink_resource *res = zink_resource(so_target->counter_buffer);
 
505
      zink_resource_buffer_barrier(ctx, res,
565
506
                                   VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT,
566
507
                                   VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT);
 
508
      res->obj->unordered_read = false;
 
509
   }
567
510
 
568
511
   zink_query_update_gs_states(ctx, dinfo->was_line_loop);
569
512
 
 
513
   if (unlikely(zink_debug & ZINK_DEBUG_SYNC)) {
 
514
      zink_batch_no_rp(ctx);
 
515
      VkMemoryBarrier mb;
 
516
      mb.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER;
 
517
      mb.pNext = NULL;
 
518
      mb.srcAccessMask = VK_ACCESS_MEMORY_WRITE_BIT;
 
519
      mb.dstAccessMask = VK_ACCESS_MEMORY_READ_BIT;
 
520
      VKSCR(CmdPipelineBarrier)(ctx->batch.state->cmdbuf,
 
521
                                VK_PIPELINE_STAGE_ALL_COMMANDS_BIT,
 
522
                                VK_PIPELINE_STAGE_ALL_COMMANDS_BIT,
 
523
                                0, 1, &mb, 0, NULL, 0, NULL);
 
524
   }
 
525
 
570
526
   zink_batch_rp(ctx);
571
527
   /* check dead swapchain */
572
528
   if (unlikely(!ctx->batch.in_rp))
615
571
   if (have_streamout && ctx->dirty_so_targets)
616
572
      zink_emit_stream_output_targets(pctx);
617
573
 
618
 
   bool pipeline_changed = false;
619
 
   if (DYNAMIC_STATE == ZINK_NO_DYNAMIC_STATE)
620
 
      pipeline_changed = update_gfx_pipeline<BATCH_CHANGED>(ctx, batch->state, mode);
 
574
   bool pipeline_changed = update_gfx_pipeline<BATCH_CHANGED>(ctx, batch->state, mode);
621
575
 
622
576
   if (BATCH_CHANGED || ctx->vp_state_changed || (DYNAMIC_STATE == ZINK_NO_DYNAMIC_STATE && pipeline_changed)) {
623
577
      VkViewport viewports[PIPE_MAX_VIEWPORTS];
627
581
            ctx->vp_state.viewport_states[i].translate[1] - ctx->vp_state.viewport_states[i].scale[1],
628
582
            MAX2(ctx->vp_state.viewport_states[i].scale[0] * 2, 1),
629
583
            ctx->vp_state.viewport_states[i].scale[1] * 2,
630
 
            ctx->rast_state->base.clip_halfz ?
631
 
               ctx->vp_state.viewport_states[i].translate[2] :
632
 
               ctx->vp_state.viewport_states[i].translate[2] - ctx->vp_state.viewport_states[i].scale[2],
633
 
            ctx->vp_state.viewport_states[i].translate[2] + ctx->vp_state.viewport_states[i].scale[2]
 
584
            CLAMP(ctx->rast_state->base.clip_halfz ?
 
585
                  ctx->vp_state.viewport_states[i].translate[2] :
 
586
                  ctx->vp_state.viewport_states[i].translate[2] - ctx->vp_state.viewport_states[i].scale[2],
 
587
                  0, 1),
 
588
            CLAMP(ctx->vp_state.viewport_states[i].translate[2] + ctx->vp_state.viewport_states[i].scale[2],
 
589
                  0, 1)
634
590
         };
 
591
         if (!ctx->rast_state->base.half_pixel_center) {
 
592
             /* magic constant value from dxvk */
 
593
             float cf = 0.5f - (1.0f / 128.0f);
 
594
             viewport.x += cf;
 
595
             if (viewport.height < 0)
 
596
                viewport.y += cf;
 
597
             else
 
598
                viewport.y -= cf;
 
599
         }
635
600
         viewports[i] = viewport;
636
601
      }
637
602
      if (DYNAMIC_STATE != ZINK_NO_DYNAMIC_STATE)
711
676
   ctx->dsa_state_changed = false;
712
677
 
713
678
   bool rast_state_changed = ctx->rast_state_changed;
714
 
   if (DYNAMIC_STATE != ZINK_NO_DYNAMIC_STATE && (BATCH_CHANGED || rast_state_changed))
715
 
      VKCTX(CmdSetFrontFaceEXT)(batch->state->cmdbuf, ctx->gfx_pipeline_state.dyn_state1.front_face);
 
679
   if (DYNAMIC_STATE != ZINK_NO_DYNAMIC_STATE && (BATCH_CHANGED || rast_state_changed)) {
 
680
      VKCTX(CmdSetFrontFaceEXT)(batch->state->cmdbuf, (VkFrontFace)ctx->gfx_pipeline_state.dyn_state1.front_face);
 
681
      VKCTX(CmdSetCullModeEXT)(batch->state->cmdbuf, ctx->gfx_pipeline_state.dyn_state1.cull_mode);
 
682
   }
716
683
   if ((BATCH_CHANGED || rast_state_changed) &&
717
684
       screen->info.have_EXT_line_rasterization && rast_state->base.line_stipple_enable)
718
685
      VKCTX(CmdSetLineStippleEXT)(batch->state->cmdbuf, rast_state->base.line_stipple_factor, rast_state->base.line_stipple_pattern);
719
686
 
720
 
   if (BATCH_CHANGED || ctx->rast_state_changed || mode_changed) {
 
687
   if (BATCH_CHANGED || ctx->rast_state_changed) {
721
688
      enum pipe_prim_type reduced_prim = ctx->last_vertex_stage->reduced_prim;
722
689
      if (reduced_prim == PIPE_PRIM_MAX)
723
690
         reduced_prim = u_reduced_prim(mode);
741
708
      }
742
709
 
743
710
      VKCTX(CmdSetLineWidth)(batch->state->cmdbuf, rast_state->line_width);
744
 
      if (depth_bias)
745
 
         VKCTX(CmdSetDepthBias)(batch->state->cmdbuf, rast_state->offset_units, rast_state->offset_clamp, rast_state->offset_scale);
746
 
      else
 
711
      if (depth_bias) {
 
712
         if (rast_state->base.offset_units_unscaled) {
 
713
            VKCTX(CmdSetDepthBias)(batch->state->cmdbuf, rast_state->offset_units * ctx->depth_bias_scale_factor, rast_state->offset_clamp, rast_state->offset_scale);
 
714
         } else {
 
715
            VKCTX(CmdSetDepthBias)(batch->state->cmdbuf, rast_state->offset_units, rast_state->offset_clamp, rast_state->offset_scale);
 
716
         }
 
717
      } else {
747
718
         VKCTX(CmdSetDepthBias)(batch->state->cmdbuf, 0.0f, 0.0f, 0.0f);
 
719
      }
748
720
   }
749
721
   ctx->rast_state_changed = false;
750
722
 
765
737
 
766
738
   if (DRAW_STATE)
767
739
      zink_bind_vertex_state(batch, ctx, vstate, partial_velem_mask);
768
 
   else if (BATCH_CHANGED || ctx->vertex_buffers_dirty)
769
 
      zink_bind_vertex_buffers<DYNAMIC_STATE>(batch, ctx);
 
740
   else if (BATCH_CHANGED || ctx->vertex_buffers_dirty) {
 
741
      if (DYNAMIC_STATE == ZINK_DYNAMIC_VERTEX_INPUT || ctx->gfx_pipeline_state.uses_dynamic_stride)
 
742
         zink_bind_vertex_buffers<DYNAMIC_STATE>(batch, ctx);
 
743
      else
 
744
         zink_bind_vertex_buffers<ZINK_NO_DYNAMIC_STATE>(batch, ctx);
 
745
   }
770
746
 
771
747
   if (BATCH_CHANGED) {
772
748
      ctx->pipeline_changed[0] = false;
773
749
      zink_select_draw_vbo(ctx);
774
750
   }
775
751
 
776
 
   if (DYNAMIC_STATE != ZINK_NO_DYNAMIC_STATE) {
777
 
      update_gfx_pipeline<BATCH_CHANGED>(ctx, batch->state, mode);
778
 
      if (BATCH_CHANGED || mode_changed)
779
 
         VKCTX(CmdSetPrimitiveTopologyEXT)(batch->state->cmdbuf, zink_primitive_topology(mode));
 
752
   if (DYNAMIC_STATE != ZINK_NO_DYNAMIC_STATE && (BATCH_CHANGED || mode_changed)) {
 
753
      VKCTX(CmdSetPrimitiveTopologyEXT)(batch->state->cmdbuf, zink_primitive_topology(mode));
780
754
   }
781
755
 
782
756
   if (DYNAMIC_STATE >= ZINK_DYNAMIC_STATE2 && (BATCH_CHANGED || ctx->primitive_restart != dinfo->primitive_restart)) {
792
766
   if (zink_program_has_descriptors(&ctx->curr_program->base))
793
767
      screen->descriptors_update(ctx, false);
794
768
 
795
 
   if (ctx->di.any_bindless_dirty && ctx->curr_program->base.dd->bindless)
 
769
   if (ctx->di.any_bindless_dirty &&
 
770
       /* some apps (d3dretrace) call MakeTextureHandleResidentARB randomly */
 
771
       zink_program_has_descriptors(&ctx->curr_program->base) &&
 
772
       ctx->curr_program->base.dd->bindless)
796
773
      zink_descriptors_update_bindless(ctx);
797
774
 
798
775
   if (reads_basevertex) {
815
792
            struct zink_resource *res = zink_resource(t->counter_buffer);
816
793
            t->stride = ctx->last_vertex_stage->sinfo.so_info.stride[i] * sizeof(uint32_t);
817
794
            zink_batch_reference_resource_rw(batch, res, true);
 
795
            res->obj->unordered_read = res->obj->unordered_write = false;
818
796
            if (t->counter_buffer_valid) {
819
797
               counter_buffers[i] = res->obj->buffer;
820
798
               counter_buffer_offsets[i] = t->counter_buffer_offset;
931
909
   struct zink_resource *res = zink_resource(vstate->input.vbuffer.buffer.resource);
932
910
   zink_resource_buffer_barrier(ctx, res, VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT,
933
911
                                VK_PIPELINE_STAGE_VERTEX_INPUT_BIT);
 
912
   res->obj->unordered_read = false;
934
913
   struct zink_vertex_elements_hw_state *hw_state = ctx->gfx_pipeline_state.element_state;
935
914
   ctx->gfx_pipeline_state.element_state = &((struct zink_vertex_state*)vstate)->velems.hw_state;
936
915
 
967
946
   if (ctx->memory_barrier)
968
947
      zink_flush_memory_barrier(ctx, true);
969
948
 
 
949
   if (unlikely(zink_debug & ZINK_DEBUG_SYNC)) {
 
950
      zink_batch_no_rp(ctx);
 
951
      VkMemoryBarrier mb;
 
952
      mb.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER;
 
953
      mb.pNext = NULL;
 
954
      mb.srcAccessMask = VK_ACCESS_MEMORY_WRITE_BIT;
 
955
      mb.dstAccessMask = VK_ACCESS_MEMORY_READ_BIT;
 
956
      VKSCR(CmdPipelineBarrier)(ctx->batch.state->cmdbuf,
 
957
                                VK_PIPELINE_STAGE_ALL_COMMANDS_BIT,
 
958
                                VK_PIPELINE_STAGE_ALL_COMMANDS_BIT,
 
959
                                0, 1, &mb, 0, NULL, 0, NULL);
 
960
   }
 
961
 
970
962
   if (zink_program_has_descriptors(&ctx->curr_compute->base))
971
963
      screen->descriptors_update(ctx, true);
972
964
   if (ctx->di.any_bindless_dirty && ctx->curr_compute->base.dd->bindless)