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Viewing changes to src/gallium/drivers/panfrost/pan_screen.c

  • Committer: mmach
  • Date: 2022-09-22 20:02:48 UTC
  • Revision ID: netbit73@gmail.com-20220922200248-7y4wybmdgipuwdiw
2022-09-22 21:17:09

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Lines of Context:
src/gallium/drivers/panfrost/pan_screen.c
69
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        {"linear",    PAN_DBG_LINEAR,   "Force linear textures"},
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        {"nocache",   PAN_DBG_NO_CACHE, "Disable BO cache"},
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        {"dump",      PAN_DBG_DUMP,     "Dump all graphics memory"},
 
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#ifdef PAN_DBG_OVERFLOW
 
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        {"overflow",  PAN_DBG_OVERFLOW, "Check for buffer overflows in pool uploads"},
 
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#endif
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        DEBUG_NAMED_VALUE_END
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};
74
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105
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        bool has_heap = dev->kernel_version->version_major > 1 ||
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                        dev->kernel_version->version_minor >= 1;
107
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108
 
        /* Bifrost is WIP */
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        switch (param) {
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        case PIPE_CAP_NPOT_TEXTURES:
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        case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
112
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        case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
113
 
        case PIPE_CAP_VERTEX_SHADER_SATURATE:
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        case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
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        case PIPE_CAP_POINT_SPRITE:
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        case PIPE_CAP_DEPTH_CLIP_DISABLE:
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        case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
123
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        case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
124
125
        case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 
126
        case PIPE_CAP_SHADER_PACK_HALF_FLOAT:
125
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                return 1;
126
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        case PIPE_CAP_MAX_RENDER_TARGETS:
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        case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
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                return is_gl3 ? 330 : 140;
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        case PIPE_CAP_ESSL_FEATURE_LEVEL:
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                return pan_is_bifrost(dev) ? 320 : 310;
 
201
                return dev->arch >= 6 ? 320 : 310;
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        case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
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                return 16;
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204
 
        case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 
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        case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT:
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                return 65536;
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        /* Must be at least 64 for correct behaviour */
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        case PIPE_CAP_SUPPORTED_PRIM_MODES:
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        case PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART: {
321
 
                /* Mali supports GLES and QUADS. Midgard supports more */
 
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                /* Mali supports GLES and QUADS. Midgard and v6 Bifrost
 
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                 * support more */
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                uint32_t modes = BITFIELD_MASK(PIPE_PRIM_QUADS + 1);
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324
 
                if (dev->arch <= 5) {
 
327
                if (dev->arch <= 6) {
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                        modes |= BITFIELD_BIT(PIPE_PRIM_QUAD_STRIP);
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                        modes |= BITFIELD_BIT(PIPE_PRIM_POLYGON);
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                }
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                if (dev->arch >= 9) {
 
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                        /* Although Valhall is supposed to support quads, they
 
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                         * don't seem to work correctly. Disable to fix
 
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                         * arb-provoking-vertex-render.
 
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                         */
 
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                        modes &= ~BITFIELD_BIT(PIPE_PRIM_QUADS);
 
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                }
 
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                return modes;
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        }
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                return 0;
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        }
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        /* We only allow observable side effects (memory writes) in compute and
 
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         * fragment shaders. Side effects in the geometry pipeline cause
 
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         * trouble with IDVS.
 
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         *
 
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         * This restriction doesn't apply to Midgard, which does not implement
 
374
         * IDVS and therefore executes vertex shaders exactly once.
 
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         */
 
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        bool allow_side_effects = (shader != PIPE_SHADER_VERTEX) ||
 
377
                                  (dev->arch <= 5);
 
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        switch (param) {
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        case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
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        case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
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        case PIPE_SHADER_CAP_MAX_TEMPS:
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                return 256; /* arbitrary */
377
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378
 
        case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 
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        case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
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                return 16 * 1024 * sizeof(float);
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        case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
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                STATIC_ASSERT(PAN_MAX_CONST_BUFFERS < 0x100);
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                return PAN_MAX_CONST_BUFFERS;
384
405
 
385
 
        case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 
406
        case PIPE_SHADER_CAP_CONT_SUPPORTED:
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                return 0;
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408
 
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        case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
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                return 0;
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        case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
394
 
                return pan_is_bifrost(dev);
 
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                return dev->arch >= 6;
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        case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
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                return 1;
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                return !is_nofp16;
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        case PIPE_SHADER_CAP_FP16_DERIVATIVES:
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        case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
417
 
                return pan_is_bifrost(dev) && !is_nofp16;
 
438
                return dev->arch >= 6 && !is_nofp16;
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        case PIPE_SHADER_CAP_INT16:
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                /* XXX: Advertise this CAP when a proper fix to lower_precision
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                 * lands. GLSL IR validation failure in glmark2 -bterrain */
421
 
                return pan_is_bifrost(dev) && !is_nofp16 && is_deqp;
 
442
                return dev->arch >= 6 && !is_nofp16 && is_deqp;
422
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        case PIPE_SHADER_CAP_INT64_ATOMICS:
424
 
        case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
425
 
        case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
426
 
        case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
427
 
        case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 
445
        case PIPE_SHADER_CAP_DROUND_SUPPORTED:
 
446
        case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED:
 
447
        case PIPE_SHADER_CAP_LDEXP_SUPPORTED:
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        case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
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                return 0;
430
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443
463
                return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_NIR_SERIALIZED);
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        case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
446
 
                return 16;
 
466
                return allow_side_effects ? 16 : 0;
447
467
 
448
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        case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
449
 
                return PIPE_MAX_SHADER_IMAGES;
 
469
                return allow_side_effects ? PIPE_MAX_SHADER_IMAGES : 0;
450
470
 
451
 
        case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
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        case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
453
472
        case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
454
 
        case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
455
 
        case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
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                return 0;
457
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458
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        default:
527
544
 
528
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        format_desc = util_format_description(format);
529
546
 
530
 
        if (!format_desc)
531
 
                return false;
532
 
 
533
547
        /* MSAA 2x gets rounded up to 4x. MSAA 8x/16x only supported on v5+.
534
548
         * TODO: debug MSAA 8x/16x */
535
549
 
590
604
        struct panfrost_device *dev = pan_device(screen);
591
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        bool afbc = dev->has_afbc && panfrost_format_supports_afbc(dev, format);
592
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        bool ytr = panfrost_afbc_can_ytr(format);
 
607
        bool tiled_afbc = panfrost_afbc_can_tile(dev);
593
608
 
594
609
        unsigned count = 0;
595
610
 
600
615
                if ((pan_best_modifiers[i] & AFBC_FORMAT_MOD_YTR) && !ytr)
601
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                        continue;
602
617
 
 
618
                if ((pan_best_modifiers[i] & AFBC_FORMAT_MOD_TILED) && !tiled_afbc)
 
619
                        continue;
 
620
 
603
621
                if (test_modifier != DRM_FORMAT_MOD_INVALID &&
604
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                    test_modifier != pan_best_modifiers[i])
605
623
                        continue;
698
716
                RET((uint32_t []) { 800 /* MHz -- TODO */ });
699
717
 
700
718
        case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
701
 
                RET((uint32_t []) { 9999 });  // TODO
 
719
                RET((uint32_t []) { dev->core_count });
702
720
 
703
721
        case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
704
722
                RET((uint32_t []) { 1 });
705
723
 
706
724
        case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
707
 
                RET((uint32_t []) { dev->arch >= 7 ? 8 : 4 });
 
725
                RET((uint32_t []) { pan_subgroup_size(dev->arch) });
708
726
 
709
727
        case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
710
728
                RET((uint64_t []) { 1024 }); // TODO
855
873
        if (dev->debug & PAN_DBG_NO_AFBC)
856
874
                dev->has_afbc = false;
857
875
 
858
 
        /* It's early days for Valhall support... disable AFBC for now to keep
859
 
         * hardware bring-up simple
860
 
         */
861
 
        if (dev->arch >= 9)
862
 
                dev->has_afbc = false;
863
 
 
864
876
        /* Bail early on unsupported hardware */
865
877
        if (dev->model == NULL) {
866
878
                debug_printf("panfrost: Unsupported model %X", dev->gpu_id);
907
919
                panfrost_cmdstream_screen_init_v6(screen);
908
920
        else if (dev->arch == 7)
909
921
                panfrost_cmdstream_screen_init_v7(screen);
 
922
        else if (dev->arch == 9)
 
923
                panfrost_cmdstream_screen_init_v9(screen);
910
924
        else
911
925
                unreachable("Unhandled architecture major");
912
926