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Viewing changes to hal/phydm/phydm_hwconfig.h

  • Committer: Vitaliy Kulikov
  • Date: 2017-09-24 10:25:11 UTC
  • Revision ID: slonua@gmail.com-20170924102511-9q45rcjnowest8ee
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hal/phydm/phydm_hwconfig.h
 
1
/******************************************************************************
 
2
 *
 
3
 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
 
4
 *
 
5
 * This program is free software; you can redistribute it and/or modify it
 
6
 * under the terms of version 2 of the GNU General Public License as
 
7
 * published by the Free Software Foundation.
 
8
 *
 
9
 * This program is distributed in the hope that it will be useful, but WITHOUT
 
10
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 
11
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 
12
 * more details.
 
13
 *
 
14
 * You should have received a copy of the GNU General Public License along with
 
15
 * this program; if not, write to the Free Software Foundation, Inc.,
 
16
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 
17
 *
 
18
 *
 
19
 ******************************************************************************/
 
20
 
 
21
 
 
22
#ifndef __HALHWOUTSRC_H__
 
23
#define __HALHWOUTSRC_H__
 
24
 
 
25
 
 
26
/*--------------------------Define -------------------------------------------*/
 
27
#define CCK_RSSI_INIT_COUNT 5
 
28
 
 
29
#define RA_RSSI_STATE_INIT      0
 
30
#define RA_RSSI_STATE_SEND      1
 
31
#define RA_RSSI_STATE_HOLD      2
 
32
 
 
33
#define CFO_HW_RPT_2_MHZ(val) ((val<<1) + (val>>1))
 
34
/* ((X* 3125)  / 10)>>7 = (X*10)>>2 = X*2.5 = X<<1 + X>>1  */
 
35
 
 
36
#define AGC_DIFF_CONFIG_MP(ic, band) (odm_read_and_config_mp_##ic##_agc_tab_diff(p_dm_odm, array_mp_##ic##_agc_tab_diff_##band, \
 
37
                      sizeof(array_mp_##ic##_agc_tab_diff_##band)/sizeof(u32)))
 
38
#define AGC_DIFF_CONFIG_TC(ic, band) (odm_read_and_config_tc_##ic##_agc_tab_diff(p_dm_odm, array_tc_##ic##_agc_tab_diff_##band, \
 
39
                      sizeof(array_tc_##ic##_agc_tab_diff_##band)/sizeof(u32)))
 
40
 
 
41
#define AGC_DIFF_CONFIG(ic, band) do {\
 
42
                if (p_dm_odm->is_mp_chip)\
 
43
                        AGC_DIFF_CONFIG_MP(ic, band);\
 
44
                else\
 
45
                        AGC_DIFF_CONFIG_TC(ic, band);\
 
46
        } while (0)
 
47
 
 
48
 
 
49
/* ************************************************************
 
50
 * structure and define
 
51
 * ************************************************************ */
 
52
 
 
53
__PACK struct _phy_rx_agc_info {
 
54
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
55
        u8      gain: 7, trsw: 1;
 
56
#else
 
57
        u8      trsw: 1, gain: 7;
 
58
#endif
 
59
};
 
60
 
 
61
__PACK struct _phy_status_rpt_8192cd {
 
62
        struct _phy_rx_agc_info path_agc[2];
 
63
        u8      ch_corr[2];
 
64
        u8      cck_sig_qual_ofdm_pwdb_all;
 
65
        u8      cck_agc_rpt_ofdm_cfosho_a;
 
66
        u8      cck_rpt_b_ofdm_cfosho_b;
 
67
        u8      rsvd_1;/*ch_corr_msb;*/
 
68
        u8      noise_power_db_msb;
 
69
        s8      path_cfotail[2];
 
70
        u8      pcts_mask[2];
 
71
        s8      stream_rxevm[2];
 
72
        u8      path_rxsnr[2];
 
73
        u8      noise_power_db_lsb;
 
74
        u8      rsvd_2[3];
 
75
        u8      stream_csi[2];
 
76
        u8      stream_target_csi[2];
 
77
        s8      sig_evm;
 
78
        u8      rsvd_3;
 
79
 
 
80
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
81
        u8      antsel_rx_keep_2: 1;    /*ex_intf_flg:1;*/
 
82
        u8      sgi_en: 1;
 
83
        u8      rxsc: 2;
 
84
        u8      idle_long: 1;
 
85
        u8      r_ant_train_en: 1;
 
86
        u8      ant_sel_b: 1;
 
87
        u8      ant_sel: 1;
 
88
#else   /*_BIG_ENDIAN_  */
 
89
        u8      ant_sel: 1;
 
90
        u8      ant_sel_b: 1;
 
91
        u8      r_ant_train_en: 1;
 
92
        u8      idle_long: 1;
 
93
        u8      rxsc: 2;
 
94
        u8      sgi_en: 1;
 
95
        u8      antsel_rx_keep_2: 1;/*ex_intf_flg:1;*/
 
96
#endif
 
97
};
 
98
 
 
99
 
 
100
struct _phy_status_rpt_8812 {
 
101
        /*      DWORD 0*/
 
102
        u8                      gain_trsw[2];                                                   /*path-A and path-B {TRSW, gain[6:0] }*/
 
103
        u8                      chl_num_LSB;                                                    /*channel number[7:0]*/
 
104
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
105
        u8                      chl_num_MSB: 2;                                                 /*channel number[9:8]*/
 
106
        u8                      sub_chnl: 4;                                                            /*sub-channel location[3:0]*/
 
107
        u8                      r_RFMOD: 2;                                                             /*RF mode[1:0]*/
 
108
#else   /*_BIG_ENDIAN_  */
 
109
        u8                      r_RFMOD: 2;
 
110
        u8                      sub_chnl: 4;
 
111
        u8                      chl_num_MSB: 2;
 
112
#endif
 
113
 
 
114
        /*      DWORD 1*/
 
115
        u8                      pwdb_all;                                                               /*CCK signal quality / OFDM pwdb all*/
 
116
        s8                      cfosho[2];              /*DW1 byte 1 DW1 byte2  CCK AGC report and CCK_BB_Power / OFDM path-A and path-B short CFO*/
 
117
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
118
        /*this should be checked again because the definition of 8812 and 8814 is different*/
 
119
        /*      u8                      r_cck_rx_enable_pathc:2;                                        cck rx enable pathc[1:0]*/
 
120
        /*      u8                      cck_rx_path:4;                                                  cck rx path[3:0]*/
 
121
        u8                      resvd_0: 6;
 
122
        u8                      bt_RF_ch_MSB: 2;                                                /*8812A:2'b0                    8814A: bt rf channel keep[7:6]*/
 
123
#else   /*_BIG_ENDIAN_*/
 
124
        u8                      bt_RF_ch_MSB: 2;
 
125
        u8                      resvd_0: 6;
 
126
#endif
 
127
 
 
128
        /*      DWORD 2*/
 
129
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
130
        u8                      ant_div_sw_a: 1;                                                        /*8812A: ant_div_sw_a    8814A: 1'b0*/
 
131
        u8                      ant_div_sw_b: 1;                                                        /*8812A: ant_div_sw_b    8814A: 1'b0*/
 
132
        u8                      bt_RF_ch_LSB: 6;                                                /*8812A: 6'b0                   8814A: bt rf channel keep[5:0]*/
 
133
#else   /*_BIG_ENDIAN_  */
 
134
        u8                      bt_RF_ch_LSB: 6;
 
135
        u8                      ant_div_sw_b: 1;
 
136
        u8                      ant_div_sw_a: 1;
 
137
#endif
 
138
        s8                      cfotail[2];                /*DW2 byte 1 DW2 byte 2      path-A and path-B CFO tail*/
 
139
        u8                      PCTS_MSK_RPT_0;                                         /*PCTS mask report[7:0]*/
 
140
        u8                      PCTS_MSK_RPT_1;                                         /*PCTS mask report[15:8]*/
 
141
 
 
142
        /*      DWORD 3*/
 
143
        s8                      rxevm[2];                /*DW3 byte 1 DW3 byte 2        stream 1 and stream 2 RX EVM*/
 
144
        s8                      rxsnr[2];                /*DW3 byte 3 DW4 byte 0        path-A and path-B RX SNR*/
 
145
 
 
146
        /*      DWORD 4*/
 
147
        u8                      PCTS_MSK_RPT_2;                                         /*PCTS mask report[23:16]*/
 
148
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
149
        u8                      PCTS_MSK_RPT_3: 6;                                              /*PCTS mask report[29:24]*/
 
150
        u8                      pcts_rpt_valid: 1;                                                      /*pcts_rpt_valid*/
 
151
        u8                      resvd_1: 1;                                                             /*1'b0*/
 
152
#else   /*_BIG_ENDIAN_*/
 
153
        u8                      resvd_1: 1;
 
154
        u8                      pcts_rpt_valid: 1;
 
155
        u8                      PCTS_MSK_RPT_3: 6;
 
156
#endif
 
157
        s8                      rxevm_cd[2];       /*DW 4 byte 3 DW5 byte 0  8812A: 16'b0       8814A: stream 3 and stream 4 RX EVM*/
 
158
 
 
159
        /*      DWORD 5*/
 
160
        u8                      csi_current[2];    /*DW5 byte 1 DW5 byte 2      8812A: stream 1 and 2 CSI       8814A:  path-C and path-D RX SNR*/
 
161
        u8                      gain_trsw_cd[2];           /*DW5 byte 3 DW6 byte 0      path-C and path-D {TRSW, gain[6:0] }*/
 
162
 
 
163
        /*      DWORD 6*/
 
164
        s8                      sigevm;                                                                 /*signal field EVM*/
 
165
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
166
        u8                      antidx_antc: 3;                                                 /*8812A: 3'b0           8814A: antidx_antc[2:0]*/
 
167
        u8                      antidx_antd: 3;                                                 /*8812A: 3'b0           8814A: antidx_antd[2:0]*/
 
168
        u8                      dpdt_ctrl_keep: 1;                                              /*8812A: 1'b0           8814A: dpdt_ctrl_keep*/
 
169
        u8                      GNT_BT_keep: 1;                                                 /*8812A: 1'b0           8814A: GNT_BT_keep*/
 
170
#else   /*_BIG_ENDIAN_*/
 
171
        u8                      GNT_BT_keep: 1;
 
172
        u8                      dpdt_ctrl_keep: 1;
 
173
        u8                      antidx_antd: 3;
 
174
        u8                      antidx_antc: 3;
 
175
#endif
 
176
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
177
        u8                      antidx_anta: 3;                                                 /*antidx_anta[2:0]*/
 
178
        u8                      antidx_antb: 3;                                                 /*antidx_antb[2:0]*/
 
179
        u8                      hw_antsw_occur: 2;                                                              /*1'b0*/
 
180
#else   /*_BIG_ENDIAN_*/
 
181
        u8                      hw_antsw_occur: 2;
 
182
        u8                      antidx_antb: 3;
 
183
        u8                      antidx_anta: 3;
 
184
#endif
 
185
};
 
186
 
 
187
void
 
188
phydm_reset_rssi_for_dm(
 
189
        struct PHY_DM_STRUCT    *p_dm_odm,
 
190
        u8              station_id
 
191
);
 
192
 
 
193
void
 
194
odm_init_rssi_for_dm(
 
195
        struct PHY_DM_STRUCT    *p_dm_odm
 
196
);
 
197
 
 
198
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 
199
void
 
200
phydm_normal_driver_rx_sniffer(
 
201
        struct PHY_DM_STRUCT                    *p_dm_odm,
 
202
        u8                              *p_desc,
 
203
        PRT_RFD_STATUS          p_rt_rfd_status,
 
204
        u8                              *p_drv_info,
 
205
        u8                              phy_status
 
206
);
 
207
#endif
 
208
 
 
209
void
 
210
odm_phy_status_query(
 
211
        struct PHY_DM_STRUCT                                    *p_dm_odm,
 
212
        struct _odm_phy_status_info_                    *p_phy_info,
 
213
        u8                                              *p_phy_status,
 
214
        struct _odm_per_pkt_info_                       *p_pktinfo
 
215
);
 
216
 
 
217
void
 
218
odm_mac_status_query(
 
219
        struct PHY_DM_STRUCT                                    *p_dm_odm,
 
220
        u8                                              *p_mac_status,
 
221
        u8                                              mac_id,
 
222
        boolean                                         is_packet_match_bssid,
 
223
        boolean                                         is_packet_to_self,
 
224
        boolean                                         is_packet_beacon
 
225
);
 
226
 
 
227
enum hal_status
 
228
odm_config_rf_with_tx_pwr_track_header_file(
 
229
        struct PHY_DM_STRUCT            *p_dm_odm
 
230
);
 
231
 
 
232
enum hal_status
 
233
odm_config_rf_with_header_file(
 
234
        struct PHY_DM_STRUCT            *p_dm_odm,
 
235
        enum odm_rf_config_type         config_type,
 
236
        enum odm_rf_radio_path_e        e_rf_path
 
237
);
 
238
 
 
239
enum hal_status
 
240
odm_config_bb_with_header_file(
 
241
        struct PHY_DM_STRUCT    *p_dm_odm,
 
242
        enum odm_bb_config_type         config_type
 
243
);
 
244
 
 
245
enum hal_status
 
246
odm_config_mac_with_header_file(
 
247
        struct PHY_DM_STRUCT    *p_dm_odm
 
248
);
 
249
 
 
250
enum hal_status
 
251
odm_config_fw_with_header_file(
 
252
        struct PHY_DM_STRUCT                    *p_dm_odm,
 
253
        enum odm_fw_config_type config_type,
 
254
        u8                              *p_firmware,
 
255
        u32                             *p_size
 
256
);
 
257
 
 
258
u32
 
259
odm_get_hw_img_version(
 
260
        struct PHY_DM_STRUCT    *p_dm_odm
 
261
);
 
262
 
 
263
s32
 
264
odm_signal_scale_mapping(
 
265
        struct PHY_DM_STRUCT *p_dm_odm,
 
266
        s32 curr_sig
 
267
);
 
268
 
 
269
#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
 
270
/*For 8822B only!! need to move to FW finally */
 
271
/*==============================================*/
 
272
void
 
273
phydm_rx_phy_status_new_type(
 
274
        struct PHY_DM_STRUCT                                    *p_phydm,
 
275
        u8                                              *p_phy_status,
 
276
        struct _odm_per_pkt_info_                       *p_pktinfo,
 
277
        struct _odm_phy_status_info_                    *p_phy_info
 
278
);
 
279
 
 
280
boolean
 
281
phydm_query_is_mu_api(
 
282
        struct PHY_DM_STRUCT                    *p_phydm,
 
283
        u8                                                              ppdu_idx,
 
284
        u8                                                              *p_data_rate,
 
285
        u8                                                              *p_gid
 
286
);
 
287
 
 
288
struct _phy_status_rpt_jaguar2_type0 {
 
289
        /* DW0 */
 
290
        u8              page_num;
 
291
        u8              pwdb;
 
292
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
293
        u8              gain: 6;
 
294
        u8              rsvd_0: 1;
 
295
        u8              trsw: 1;
 
296
#else
 
297
        u8              trsw: 1;
 
298
        u8              rsvd_0: 1;
 
299
        u8              gain: 6;
 
300
#endif
 
301
        u8              rsvd_1;
 
302
 
 
303
        /* DW1 */
 
304
        u8              rsvd_2;
 
305
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
306
        u8              rxsc: 4;
 
307
        u8              agc_table: 4;
 
308
#else
 
309
        u8              agc_table: 4;
 
310
        u8              rxsc: 4;
 
311
#endif
 
312
        u8              channel;
 
313
        u8              band;
 
314
 
 
315
        /* DW2 */
 
316
        u16             length;
 
317
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
318
        u8              antidx_a: 3;
 
319
        u8              antidx_b: 3;
 
320
        u8              rsvd_3: 2;
 
321
        u8              antidx_c: 3;
 
322
        u8              antidx_d: 3;
 
323
        u8              rsvd_4:2;
 
324
#else
 
325
        u8              rsvd_3: 2;
 
326
        u8              antidx_b: 3;
 
327
        u8              antidx_a: 3;
 
328
        u8              rsvd_4:2;
 
329
        u8              antidx_d: 3;
 
330
        u8              antidx_c: 3;
 
331
#endif
 
332
 
 
333
        /* DW3 */
 
334
        u8              signal_quality;
 
335
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
336
        u8              vga:5;
 
337
        u8              lna_l:3;
 
338
        u8              bb_power:6;
 
339
        u8              rsvd_9:1;
 
340
        u8              lna_h:1;
 
341
#else
 
342
        u8              lna_l:3;
 
343
        u8              vga:5;
 
344
        u8              lna_h:1;
 
345
        u8              rsvd_9:1;
 
346
        u8              bb_power:6;
 
347
#endif
 
348
        u8              rsvd_5;
 
349
 
 
350
        /* DW4 */
 
351
        u32             rsvd_6;
 
352
 
 
353
        /* DW5 */
 
354
        u32             rsvd_7;
 
355
 
 
356
        /* DW6 */
 
357
        u32             rsvd_8;
 
358
};
 
359
 
 
360
struct _phy_status_rpt_jaguar2_type1 {
 
361
        /* DW0 and DW1 */
 
362
        u8              page_num;
 
363
        u8              pwdb[4];
 
364
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
365
        u8              l_rxsc: 4;
 
366
        u8              ht_rxsc: 4;
 
367
#else
 
368
        u8              ht_rxsc: 4;
 
369
        u8              l_rxsc: 4;
 
370
#endif
 
371
        u8              channel;
 
372
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
373
        u8              band: 2;
 
374
        u8              rsvd_0: 1;
 
375
        u8              hw_antsw_occu: 1;
 
376
        u8              gnt_bt: 1;
 
377
        u8              ldpc: 1;
 
378
        u8              stbc: 1;
 
379
        u8              beamformed: 1;
 
380
#else
 
381
        u8              beamformed: 1;
 
382
        u8              stbc: 1;
 
383
        u8              ldpc: 1;
 
384
        u8              gnt_bt: 1;
 
385
        u8              hw_antsw_occu: 1;
 
386
        u8              rsvd_0: 1;
 
387
        u8              band: 2;
 
388
#endif
 
389
 
 
390
        /* DW2 */
 
391
        u16             lsig_length;
 
392
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
393
        u8              antidx_a: 3;
 
394
        u8              antidx_b: 3;
 
395
        u8              rsvd_1: 2;
 
396
        u8              antidx_c: 3;
 
397
        u8              antidx_d: 3;
 
398
        u8              rsvd_2: 2;
 
399
#else
 
400
        u8              rsvd_1: 2;
 
401
        u8              antidx_b: 3;
 
402
        u8              antidx_a: 3;
 
403
        u8              rsvd_2: 2;
 
404
        u8              antidx_d: 3;
 
405
        u8              antidx_c: 3;
 
406
#endif
 
407
 
 
408
        /* DW3 */
 
409
        u8              paid;
 
410
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
411
        u8              paid_msb: 1;
 
412
        u8              gid: 6;
 
413
        u8              rsvd_3: 1;
 
414
#else
 
415
        u8              rsvd_3: 1;
 
416
        u8              gid: 6;
 
417
        u8              paid_msb: 1;
 
418
#endif
 
419
        u8              intf_pos;
 
420
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
421
        u8              intf_pos_msb: 1;
 
422
        u8              rsvd_4: 2;
 
423
        u8              nb_intf_flag: 1;
 
424
        u8              rf_mode: 2;
 
425
        u8              rsvd_5: 2;
 
426
#else
 
427
        u8              rsvd_5: 2;
 
428
        u8              rf_mode: 2;
 
429
        u8              nb_intf_flag: 1;
 
430
        u8              rsvd_4: 2;
 
431
        u8              intf_pos_msb: 1;
 
432
#endif
 
433
 
 
434
        /* DW4 */
 
435
        s8              rxevm[4];                       /* s(8,1) */
 
436
 
 
437
        /* DW5 */
 
438
        s8              cfo_tail[4];                    /* s(8,7) */
 
439
 
 
440
        /* DW6 */
 
441
        s8              rxsnr[4];                       /* s(8,1) */
 
442
};
 
443
 
 
444
struct _phy_status_rpt_jaguar2_type2 {
 
445
        /* DW0 ane DW1 */
 
446
        u8              page_num;
 
447
        u8              pwdb[4];
 
448
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
449
        u8              l_rxsc: 4;
 
450
        u8              ht_rxsc: 4;
 
451
#else
 
452
        u8              ht_rxsc: 4;
 
453
        u8              l_rxsc: 4;
 
454
#endif
 
455
        u8              channel;
 
456
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
457
        u8              band: 2;
 
458
        u8              rsvd_0: 1;
 
459
        u8              hw_antsw_occu: 1;
 
460
        u8              gnt_bt: 1;
 
461
        u8              ldpc: 1;
 
462
        u8              stbc: 1;
 
463
        u8              beamformed: 1;
 
464
#else
 
465
        u8              beamformed: 1;
 
466
        u8              stbc: 1;
 
467
        u8              ldpc: 1;
 
468
        u8              gnt_bt: 1;
 
469
        u8              hw_antsw_occu: 1;
 
470
        u8              rsvd_0: 1;
 
471
        u8              band: 2;
 
472
#endif
 
473
 
 
474
        /* DW2 */
 
475
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
476
        u8              shift_l_map: 6;
 
477
        u8              rsvd_1: 2;
 
478
#else
 
479
        u8              rsvd_1: 2;
 
480
        u8              shift_l_map: 6;
 
481
#endif
 
482
        u8              cnt_pw2cca;
 
483
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
484
        u8              agc_table_a: 4;
 
485
        u8              agc_table_b: 4;
 
486
        u8              agc_table_c: 4;
 
487
        u8              agc_table_d: 4;
 
488
#else
 
489
        u8              agc_table_b: 4;
 
490
        u8              agc_table_a: 4;
 
491
        u8              agc_table_d: 4;
 
492
        u8              agc_table_c: 4;
 
493
#endif
 
494
 
 
495
        /* DW3 ~ DW6*/
 
496
        u8              cnt_cca2agc_rdy;
 
497
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
498
        u8              gain_a: 6;
 
499
        u8              rsvd_2: 1;
 
500
        u8              trsw_a: 1;
 
501
        u8              gain_b: 6;
 
502
        u8              rsvd_3: 1;
 
503
        u8              trsw_b: 1;
 
504
        u8              gain_c: 6;
 
505
        u8              rsvd_4: 1;
 
506
        u8              trsw_c: 1;
 
507
        u8              gain_d: 6;
 
508
        u8              rsvd_5: 1;
 
509
        u8              trsw_d: 1;
 
510
        u8              aagc_step_a: 2;
 
511
        u8              aagc_step_b: 2;
 
512
        u8              aagc_step_c: 2;
 
513
        u8              aagc_step_d: 2;
 
514
#else
 
515
        u8              trsw_a: 1;
 
516
        u8              rsvd_2: 1;
 
517
        u8              gain_a: 6;
 
518
        u8              trsw_b: 1;
 
519
        u8              rsvd_3: 1;
 
520
        u8              gain_b: 6;
 
521
        u8              trsw_c: 1;
 
522
        u8              rsvd_4: 1;
 
523
        u8              gain_c: 6;
 
524
        u8              trsw_d: 1;
 
525
        u8              rsvd_5: 1;
 
526
        u8              gain_d: 6;
 
527
        u8              aagc_step_d: 2;
 
528
        u8              aagc_step_c: 2;
 
529
        u8              aagc_step_b: 2;
 
530
        u8              aagc_step_a: 2;
 
531
#endif
 
532
        u8              ht_aagc_gain[4];
 
533
        u8              dagc_gain[4];
 
534
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
 
535
        u8              counter: 6;
 
536
        u8              rsvd_6: 2;
 
537
        u8              syn_count: 5;
 
538
        u8              rsvd_7:3;
 
539
#else
 
540
        u8              rsvd_6: 2;
 
541
        u8              counter: 6;
 
542
        u8              rsvd_7:3;
 
543
        u8              syn_count: 5;
 
544
#endif
 
545
};
 
546
/*==============================================*/
 
547
#endif /*#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)*/
 
548
 
 
549
u32
 
550
query_phydm_trx_capability(
 
551
        struct PHY_DM_STRUCT                                    *p_dm_odm
 
552
);
 
553
 
 
554
u32
 
555
query_phydm_stbc_capability(
 
556
        struct PHY_DM_STRUCT                                    *p_dm_odm
 
557
);
 
558
 
 
559
u32
 
560
query_phydm_ldpc_capability(
 
561
        struct PHY_DM_STRUCT                                    *p_dm_odm
 
562
);
 
563
 
 
564
u32
 
565
query_phydm_txbf_parameters(
 
566
        struct PHY_DM_STRUCT                                    *p_dm_odm
 
567
);
 
568
 
 
569
u32
 
570
query_phydm_txbf_capability(
 
571
        struct PHY_DM_STRUCT                                    *p_dm_odm
 
572
);
 
573
 
 
574
#endif /*#ifndef        __HALHWOUTSRC_H__*/