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Viewing changes to hal/phydm/rtl8821c/phydm_hal_api8821c.h

  • Committer: Vitaliy Kulikov
  • Date: 2017-09-24 10:25:11 UTC
  • Revision ID: slonua@gmail.com-20170924102511-9q45rcjnowest8ee
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hal/phydm/rtl8821c/phydm_hal_api8821c.h
 
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/******************************************************************************
 
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 *
 
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 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
 
4
 *
 
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 * This program is free software; you can redistribute it and/or modify it
 
6
 * under the terms of version 2 of the GNU General Public License as
 
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 * published by the Free Software Foundation.
 
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 *
 
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 * This program is distributed in the hope that it will be useful, but WITHOUT
 
10
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 
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 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 
12
 * more details.
 
13
 *
 
14
 * You should have received a copy of the GNU General Public License along with
 
15
 * this program; if not, write to the Free Software Foundation, Inc.,
 
16
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 
17
 *
 
18
 *
 
19
 ******************************************************************************/
 
20
#ifndef __INC_PHYDM_API_H_8821C__
 
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#define __INC_PHYDM_API_H_8821C__
 
22
 
 
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#if (RTL8821C_SUPPORT == 1)
 
24
 
 
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#define PHY_CONFIG_VERSION_8821C                        "3.1.20"        /*2016.11.21     (HW user guide version: R03, SW user guide version: R01, Modification: R20)*/
 
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#define INVALID_RF_DATA                                 0xffffffff
 
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#define INVALID_TXAGC_DATA                              0xff
 
29
 
 
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#define config_phydm_read_rf_check_8821c(data)                  (data != INVALID_RF_DATA)
 
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#define config_phydm_read_txagc_check_8821c(data)               (data != INVALID_TXAGC_DATA)
 
32
 
 
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enum rf_set_8821c {
 
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        SWITCH_TO_BTG           = 0x0,
 
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        SWITCH_TO_WLG   = 0x1,
 
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        SWITCH_TO_WLA   = 0x2,
 
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        SWITCH_TO_BT            = 0x3
 
38
};
 
39
 
 
40
enum ant_num_8821c {
 
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        SWITCH_TO_ANT1  = 0x0,
 
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        SWITCH_TO_ANT2  = 0x1
 
43
};
 
44
 
 
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enum ant_num_map_8821c {
 
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        BOTH_AVAILABLE          = 0x1,
 
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        ONLY_ANT1                               = 0x2,
 
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        ONLY_ANT2                               = 0x3,
 
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        DONT_CARE                               = 0x4
 
50
};
 
51
 
 
52
u32
 
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config_phydm_read_rf_reg_8821c(
 
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        struct PHY_DM_STRUCT                            *p_dm_odm,
 
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        enum odm_rf_radio_path_e                rf_path,
 
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        u32                                     reg_addr,
 
57
        u32                                     bit_mask
 
58
);
 
59
 
 
60
boolean
 
61
config_phydm_write_rf_reg_8821c(
 
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        struct PHY_DM_STRUCT                            *p_dm_odm,
 
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        enum odm_rf_radio_path_e                rf_path,
 
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        u32                                     reg_addr,
 
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        u32                                     bit_mask,
 
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        u32                                     data
 
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);
 
68
 
 
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boolean
 
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config_phydm_write_txagc_8821c(
 
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        struct PHY_DM_STRUCT                            *p_dm_odm,
 
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        u32                                     power_index,
 
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        enum odm_rf_radio_path_e                path,
 
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        u8                                      hw_rate
 
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);
 
76
 
 
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u8
 
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config_phydm_read_txagc_8821c(
 
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        struct PHY_DM_STRUCT                            *p_dm_odm,
 
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        enum odm_rf_radio_path_e                path,
 
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        u8                                      hw_rate
 
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);
 
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boolean
 
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config_phydm_switch_band_8821c(
 
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        struct PHY_DM_STRUCT                            *p_dm_odm,
 
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        u8                                      central_ch
 
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);
 
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boolean
 
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config_phydm_switch_channel_8821c(
 
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        struct PHY_DM_STRUCT                            *p_dm_odm,
 
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        u8                                      central_ch
 
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);
 
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boolean
 
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config_phydm_switch_bandwidth_8821c(
 
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        struct PHY_DM_STRUCT                            *p_dm_odm,
 
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        u8                                      primary_ch_idx,
 
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        enum odm_bw_e                           bandwidth
 
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);
 
102
 
 
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boolean
 
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config_phydm_switch_channel_bw_8821c(
 
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        struct PHY_DM_STRUCT                            *p_dm_odm,
 
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        u8                                      central_ch,
 
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        u8                                      primary_ch_idx,
 
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        enum odm_bw_e                           bandwidth
 
109
);
 
110
 
 
111
boolean
 
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config_phydm_trx_mode_8821c(
 
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        struct PHY_DM_STRUCT                            *p_dm_odm,
 
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        enum odm_rf_path_e                      tx_path,
 
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        enum odm_rf_path_e                      rx_path,
 
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        boolean                                 is_tx2_path
 
117
);
 
118
 
 
119
boolean
 
120
config_phydm_parameter_init_8821c(
 
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        struct PHY_DM_STRUCT                            *p_dm_odm,
 
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        enum odm_parameter_init_e       type
 
123
);
 
124
 
 
125
void
 
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config_phydm_switch_rf_set_8821c(
 
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        struct PHY_DM_STRUCT                    *p_dm_odm,
 
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        u8                              rf_set
 
129
);
 
130
 
 
131
void
 
132
config_phydm_set_ant_path(
 
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        struct PHY_DM_STRUCT                    *p_dm_odm,
 
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        u8                              rf_set,
 
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        u8                              ant_num
 
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);
 
137
 
 
138
/* ======================================================================== */
 
139
/* These following functions can be used for PHY DM only*/
 
140
 
 
141
boolean
 
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phydm_write_txagc_1byte_8821c(
 
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        struct PHY_DM_STRUCT                            *p_dm_odm,
 
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        u32                                     power_index,
 
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        enum odm_rf_radio_path_e                path,
 
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        u8                                      hw_rate
 
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);
 
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void
 
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phydm_init_hw_info_by_rfe_type_8821c(
 
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        struct PHY_DM_STRUCT                            *p_dm_odm
 
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);
 
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void
 
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phydm_set_gnt_state_8821c(
 
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        struct PHY_DM_STRUCT                    *p_dm_odm,
 
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        boolean                         gnt_wl_state,
 
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        boolean                         gnt_bt_state
 
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);
 
160
 
 
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/* ======================================================================== */
 
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163
u32
 
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query_phydm_trx_capability_8821c(
 
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        struct PHY_DM_STRUCT                            *p_dm_odm
 
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);
 
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u32
 
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query_phydm_stbc_capability_8821c(
 
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        struct PHY_DM_STRUCT                            *p_dm_odm
 
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);
 
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u32
 
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query_phydm_ldpc_capability_8821c(
 
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        struct PHY_DM_STRUCT                            *p_dm_odm
 
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);
 
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u32
 
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query_phydm_txbf_parameters_8821c(
 
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        struct PHY_DM_STRUCT                            *p_dm_odm
 
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);
 
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u32
 
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query_phydm_txbf_capability_8821c(
 
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        struct PHY_DM_STRUCT                            *p_dm_odm
 
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);
 
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u8
 
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query_phydm_default_rf_set_8821c(
 
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        struct PHY_DM_STRUCT                            *p_dm_odm
 
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);
 
192
 
 
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u8
 
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query_phydm_current_rf_set_8821c(
 
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        struct PHY_DM_STRUCT                            *p_dm_odm
 
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);
 
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u8
 
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query_phydm_rfetype_8821c(
 
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        struct PHY_DM_STRUCT                            *p_dm_odm
 
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);
 
202
 
 
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u8
 
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query_phydm_current_ant_num_8821c(
 
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        struct PHY_DM_STRUCT                            *p_dm_odm
 
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);
 
207
 
 
208
u8
 
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query_phydm_ant_num_map_8821c(
 
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        struct PHY_DM_STRUCT                            *p_dm_odm
 
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);
 
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#endif  /* RTL8821C_SUPPORT == 1 */
 
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#endif  /*  __INC_PHYDM_API_H_8821C__ */