31
31
/* Position of cpu flags bitfiled. */
33
/* i186 or better required */
35
/* i286 or better required */
36
#define Cpu286 (Cpu186 + 1)
37
/* i386 or better required */
38
#define Cpu386 (Cpu286 + 1)
39
/* i486 or better required */
40
#define Cpu486 (Cpu386 + 1)
41
/* i585 or better required */
42
#define Cpu586 (Cpu486 + 1)
43
/* i686 or better required */
44
#define Cpu686 (Cpu586 + 1)
45
/* CLFLUSH Instuction support required */
46
#define CpuClflush (Cpu686 + 1)
47
/* SYSCALL Instuctions support required */
48
#define CpuSYSCALL (CpuClflush + 1)
49
/* Floating point support required */
50
#define Cpu8087 (CpuSYSCALL + 1)
51
/* i287 support required */
52
#define Cpu287 (Cpu8087 + 1)
53
/* i387 support required */
54
#define Cpu387 (Cpu287 + 1)
55
/* i686 and floating point support required */
56
#define Cpu687 (Cpu387 + 1)
57
/* SSE3 and floating point support required */
58
#define CpuFISTTP (Cpu687 + 1)
59
/* MMX support required */
60
#define CpuMMX (CpuFISTTP + 1)
61
/* SSE support required */
62
#define CpuSSE (CpuMMX + 1)
63
/* SSE2 support required */
64
#define CpuSSE2 (CpuSSE + 1)
65
/* 3dnow! support required */
66
#define Cpu3dnow (CpuSSE2 + 1)
67
/* 3dnow! Extensions support required */
68
#define Cpu3dnowA (Cpu3dnow + 1)
69
/* SSE3 support required */
70
#define CpuSSE3 (Cpu3dnowA + 1)
71
/* VIA PadLock required */
72
#define CpuPadLock (CpuSSE3 + 1)
73
/* AMD Secure Virtual Machine Ext-s required */
74
#define CpuSVME (CpuPadLock + 1)
75
/* VMX Instructions required */
76
#define CpuVMX (CpuSVME + 1)
77
/* SMX Instructions required */
78
#define CpuSMX (CpuVMX + 1)
79
/* SSSE3 support required */
80
#define CpuSSSE3 (CpuSMX + 1)
81
/* SSE4a support required */
82
#define CpuSSE4a (CpuSSSE3 + 1)
83
/* ABM New Instructions required */
84
#define CpuABM (CpuSSE4a + 1)
85
/* SSE4.1 support required */
86
#define CpuSSE4_1 (CpuABM + 1)
87
/* SSE4.2 support required */
88
#define CpuSSE4_2 (CpuSSE4_1 + 1)
89
/* AVX support required */
90
#define CpuAVX (CpuSSE4_2 + 1)
91
/* Intel L1OM support required */
92
#define CpuL1OM (CpuAVX + 1)
93
/* Xsave/xrstor New Instuctions support required */
94
#define CpuXsave (CpuL1OM + 1)
95
/* AES support required */
96
#define CpuAES (CpuXsave + 1)
97
/* PCLMUL support required */
98
#define CpuPCLMUL (CpuAES + 1)
99
/* FMA support required */
100
#define CpuFMA (CpuPCLMUL + 1)
101
/* FMA4 support required */
102
#define CpuFMA4 (CpuFMA + 1)
103
/* MOVBE Instuction support required */
104
#define CpuMovbe (CpuFMA4 + 1)
105
/* EPT Instructions required */
106
#define CpuEPT (CpuMovbe + 1)
107
/* RDTSCP Instuction support required */
108
#define CpuRdtscp (CpuEPT + 1)
109
/* 64bit support available, used by -march= in assembler. */
110
#define CpuLM (CpuRdtscp + 1)
111
/* 64bit support required */
112
#define Cpu64 (CpuLM + 1)
113
/* Not supported in the 64bit mode */
114
#define CpuNo64 (Cpu64 + 1)
115
/* The last bitfield in i386_cpu_flags. */
116
#define CpuMax CpuNo64
35
/* i186 or better required */
37
/* i286 or better required */
39
/* i386 or better required */
41
/* i486 or better required */
43
/* i585 or better required */
45
/* i686 or better required */
47
/* CLFLUSH Instuction support required */
49
/* SYSCALL Instuctions support required */
51
/* Floating point support required */
53
/* i287 support required */
55
/* i387 support required */
57
/* i686 and floating point support required */
59
/* SSE3 and floating point support required */
61
/* MMX support required */
63
/* SSE support required */
65
/* SSE2 support required */
67
/* 3dnow! support required */
69
/* 3dnow! Extensions support required */
71
/* SSE3 support required */
73
/* VIA PadLock required */
75
/* AMD Secure Virtual Machine Ext-s required */
77
/* VMX Instructions required */
79
/* SMX Instructions required */
81
/* SSSE3 support required */
83
/* SSE4a support required */
85
/* ABM New Instructions required */
87
/* SSE4.1 support required */
89
/* SSE4.2 support required */
91
/* AVX support required */
93
/* Intel L1OM support required */
95
/* Xsave/xrstor New Instuctions support required */
97
/* AES support required */
99
/* PCLMUL support required */
101
/* FMA support required */
103
/* FMA4 support required */
105
/* XOP support required */
107
/* LWP support required */
109
/* MOVBE Instuction support required */
111
/* EPT Instructions required */
113
/* RDTSCP Instuction support required */
115
/* 64bit support available, used by -march= in assembler. */
117
/* 64bit support required */
119
/* Not supported in the 64bit mode */
121
/* The last bitfield in i386_cpu_flags. */
118
125
#define CpuNumOfUints \
119
126
(CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
181
190
/* Position of opcode_modifier bits. */
183
/* has direction bit. */
185
/* set if operands can be words or dwords encoded the canonical way */
187
/* Skip the current insn and use the next insn in i386-opc.tbl to swap
188
operand in encoding. */
190
/* insn has a modrm byte. */
191
#define Modrm (S + 1)
192
/* register is in low 3 bits of opcode */
193
#define ShortForm (Modrm + 1)
194
/* special case for jump insns. */
195
#define Jump (ShortForm + 1)
197
#define JumpDword (Jump + 1)
199
#define JumpByte (JumpDword + 1)
200
/* special case for intersegment leaps/calls */
201
#define JumpInterSegment (JumpByte + 1)
202
/* FP insn memory format bit, sized by 0x4 */
203
#define FloatMF (JumpInterSegment + 1)
204
/* src/dest swap for floats. */
205
#define FloatR (FloatMF + 1)
206
/* has float insn direction bit. */
207
#define FloatD (FloatR + 1)
208
/* needs size prefix if in 32-bit mode */
209
#define Size16 (FloatD + 1)
210
/* needs size prefix if in 16-bit mode */
211
#define Size32 (Size16 + 1)
212
/* needs size prefix if in 64-bit mode */
213
#define Size64 (Size32 + 1)
214
/* instruction ignores operand size prefix and in Intel mode ignores
215
mnemonic size suffix check. */
216
#define IgnoreSize (Size64 + 1)
217
/* default insn size depends on mode */
218
#define DefaultSize (IgnoreSize + 1)
219
/* b suffix on instruction illegal */
220
#define No_bSuf (DefaultSize + 1)
221
/* w suffix on instruction illegal */
222
#define No_wSuf (No_bSuf + 1)
223
/* l suffix on instruction illegal */
224
#define No_lSuf (No_wSuf + 1)
225
/* s suffix on instruction illegal */
226
#define No_sSuf (No_lSuf + 1)
227
/* q suffix on instruction illegal */
228
#define No_qSuf (No_sSuf + 1)
229
/* long double suffix on instruction illegal */
230
#define No_ldSuf (No_qSuf + 1)
231
/* instruction needs FWAIT */
232
#define FWait (No_ldSuf + 1)
233
/* quick test for string instructions */
234
#define IsString (FWait + 1)
235
/* fake an extra reg operand for clr, imul and special register
236
processing for some instructions. */
237
#define RegKludge (IsString + 1)
238
/* The first operand must be xmm0 */
239
#define FirstXmm0 (RegKludge + 1)
240
/* An implicit xmm0 as the first operand */
241
#define Implicit1stXmm0 (FirstXmm0 + 1)
242
/* BYTE is OK in Intel syntax. */
243
#define ByteOkIntel (Implicit1stXmm0 + 1)
244
/* Convert to DWORD */
245
#define ToDword (ByteOkIntel + 1)
246
/* Convert to QWORD */
247
#define ToQword (ToDword + 1)
248
/* Address prefix changes operand 0 */
249
#define AddrPrefixOp0 (ToQword + 1)
250
/* opcode is a prefix */
251
#define IsPrefix (AddrPrefixOp0 + 1)
252
/* instruction has extension in 8 bit imm */
253
#define ImmExt (IsPrefix + 1)
254
/* instruction don't need Rex64 prefix. */
255
#define NoRex64 (ImmExt + 1)
256
/* instruction require Rex64 prefix. */
257
#define Rex64 (NoRex64 + 1)
258
/* deprecated fp insn, gets a warning */
259
#define Ugh (Rex64 + 1)
260
/* insn has VEX prefix. */
261
#define Vex (Ugh + 1)
262
/* insn has 256bit VEX prefix. */
263
#define Vex256 (Vex + 1)
264
/* insn has VEX NDS. Register-only source is encoded in Vex prefix.
265
We use VexNDS on insns with VEX DDS since the register-only source
266
is the second source register. */
267
#define VexNDS (Vex256 + 1)
268
/* insn has VEX NDD. Register destination is encoded in Vex
270
#define VexNDD (VexNDS + 1)
271
/* insn has VEX W0. */
272
#define VexW0 (VexNDD + 1)
273
/* insn has VEX W1. */
274
#define VexW1 (VexW0 + 1)
275
/* insn has VEX 0x0F opcode prefix. */
276
#define Vex0F (VexW1 + 1)
277
/* insn has VEX 0x0F38 opcode prefix. */
278
#define Vex0F38 (Vex0F + 1)
279
/* insn has VEX 0x0F3A opcode prefix. */
280
#define Vex0F3A (Vex0F38 + 1)
281
/* insn has VEX prefix with 3 soures. */
282
#define Vex3Sources (Vex0F3A + 1)
283
/* instruction has VEX 8 bit imm */
284
#define VexImmExt (Vex3Sources + 1)
285
/* SSE to AVX support required */
286
#define SSE2AVX (VexImmExt + 1)
287
/* No AVX equivalent */
288
#define NoAVX (SSE2AVX + 1)
289
/* Compatible with old (<= 2.8.1) versions of gcc */
290
#define OldGcc (NoAVX + 1)
292
#define ATTMnemonic (OldGcc + 1)
294
#define ATTSyntax (ATTMnemonic + 1)
296
#define IntelSyntax (ATTSyntax + 1)
297
/* The last bitfield in i386_opcode_modifier. */
298
#define Opcode_Modifier_Max IntelSyntax
194
/* has direction bit. */
196
/* set if operands can be words or dwords encoded the canonical way */
198
/* Skip the current insn and use the next insn in i386-opc.tbl to swap
199
operand in encoding. */
201
/* insn has a modrm byte. */
203
/* register is in low 3 bits of opcode */
205
/* special case for jump insns. */
211
/* special case for intersegment leaps/calls */
213
/* FP insn memory format bit, sized by 0x4 */
215
/* src/dest swap for floats. */
217
/* has float insn direction bit. */
219
/* needs size prefix if in 32-bit mode */
221
/* needs size prefix if in 16-bit mode */
223
/* needs size prefix if in 64-bit mode */
225
/* instruction ignores operand size prefix and in Intel mode ignores
226
mnemonic size suffix check. */
228
/* default insn size depends on mode */
230
/* b suffix on instruction illegal */
232
/* w suffix on instruction illegal */
234
/* l suffix on instruction illegal */
236
/* s suffix on instruction illegal */
238
/* q suffix on instruction illegal */
240
/* long double suffix on instruction illegal */
242
/* instruction needs FWAIT */
244
/* quick test for string instructions */
246
/* quick test for lockable instructions */
248
/* fake an extra reg operand for clr, imul and special register
249
processing for some instructions. */
251
/* The first operand must be xmm0 */
253
/* An implicit xmm0 as the first operand */
255
/* Convert to DWORD */
257
/* Convert to QWORD */
259
/* Address prefix changes operand 0 */
261
/* opcode is a prefix */
263
/* instruction has extension in 8 bit imm */
265
/* instruction don't need Rex64 prefix. */
267
/* instruction require Rex64 prefix. */
269
/* deprecated fp insn, gets a warning */
271
/* insn has VEX prefix:
272
1: 128bit VEX prefix.
273
2: 256bit VEX prefix.
274
3: Scalar VEX prefix.
280
/* How to encode VEX.vvvv:
281
0: VEX.vvvv must be 1111b.
282
1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
283
the content of source registers will be preserved.
284
VEX.DDS. The second register operand is encoded in VEX.vvvv
285
where the content of first source register will be overwritten
287
For assembler, there are no difference between VEX.NDS and
289
2. VEX.NDD. Register destination is encoded in VEX.vvvv.
290
3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
291
of the operands can access a memory location.
297
/* How the VEX.W bit is used:
298
0: Set by the REX.W bit.
299
1: VEX.W0. Should always be 0.
300
2: VEX.W1. Should always be 1.
305
/* VEX opcode prefix:
306
0: VEX 0x0F opcode prefix.
307
1: VEX 0x0F38 opcode prefix.
308
2: VEX 0x0F3A opcode prefix
309
3: XOP 0x08 opcode prefix.
310
4: XOP 0x09 opcode prefix
311
5: XOP 0x0A opcode prefix.
320
/* number of VEX source operands:
321
0: <= 2 source operands.
322
1: 2 XOP source operands.
323
2: 3 source operands.
325
#define XOP2SOURCES 1
326
#define VEX3SOURCES 2
328
/* instruction has VEX 8 bit imm */
330
/* SSE to AVX support required */
332
/* No AVX equivalent */
334
/* Compatible with old (<= 2.8.1) versions of gcc */
342
/* The last bitfield in i386_opcode_modifier. */
300
346
typedef struct i386_opcode_modifier
358
399
/* Position of operand_type bits. */
363
#define Reg16 (Reg8 + 1)
365
#define Reg32 (Reg16 + 1)
367
#define Reg64 (Reg32 + 1)
368
/* Floating pointer stack register */
369
#define FloatReg (Reg64 + 1)
371
#define RegMMX (FloatReg + 1)
373
#define RegXMM (RegMMX + 1)
375
#define RegYMM (RegXMM + 1)
376
/* Control register */
377
#define Control (RegYMM + 1)
379
#define Debug (Control + 1)
381
#define Test (Debug + 1)
382
/* 2 bit segment register */
383
#define SReg2 (Test + 1)
384
/* 3 bit segment register */
385
#define SReg3 (SReg2 + 1)
386
/* 1 bit immediate */
387
#define Imm1 (SReg3 + 1)
388
/* 8 bit immediate */
389
#define Imm8 (Imm1 + 1)
390
/* 8 bit immediate sign extended */
391
#define Imm8S (Imm8 + 1)
392
/* 16 bit immediate */
393
#define Imm16 (Imm8S + 1)
394
/* 32 bit immediate */
395
#define Imm32 (Imm16 + 1)
396
/* 32 bit immediate sign extended */
397
#define Imm32S (Imm32 + 1)
398
/* 64 bit immediate */
399
#define Imm64 (Imm32S + 1)
400
/* 8bit/16bit/32bit displacements are used in different ways,
401
depending on the instruction. For jumps, they specify the
402
size of the PC relative displacement, for instructions with
403
memory operand, they specify the size of the offset relative
404
to the base register, and for instructions with memory offset
405
such as `mov 1234,%al' they specify the size of the offset
406
relative to the segment base. */
407
/* 8 bit displacement */
408
#define Disp8 (Imm64 + 1)
409
/* 16 bit displacement */
410
#define Disp16 (Disp8 + 1)
411
/* 32 bit displacement */
412
#define Disp32 (Disp16 + 1)
413
/* 32 bit signed displacement */
414
#define Disp32S (Disp32 + 1)
415
/* 64 bit displacement */
416
#define Disp64 (Disp32S + 1)
417
/* Accumulator %al/%ax/%eax/%rax */
418
#define Acc (Disp64 + 1)
419
/* Floating pointer top stack register %st(0) */
420
#define FloatAcc (Acc + 1)
421
/* Register which can be used for base or index in memory operand. */
422
#define BaseIndex (FloatAcc + 1)
423
/* Register to hold in/out port addr = dx */
424
#define InOutPortReg (BaseIndex + 1)
425
/* Register to hold shift count = cl */
426
#define ShiftCount (InOutPortReg + 1)
427
/* Absolute address for jump. */
428
#define JumpAbsolute (ShiftCount + 1)
429
/* String insn operand with fixed es segment */
430
#define EsSeg (JumpAbsolute + 1)
431
/* RegMem is for instructions with a modrm byte where the register
432
destination operand should be encoded in the mod and regmem fields.
433
Normally, it will be encoded in the reg field. We add a RegMem
434
flag to the destination register operand to indicate that it should
435
be encoded in the regmem field. */
436
#define RegMem (EsSeg + 1)
438
#define Mem (RegMem + 1)
440
#define Byte (Mem + 1)
441
/* WORD memory. 2 byte */
442
#define Word (Byte + 1)
443
/* DWORD memory. 4 byte */
444
#define Dword (Word + 1)
445
/* FWORD memory. 6 byte */
446
#define Fword (Dword + 1)
447
/* QWORD memory. 8 byte */
448
#define Qword (Fword + 1)
449
/* TBYTE memory. 10 byte */
450
#define Tbyte (Qword + 1)
451
/* XMMWORD memory. */
452
#define Xmmword (Tbyte + 1)
453
/* YMMWORD memory. */
454
#define Ymmword (Xmmword + 1)
455
/* Unspecified memory size. */
456
#define Unspecified (Ymmword + 1)
457
/* Any memory size. */
458
#define Anysize (Unspecified + 1)
460
/* The last bitfield in i386_operand_type. */
461
#define OTMax Anysize
411
/* Floating pointer stack register */
419
/* Control register */
425
/* 2 bit segment register */
427
/* 3 bit segment register */
429
/* 1 bit immediate */
431
/* 8 bit immediate */
433
/* 8 bit immediate sign extended */
435
/* 16 bit immediate */
437
/* 32 bit immediate */
439
/* 32 bit immediate sign extended */
441
/* 64 bit immediate */
443
/* 8bit/16bit/32bit displacements are used in different ways,
444
depending on the instruction. For jumps, they specify the
445
size of the PC relative displacement, for instructions with
446
memory operand, they specify the size of the offset relative
447
to the base register, and for instructions with memory offset
448
such as `mov 1234,%al' they specify the size of the offset
449
relative to the segment base. */
450
/* 8 bit displacement */
452
/* 16 bit displacement */
454
/* 32 bit displacement */
456
/* 32 bit signed displacement */
458
/* 64 bit displacement */
460
/* Accumulator %al/%ax/%eax/%rax */
462
/* Floating pointer top stack register %st(0) */
464
/* Register which can be used for base or index in memory operand. */
466
/* Register to hold in/out port addr = dx */
468
/* Register to hold shift count = cl */
470
/* Absolute address for jump. */
472
/* String insn operand with fixed es segment */
474
/* RegMem is for instructions with a modrm byte where the register
475
destination operand should be encoded in the mod and regmem fields.
476
Normally, it will be encoded in the reg field. We add a RegMem
477
flag to the destination register operand to indicate that it should
478
be encoded in the regmem field. */
484
/* WORD memory. 2 byte */
486
/* DWORD memory. 4 byte */
488
/* FWORD memory. 6 byte */
490
/* QWORD memory. 8 byte */
492
/* TBYTE memory. 10 byte */
494
/* XMMWORD memory. */
496
/* YMMWORD memory. */
498
/* Unspecified memory size. */
500
/* Any memory size. */
503
/* Vector 4 bit immediate. */
506
/* The last bitfield in i386_operand_type. */
463
510
#define OTNumOfUints \
464
511
(OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
added
removed
opcodes/i386-opc.h
