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  • Committer: Bazaar Package Importer
  • Author(s): Jordi Mallach, Emmanuel Kasper, Félix Arreola Rodríguez, Jordi Mallach
  • Date: 2011-05-11 21:06:50 UTC
  • mfrom: (1.1.1 upstream)
  • Revision ID: james.westby@ubuntu.com-20110511210650-jizvh8a6x117y9hr
Tags: 0.142-1
[ Emmanuel Kasper ]
* New upstream release
* Set NOWERROR=1 to allow compiling with gcc-4.6
* Remove fix_powerpc_build.patch, as upstream has taken it in this release
* Add gnome-video-arcade front end as a suggested package

[ Félix Arreola Rodríguez ]
* Add kfreebsd-build.patch to quilt series, to fix build on kfreebsd

[ Jordi Mallach ]
* Remove unneeded and bogus addition of --with-quilt to the dh invocation.
* Add Cesare Falco (long time Ubuntu maintainer) to Uploaders, and wrap
  them into multiple lines.

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src/emu/machine/z8536.c
 
1
/**********************************************************************
 
2
 
 
3
    Zilog Z8536 Counter/Timer and Parallel I/O emulation
 
4
 
 
5
    Copyright MESS Team.
 
6
    Visit http://mamedev.org for licensing and usage restrictions.
 
7
 
 
8
**********************************************************************/
 
9
 
 
10
#include "emu.h"
 
11
#include "z8536.h"
 
12
#include "machine/devhelpr.h"
 
13
 
 
14
 
 
15
 
 
16
//**************************************************************************
 
17
//  MACROS / CONSTANTS
 
18
//**************************************************************************
 
19
 
 
20
// states
 
21
enum
 
22
{
 
23
        STATE_RESET = -1,
 
24
        STATE_0,
 
25
        STATE_1
 
26
};
 
27
 
 
28
 
 
29
// ports
 
30
enum
 
31
{
 
32
        PORT_C = 0,
 
33
        PORT_B,
 
34
        PORT_A,
 
35
        CONTROL
 
36
};
 
37
 
 
38
 
 
39
// registers
 
40
enum
 
41
{
 
42
        MASTER_INTERRUPT_CONTROL = 0,
 
43
        MASTER_CONFIGURATION_CONTROL,
 
44
        PORT_A_INTERRUPT_VECTOR,
 
45
        PORT_B_INTERRUPT_VECTOR,
 
46
        COUNTER_TIMER_INTERRUPT_VECTOR,
 
47
        PORT_C_DATA_PATH_POLARITY,
 
48
        PORT_C_DATA_DIRECTION,
 
49
        PORT_C_SPECIAL_IO_CONTROL,
 
50
        PORT_A_COMMAND_AND_STATUS,
 
51
        PORT_B_COMMAND_AND_STATUS,
 
52
        COUNTER_TIMER_1_COMMAND_AND_STATUS,
 
53
        COUNTER_TIMER_2_COMMAND_AND_STATUS,
 
54
        COUNTER_TIMER_3_COMMAND_AND_STATUS,
 
55
        PORT_A_DATA,
 
56
        PORT_B_DATA,
 
57
        PORT_C_DATA,
 
58
        COUNTER_TIMER_1_CURRENT_COUNT_MS_BYTE,
 
59
        COUNTER_TIMER_1_CURRENT_COUNT_LS_BYTE,
 
60
        COUNTER_TIMER_2_CURRENT_COUNT_MS_BYTE,
 
61
        COUNTER_TIMER_2_CURRENT_COUNT_LS_BYTE,
 
62
        COUNTER_TIMER_3_CURRENT_COUNT_MS_BYTE,
 
63
        COUNTER_TIMER_3_CURRENT_COUNT_LS_BYTE,
 
64
        COUNTER_TIMER_1_TIME_CONSTANT_MS_BYTE,
 
65
        COUNTER_TIMER_1_TIME_CONSTANT_LS_BYTE,
 
66
        COUNTER_TIMER_2_TIME_CONSTANT_MS_BYTE,
 
67
        COUNTER_TIMER_2_TIME_CONSTANT_LS_BYTE,
 
68
        COUNTER_TIMER_3_TIME_CONSTANT_MS_BYTE,
 
69
        COUNTER_TIMER_3_TIME_CONSTANT_LS_BYTE,
 
70
        COUNTER_TIMER_1_MODE_SPECIFICATION,
 
71
        COUNTER_TIMER_2_MODE_SPECIFICATION,
 
72
        COUNTER_TIMER_3_MODE_SPECIFICATION,
 
73
        CURRENT_VECTOR,
 
74
        PORT_A_MODE_SPECIFICATION,
 
75
        PORT_A_HANDSHAKE_SPECIFICATION,
 
76
        PORT_A_DATA_PATH_POLARITY,
 
77
        PORT_A_DATA_DIRECTION,
 
78
        PORT_A_SPECIAL_IO_CONTROL,
 
79
        PORT_A_PATTERN_POLARITY,
 
80
        PORT_A_PATTERN_TRANSITION,
 
81
        PORT_A_PATTERN_MASK,
 
82
        PORT_B_MODE_SPECIFICATION,
 
83
        PORT_B_HANDSHAKE_SPECIFICATION,
 
84
        PORT_B_DATA_PATH_POLARITY,
 
85
        PORT_B_DATA_DIRECTION,
 
86
        PORT_B_SPECIAL_IO_CONTROL,
 
87
        PORT_B_PATTERN_POLARITY,
 
88
        PORT_B_PATTERN_TRANSITION,
 
89
        PORT_B_PATTERN_MASK
 
90
};
 
91
 
 
92
 
 
93
// counter/timer link control
 
94
enum
 
95
{
 
96
        LC_INDEPENDENT = 0,
 
97
        LC_CT1_GATES_CT2,
 
98
        LC_CT1_TRIGGERS_CT2,
 
99
        LC_CT1_COUNTS_CT2
 
100
};
 
101
 
 
102
 
 
103
// port type select
 
104
enum
 
105
{
 
106
        PTS_BIT = 0,
 
107
        PTS_INPUT,
 
108
        PTS_OUTPUT,
 
109
        PTS_BIDIRECTIONAL
 
110
};
 
111
 
 
112
 
 
113
// pattern mode specification
 
114
enum
 
115
{
 
116
        PMS_DISABLE = 0,
 
117
        PMS_AND,
 
118
        PMS_OR,
 
119
        PMS_VECTOR
 
120
};
 
121
 
 
122
 
 
123
// handshake specification
 
124
enum
 
125
{
 
126
        HTS_INTERLOCKED = 0,
 
127
        HTS_STROBED,
 
128
        HTS_PULSED,
 
129
        HTS_3_WIRE
 
130
};
 
131
 
 
132
 
 
133
// request/wait specification
 
134
enum
 
135
{
 
136
        RWS_DISABLED = 0,
 
137
        RWS_OUTPUT_WAIT,
 
138
        RWS_INPUT_WAIT = 3,
 
139
        RWS_SPECIAL_REQUEST,
 
140
        RWS_OUTPUT_REQUEST,
 
141
        RWS_INPUT_REQUEST = 7
 
142
};
 
143
 
 
144
 
 
145
// pattern specification
 
146
enum
 
147
{
 
148
        BIT_MASKED_OFF = 0,
 
149
        ANY_TRANSITION,
 
150
        ZERO = 4,
 
151
        ONE,
 
152
        ONE_TO_ZERO,
 
153
        ZERO_TO_ONE
 
154
};
 
155
 
 
156
 
 
157
// output duty cycle
 
158
enum
 
159
{
 
160
        DCS_PULSE,
 
161
        DCS_ONE_SHOT,
 
162
        DCS_SQUARE_WAVE,
 
163
        DCS_DO_NOT_USE
 
164
};
 
165
 
 
166
 
 
167
// master interrupt control register
 
168
#define MICR_RESET              0x01    // reset
 
169
#define MICR_RJA                0x02    // right justified address
 
170
#define MICR_CT_VIS             0x04    // counter/timer vector includes status
 
171
#define MICR_PB_VIS             0x08    // port B vector includes status
 
172
#define MICR_PA_VIS             0x10    // port A vector includes status
 
173
#define MICR_NV                 0x20    // no vector
 
174
#define MICR_DLC                0x40    // disable lower chain
 
175
#define MICR_MIE                0x80    // master interrupt enable
 
176
 
 
177
 
 
178
// master configuration control register
 
179
#define MCCR_LC_MASK    0x03    // counter/timer link controls
 
180
#define MCCR_PAE                0x04    // port A enable
 
181
#define MCCR_PLC                0x08    // port link control
 
182
#define MCCR_PCE_CT3E   0x10    // port C and counter/timer 3 enable
 
183
#define MCCR_CT2E               0x20    // counter/timer 2 enable
 
184
#define MCCR_CT1E               0x40    // counter/timer 1 enable
 
185
#define MCCR_PBE                0x80    // port B enable
 
186
 
 
187
 
 
188
// port mode specification registers
 
189
#define PMS_LPM                 0x01    // latch on pattern match
 
190
#define PMS_PMS_MASK    0x06    // pattern mode specification
 
191
#define PMS_IMO                 0x08    // interrupt on match only
 
192
#define PMS_SB                  0x10    // single buffer
 
193
#define PMS_ITB                 0x20    // interrupt on two bytes
 
194
#define PMS_PTS_MASK    0xc0    // port type select
 
195
 
 
196
 
 
197
// port handshake specification registers
 
198
#define PHS_DTS_MASK    0x07    // deskew time specification
 
199
#define PHS_RWS_MASK    0x38    // request/wait specification
 
200
#define PHS_HTS_MASK    0xc0    // handshake type specification
 
201
 
 
202
 
 
203
// port command and status registers
 
204
#define PCS_IOE                 0x01    // interrupt on error
 
205
#define PCS_PMF                 0x02    // pattern match flag (read only)
 
206
#define PCS_IRF                 0x04    // input register full (read only)
 
207
#define PCS_ORE                 0x08    // output register empty (read only)
 
208
#define PCS_ERR                 0x10    // interrupt error (read only)
 
209
#define PCS_IP                  0x20    // interrupt pending
 
210
#define PCS_IE                  0x40    // interrupt enable
 
211
#define PCS_IUS                 0x80    // interrupt under service
 
212
 
 
213
 
 
214
// counter/timer mode specification registers
 
215
#define CTMS_DCS_MASK   0x03    // output duty cycle
 
216
#define CTMS_REB                0x04    // retrigger enable bit
 
217
#define CTMS_EDE                0x08    // external gate enable
 
218
#define CTMS_ETE                0x10    // external trigger enable
 
219
#define CTMS_ECE                0x20    // external count enable
 
220
#define CTMS_EOE                0x40    // external output enable
 
221
#define CTMS_CSC                0x80    // continuous single cycle
 
222
 
 
223
 
 
224
// counter/timer command and status registers
 
225
#define CTCS_CIP                0x01    // count in progress (read only)
 
226
#define CTCS_TCB                0x02    // trigger command bit (write only - read returns 0)
 
227
#define CTCS_GCB                0x04    // gate command bit
 
228
#define CTCS_RCC                0x08    // read counter control (read/set only - cleared by reading CCR LSB)
 
229
#define CTCS_ERR                0x10    // interrupt error (read only)
 
230
#define CTCS_IP                 0x20    // interrupt pending
 
231
#define CTCS_IE                 0x40    // interrupt enable
 
232
#define CTCS_IUS                0x80    // interrupt under service
 
233
 
 
234
 
 
235
 
 
236
//**************************************************************************
 
237
//  DEVICE DEFINITIONS
 
238
//**************************************************************************
 
239
 
 
240
const device_type Z8536 = z8536_device_config::static_alloc_device_config;
 
241
 
 
242
 
 
243
 
 
244
//**************************************************************************
 
245
//  DEVICE CONFIGURATION
 
246
//**************************************************************************
 
247
 
 
248
GENERIC_DEVICE_CONFIG_SETUP(z8536, "Zilog Z8536")
 
249
 
 
250
 
 
251
//-------------------------------------------------
 
252
//  device_config_complete - perform any
 
253
//  operations now that the configuration is
 
254
//  complete
 
255
//-------------------------------------------------
 
256
 
 
257
void z8536_device_config::device_config_complete()
 
258
{
 
259
        // inherit a copy of the static data
 
260
        const z8536_interface *intf = reinterpret_cast<const z8536_interface *>(static_config());
 
261
        if (intf != NULL)
 
262
                *static_cast<z8536_interface *>(this) = *intf;
 
263
 
 
264
        // or initialize to defaults if none provided
 
265
        else
 
266
        {
 
267
                memset(&m_out_int_func, 0, sizeof(m_out_int_func));
 
268
                memset(&m_in_pa_func, 0, sizeof(m_in_pa_func));
 
269
                memset(&m_out_pa_func, 0, sizeof(m_out_pa_func));
 
270
                memset(&m_in_pb_func, 0, sizeof(m_in_pb_func));
 
271
                memset(&m_out_pb_func, 0, sizeof(m_out_pb_func));
 
272
                memset(&m_in_pc_func, 0, sizeof(m_in_pc_func));
 
273
                memset(&m_out_pc_func, 0, sizeof(m_out_pc_func));
 
274
        }
 
275
}
 
276
 
 
277
 
 
278
 
 
279
//**************************************************************************
 
280
//  INLINE HELPERS
 
281
//**************************************************************************
 
282
 
 
283
//-------------------------------------------------
 
284
//  read_register - read from register
 
285
//-------------------------------------------------
 
286
 
 
287
inline UINT8 z8536_device::read_register(offs_t offset)
 
288
{
 
289
        UINT8 data = 0;
 
290
 
 
291
        data = m_register[offset]; // HACK
 
292
 
 
293
        switch (offset)
 
294
        {
 
295
        case PORT_A_DATA:
 
296
                data = devcb_call_read8(&m_in_pa_func, 0);
 
297
                break;
 
298
 
 
299
        case PORT_B_DATA:
 
300
                data = devcb_call_read8(&m_in_pb_func, 0);
 
301
                break;
 
302
 
 
303
        case PORT_C_DATA:
 
304
                data = 0xf0 | (devcb_call_read8(&m_in_pc_func, 0) & 0x0f);
 
305
                break;
 
306
 
 
307
        default:
 
308
                logerror("Z8536 '%s' Unimplemented read from register %u\n", tag(), offset);
 
309
        }
 
310
 
 
311
        return data;
 
312
}
 
313
 
 
314
 
 
315
//-------------------------------------------------
 
316
//  read_register - masked read from register
 
317
//-------------------------------------------------
 
318
 
 
319
inline UINT8 z8536_device::read_register(offs_t offset, UINT8 mask)
 
320
{
 
321
        return read_register(offset) & mask;
 
322
}
 
323
 
 
324
 
 
325
//-------------------------------------------------
 
326
//  write_register - write to register
 
327
//-------------------------------------------------
 
328
 
 
329
inline void z8536_device::write_register(offs_t offset, UINT8 data)
 
330
{
 
331
        switch (offset)
 
332
        {
 
333
        case MASTER_INTERRUPT_CONTROL:
 
334
                if (data & MICR_RESET)
 
335
                {
 
336
                        device_reset();
 
337
                }
 
338
                else if (m_state == STATE_RESET)
 
339
                {
 
340
                        m_state = STATE_0;
 
341
                }
 
342
                break;
 
343
 
 
344
        case PORT_A_DATA:
 
345
                devcb_call_write8(&m_out_pa_func, 0, data);
 
346
                break;
 
347
 
 
348
        case PORT_B_DATA:
 
349
                devcb_call_write8(&m_out_pb_func, 0, data);
 
350
                break;
 
351
 
 
352
        case PORT_C_DATA:
 
353
                {
 
354
                UINT8 mask = (data & 0xf0) | (data >> 4);
 
355
 
 
356
                m_output[PORT_C] = (m_output[PORT_C] & mask) | ((data & 0x0f) & (mask ^ 0xff));
 
357
 
 
358
                devcb_call_write8(&m_out_pc_func, 0, m_output[PORT_C]);
 
359
                }
 
360
                break;
 
361
 
 
362
        default:
 
363
                logerror("Z8536 '%s' Unimplemented write %02x to register %u\n", tag(), data, offset);
 
364
        }
 
365
 
 
366
        m_register[offset] = data; // HACK
 
367
}
 
368
 
 
369
 
 
370
//-------------------------------------------------
 
371
//  write_register - masked write to register
 
372
//-------------------------------------------------
 
373
 
 
374
inline void z8536_device::write_register(offs_t offset, UINT8 data, UINT8 mask)
 
375
{
 
376
        UINT8 combined_data = (data & mask) | (m_register[offset] & (mask ^ 0xff));
 
377
 
 
378
        write_register(offset, combined_data);
 
379
}
 
380
 
 
381
 
 
382
//-------------------------------------------------
 
383
//   count -
 
384
//-------------------------------------------------
 
385
 
 
386
inline void z8536_device::count(device_timer_id id)
 
387
{
 
388
}
 
389
 
 
390
 
 
391
//-------------------------------------------------
 
392
//  trigger -
 
393
//-------------------------------------------------
 
394
 
 
395
inline void z8536_device::trigger(device_timer_id id)
 
396
{
 
397
}
 
398
 
 
399
 
 
400
//-------------------------------------------------
 
401
//  gate -
 
402
//-------------------------------------------------
 
403
 
 
404
inline void z8536_device::gate(device_timer_id id)
 
405
{
 
406
}
 
407
 
 
408
 
 
409
 
 
410
//**************************************************************************
 
411
//  LIVE DEVICE
 
412
//**************************************************************************
 
413
 
 
414
//-------------------------------------------------
 
415
//  z8536_device - constructor
 
416
//-------------------------------------------------
 
417
 
 
418
z8536_device::z8536_device(running_machine &_machine, const z8536_device_config &config)
 
419
    : device_t(_machine, config),
 
420
      m_config(config)
 
421
{
 
422
}
 
423
 
 
424
 
 
425
//-------------------------------------------------
 
426
//  device_start - device-specific startup
 
427
//-------------------------------------------------
 
428
 
 
429
void z8536_device::device_start()
 
430
{
 
431
        // allocate timers
 
432
        m_timer[TIMER_1] = timer_alloc(TIMER_1);
 
433
        m_timer[TIMER_2] = timer_alloc(TIMER_2);
 
434
        m_timer[TIMER_3] = timer_alloc(TIMER_3);
 
435
 
 
436
        // resolve callbacks
 
437
        devcb_resolve_write_line(&m_out_int_func, &m_config.m_out_int_func, this);
 
438
        devcb_resolve_read8(&m_in_pa_func, &m_config.m_in_pa_func, this);
 
439
        devcb_resolve_write8(&m_out_pa_func, &m_config.m_out_pa_func, this);
 
440
        devcb_resolve_read8(&m_in_pb_func, &m_config.m_in_pb_func, this);
 
441
        devcb_resolve_write8(&m_out_pb_func, &m_config.m_out_pb_func, this);
 
442
        devcb_resolve_read8(&m_in_pc_func, &m_config.m_in_pc_func, this);
 
443
        devcb_resolve_write8(&m_out_pc_func, &m_config.m_out_pc_func, this);
 
444
}
 
445
 
 
446
 
 
447
//-------------------------------------------------
 
448
//  device_start - device-specific reset
 
449
//-------------------------------------------------
 
450
 
 
451
void z8536_device::device_reset()
 
452
{
 
453
        m_state = STATE_RESET;
 
454
 
 
455
        for (int i = 0; i < 48; i++)
 
456
        {
 
457
                m_register[i] = 0;
 
458
        }
 
459
 
 
460
        m_register[MASTER_INTERRUPT_CONTROL] = MICR_RESET;
 
461
        m_pointer = 0;
 
462
}
 
463
 
 
464
 
 
465
//-------------------------------------------------
 
466
//  device_timer - handler timer events
 
467
//-------------------------------------------------
 
468
 
 
469
void z8536_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
 
470
{
 
471
        switch (id)
 
472
        {
 
473
        case TIMER_1:
 
474
                count(TIMER_1);
 
475
                break;
 
476
 
 
477
        case TIMER_2:
 
478
                count(TIMER_2);
 
479
                break;
 
480
 
 
481
        case TIMER_3:
 
482
                count(TIMER_3);
 
483
                break;
 
484
        }
 
485
}
 
486
 
 
487
 
 
488
//-------------------------------------------------
 
489
//  read - register read
 
490
//-------------------------------------------------
 
491
 
 
492
READ8_MEMBER( z8536_device::read )
 
493
{
 
494
        UINT8 data = 0;
 
495
 
 
496
        if (m_state == STATE_RESET)
 
497
        {
 
498
                // read RESET bit
 
499
                data = read_register(m_pointer, 0x01);
 
500
        }
 
501
        else
 
502
        {
 
503
                switch (offset & 0x03)
 
504
                {
 
505
                case PORT_C:
 
506
                        data = read_register(PORT_C_DATA);
 
507
                        break;
 
508
 
 
509
                case PORT_B:
 
510
                        data = read_register(PORT_B_DATA);
 
511
                        break;
 
512
 
 
513
                case PORT_A:
 
514
                        data = read_register(PORT_A_DATA);
 
515
                        break;
 
516
 
 
517
                case CONTROL:
 
518
                        switch (m_state)
 
519
                        {
 
520
                        case STATE_1:
 
521
                                m_state = STATE_0;
 
522
                                // fallthru
 
523
                        case STATE_0:
 
524
                                data = read_register(m_pointer);
 
525
                                break;
 
526
                        }
 
527
                        break;
 
528
                }
 
529
        }
 
530
 
 
531
        return data;
 
532
}
 
533
 
 
534
 
 
535
//-------------------------------------------------
 
536
//  write - register write
 
537
//-------------------------------------------------
 
538
 
 
539
WRITE8_MEMBER( z8536_device::write )
 
540
{
 
541
        if (m_state == STATE_RESET)
 
542
        {
 
543
                // write RESET bit
 
544
                write_register(m_pointer, data, 0x01);
 
545
        }
 
546
        else
 
547
        {
 
548
                switch (offset & 0x03)
 
549
                {
 
550
                case PORT_C:
 
551
                        write_register(PORT_C_DATA, data);
 
552
                        break;
 
553
 
 
554
                case PORT_B:
 
555
                        write_register(PORT_B_DATA, data);
 
556
                        break;
 
557
 
 
558
                case PORT_A:
 
559
                        write_register(PORT_A_DATA, data);
 
560
                        break;
 
561
 
 
562
                case CONTROL:
 
563
                        switch (m_state)
 
564
                        {
 
565
                        case STATE_0:
 
566
                                m_pointer = data;
 
567
                                m_state = STATE_1;
 
568
                                break;
 
569
 
 
570
                        case STATE_1:
 
571
                                write_register(m_pointer, data);
 
572
                                m_state = STATE_0;
 
573
                        }
 
574
                        break;
 
575
                }
 
576
        }
 
577
}
 
578
 
 
579
 
 
580
//-------------------------------------------------
 
581
//  intack_w - interrupt acknowledge
 
582
//-------------------------------------------------
 
583
 
 
584
WRITE_LINE_MEMBER( z8536_device::intack_w )
 
585
{
 
586
}
 
587
 
 
588
 
 
589
//-------------------------------------------------
 
590
//  pb*_w - port B bits 0-7 write
 
591
//-------------------------------------------------
 
592
 
 
593
WRITE_LINE_MEMBER( z8536_device::pb0_w ) { }
 
594
WRITE_LINE_MEMBER( z8536_device::pb1_w ) { }
 
595
WRITE_LINE_MEMBER( z8536_device::pb2_w ) { }
 
596
WRITE_LINE_MEMBER( z8536_device::pb3_w ) { }
 
597
WRITE_LINE_MEMBER( z8536_device::pb4_w ) { }
 
598
WRITE_LINE_MEMBER( z8536_device::pb5_w ) { }
 
599
WRITE_LINE_MEMBER( z8536_device::pb6_w ) { }
 
600
WRITE_LINE_MEMBER( z8536_device::pb7_w ) { }
 
601
 
 
602
 
 
603
//-------------------------------------------------
 
604
//  pc*_w - port C bits 0-3 write
 
605
//-------------------------------------------------
 
606
 
 
607
WRITE_LINE_MEMBER( z8536_device::pc0_w ) { }
 
608
WRITE_LINE_MEMBER( z8536_device::pc1_w ) { }
 
609
WRITE_LINE_MEMBER( z8536_device::pc2_w ) { }
 
610
WRITE_LINE_MEMBER( z8536_device::pc3_w ) { }