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###############################################################################
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# simulavr - A simulator for the Atmel AVR family of microcontrollers.
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# Copyright (C) 2001, 2002 Theodore A. Roth
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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###############################################################################
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# $Id: test_MULS.py,v 1.1 2002/04/02 16:12:55 troth Exp $
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"""Test the MULS opcode.
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from registers import Reg, SREG
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class MULS_TestFail(base_test.TestFail): pass
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class base_MULS(base_test.opcode_test):
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"""Generic test case for testing MULS opcode.
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description: multiply two signed numbers and save the result in R1:R0 (highb:lowbyte)
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opcode: 0000 0010 dddd rrrr 16 <= d,r <= 31
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changes: R1,R0,SREG: C set if R15 set, Z set if result 0x0000
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# Set SREG to zero or only C flag set
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self.setup_regs[Reg.SREG] = 0x0
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# Set the register values
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self.setup_regs[self.Rd] = self.Vd & 0xff
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self.setup_regs[self.Rr] = self.Vr & 0xff
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# Return the raw opcode
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return 0x0200 | (self.Rr & 0x0f) | (self.Rd & 0x0f) << 4
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def analyze_results(self):
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self.reg_changed.extend( [Reg.R00, Reg.R01, Reg.SREG] )
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# Vd is a negative 8 bit number, so convert to 32 bit
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# Vd is a negative 8 bit number, so convert to 32 bit
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# check that result is correct
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res = (self.Vd * self.Vr)
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got = self.anal_regs[Reg.R00] | self.anal_regs[Reg.R01] << 8
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self.fail('MULS calc r%02d, r%02d: %d * %d = (expect=%04x, got=%04x)' % (
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self.Rd, self.Rr, self.Vd,
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self.Vr, expect, got))
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# calculate what we expect sreg to be
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C = (expect & 0x8000) >> 15
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expect_sreg += (expect == 0) << SREG.Z
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expect_sreg += C << SREG.C
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got_sreg = self.anal_regs[Reg.SREG]
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if expect_sreg != got_sreg:
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self.fail('MULS flag setting: 0x%d * 0x%d -> SREG (expect=%02x, got=%02x)' % (
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self.Vd, self.Vr, expect_sreg, got_sreg))
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# Template code for test case.
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# The fail method will raise a test specific exception.
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class MULS_rd%02d_vd%02x_rr%02d_vr%02x_TestFail(MULS_TestFail): pass
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class test_MULS_rd%02d_vd%02x_rr%02d_vr%02x(base_MULS):
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raise MULS_rd%02d_vd%02x_rr%02d_vr%02x_TestFail, s
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# Define a list of test values such that we all the cases of SREG bits being set.
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# automagically generate the test_MULS_rdNN_vdXX_rrNN_vrXX_C[01] class definitions.
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# For these, we don't want Rd=Rr as that is a special case handled below.
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for d in range(16,32,step):
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for r in range(17,32,step):
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args = (d, vd, r, vr)*4
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code += template % args
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# Special case when Rd==Rr, make sure Vd==Vr.
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for d in range(16,32,step):
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args = (d, vd, d, vd)*4
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code += template % args
added
removed
regress/test_opcodes/test_MULS.py
