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###############################################################################
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# simulavr - A simulator for the Atmel AVR family of microcontrollers.
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# Copyright (C) 2001, 2002 Theodore A. Roth
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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###############################################################################
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# $Id: test_ROR.py,v 1.1 2002/02/23 01:35:39 troth Exp $
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"""Test the ROR opcode.
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from registers import Reg, SREG
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class ROR_TestFail(base_test.TestFail): pass
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class base_ROR(base_test.opcode_test):
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"""Generic test case for testing ROR opcode.
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ROR - Rotate Right through Carry
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opcode is '1001 010d dddd 0111' where d is register (0-31)
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Only registers PC, Rd and SREG should be changed.
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self.setup_regs[Reg.SREG] = (self.C << SREG.C)
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# Set the register values
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self.setup_regs[self.Rd] = self.Vd
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# Return the raw opcode
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return 0x9407 | (self.Rd << 4)
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def analyze_results(self):
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self.reg_changed.extend( [self.Rd, Reg.SREG] )
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# check that result is correct
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expect = ( ((self.Vd >> 1) & 0x7f) | (self.C << 7))
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got = self.anal_regs[self.Rd]
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self.fail('ROR r%02d: 0x%02x = (expect=%02x, got=%02x)' % (
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self.Rd, self.Vd, expect, got))
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# calculate what we expect sreg to be (I, T and H should be zero)
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N = ((expect & 0x80) != 0)
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expect_sreg += (N ^ V) << SREG.S
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expect_sreg += V << SREG.V
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expect_sreg += N << SREG.N
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expect_sreg += (expect == 0) << SREG.Z
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expect_sreg += C << SREG.C
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got_sreg = self.anal_regs[Reg.SREG]
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if expect_sreg != got_sreg:
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self.fail('ROR r%02d: 0x%02x -> SREG (expect=%02x, got=%02x)' % (
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self.Rd, self.Vd, expect_sreg, got_sreg))
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# Template code for test case.
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# The fail method will raise a test specific exception.
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class ROR_r%02d_v%02x_C%d_TestFail(ROR_TestFail): pass
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class test_ROR_r%02d_v%02x_C%d(base_ROR):
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raise ROR_r%02d_v%02x_C%d_TestFail, s
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# Define a list of test values such that we test all the cases of SREG bits being set.
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# automagically generate the test_ROR_rNN_vXX_rrNN_kXX class definitions.
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code += template % args
added
removed
regress/test_opcodes/test_ROR.py
