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Viewing changes to arch/arm/mach-omap2/clock24xx.h

  • Committer: Bazaar Package Importer
  • Author(s): Luke Yelavich, Luke Yelavich, Michael Casadevall, Tim Gardner, Upstream Kernel Changes
  • Date: 2009-05-06 18:18:55 UTC
  • Revision ID: james.westby@ubuntu.com-20090506181855-t00baeevpnvd9o7a
Tags: 2.6.30-1.1
[ Luke Yelavich ]
* initial release for karmic
* SAUCE: rebase-ports - adjust for the karmic ports kernel
* SAUCE: rebase-ports - also remove abi dirs/files on rebase
* Update configs after rebase against mainline Jaunty tree
* [Config] Disable CONFIG_BLK_DEV_UB and CONFIG_USB_LIBUSUAL as per
  mainline jaunty
* forward-port patch to drbd for powerpc compilation
* [Config] disable CONFIG_LENOVO_SL_LAPTOP for i386 due to FTBFS
* add .o files found in arch/powerpc/lib to all powerpc kernel header
  packages
* [Config] enable CONFIG_DRM_I915_KMS for i386 as per karmic mainline

[ Michael Casadevall ]

* Disable kgdb on sparc64
* [sparc] [Config] Disable GPIO LEDS
* [ia64] Rename -ia64-generic to -ia64 in line with other architectures
* Correct kernel image path for sparc builds
* [hppa] Fix HPPA config files to build modules for all udebian

Rebase on top of karmic mainline 2.6.30-1.1

[ Tim Gardner ]

* [Config] armel: disable staging drivers, fixes FTBS
* [Config] armel imx51: Disable CONFIG_MTD_NAND_MXC, fixes FTBS

[ Upstream Kernel Changes ]

* mpt2sas: Change reset_type enum to avoid namespace collision.
  Submitted upstream.

* Initial release after rebasing against v2.6.30-rc3

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Lines of Context:
arch/arm/mach-omap2/clock24xx.h
24
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#include "cm-regbits-24xx.h"
25
25
#include "sdrc.h"
26
26
 
27
 
static void omap2_table_mpu_recalc(struct clk *clk);
 
27
static unsigned long omap2_table_mpu_recalc(struct clk *clk);
28
28
static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
29
29
static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
30
 
static void omap2_sys_clk_recalc(struct clk *clk);
31
 
static void omap2_osc_clk_recalc(struct clk *clk);
32
 
static void omap2_sys_clk_recalc(struct clk *clk);
33
 
static void omap2_dpllcore_recalc(struct clk *clk);
34
 
static int omap2_clk_fixed_enable(struct clk *clk);
35
 
static void omap2_clk_fixed_disable(struct clk *clk);
36
 
static int omap2_enable_osc_ck(struct clk *clk);
37
 
static void omap2_disable_osc_ck(struct clk *clk);
 
30
static unsigned long omap2_sys_clk_recalc(struct clk *clk);
 
31
static unsigned long omap2_osc_clk_recalc(struct clk *clk);
 
32
static unsigned long omap2_sys_clk_recalc(struct clk *clk);
 
33
static unsigned long omap2_dpllcore_recalc(struct clk *clk);
38
34
static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
39
35
 
40
36
/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
623
619
/* Base external input clocks */
624
620
static struct clk func_32k_ck = {
625
621
        .name           = "func_32k_ck",
 
622
        .ops            = &clkops_null,
626
623
        .rate           = 32000,
627
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
628
 
                                RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 
624
        .flags          = RATE_FIXED,
629
625
        .clkdm_name     = "wkup_clkdm",
630
 
        .recalc         = &propagate_rate,
631
626
};
632
627
 
633
628
/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
634
629
static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
635
630
        .name           = "osc_ck",
636
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
637
 
                                RATE_PROPAGATES,
 
631
        .ops            = &clkops_oscck,
638
632
        .clkdm_name     = "wkup_clkdm",
639
 
        .enable         = &omap2_enable_osc_ck,
640
 
        .disable        = &omap2_disable_osc_ck,
641
633
        .recalc         = &omap2_osc_clk_recalc,
642
634
};
643
635
 
644
636
/* Without modem likely 12MHz, with modem likely 13MHz */
645
637
static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
646
638
        .name           = "sys_ck",             /* ~ ref_clk also */
 
639
        .ops            = &clkops_null,
647
640
        .parent         = &osc_ck,
648
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
649
 
                                ALWAYS_ENABLED | RATE_PROPAGATES,
650
641
        .clkdm_name     = "wkup_clkdm",
651
642
        .recalc         = &omap2_sys_clk_recalc,
652
643
};
653
644
 
654
645
static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
655
646
        .name           = "alt_ck",
 
647
        .ops            = &clkops_null,
656
648
        .rate           = 54000000,
657
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
658
 
                                RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
 
649
        .flags          = RATE_FIXED,
659
650
        .clkdm_name     = "wkup_clkdm",
660
 
        .recalc         = &propagate_rate,
661
651
};
662
652
 
663
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/*
673
663
        .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
674
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        .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
675
665
        .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 
666
        .clk_bypass             = &sys_ck,
 
667
        .clk_ref                = &sys_ck,
 
668
        .control_reg            = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 
669
        .enable_mask            = OMAP24XX_EN_DPLL_MASK,
676
670
        .max_multiplier         = 1024,
 
671
        .min_divider            = 1,
677
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        .max_divider            = 16,
678
673
        .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
679
674
};
684
679
 */
685
680
static struct clk dpll_ck = {
686
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        .name           = "dpll_ck",
 
682
        .ops            = &clkops_null,
687
683
        .parent         = &sys_ck,              /* Can be func_32k also */
688
684
        .dpll_data      = &dpll_dd,
689
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
690
 
                                RATE_PROPAGATES | ALWAYS_ENABLED,
691
685
        .clkdm_name     = "wkup_clkdm",
692
686
        .recalc         = &omap2_dpllcore_recalc,
693
687
        .set_rate       = &omap2_reprogram_dpllcore,
695
689
 
696
690
static struct clk apll96_ck = {
697
691
        .name           = "apll96_ck",
 
692
        .ops            = &clkops_fixed,
698
693
        .parent         = &sys_ck,
699
694
        .rate           = 96000000,
700
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
701
 
                                RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 
695
        .flags          = RATE_FIXED | ENABLE_ON_INIT,
702
696
        .clkdm_name     = "wkup_clkdm",
703
697
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
704
698
        .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
705
 
        .enable         = &omap2_clk_fixed_enable,
706
 
        .disable        = &omap2_clk_fixed_disable,
707
 
        .recalc         = &propagate_rate,
708
699
};
709
700
 
710
701
static struct clk apll54_ck = {
711
702
        .name           = "apll54_ck",
 
703
        .ops            = &clkops_fixed,
712
704
        .parent         = &sys_ck,
713
705
        .rate           = 54000000,
714
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
715
 
                                RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
 
706
        .flags          = RATE_FIXED | ENABLE_ON_INIT,
716
707
        .clkdm_name     = "wkup_clkdm",
717
708
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
718
709
        .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
719
 
        .enable         = &omap2_clk_fixed_enable,
720
 
        .disable        = &omap2_clk_fixed_disable,
721
 
        .recalc         = &propagate_rate,
722
710
};
723
711
 
724
712
/*
745
733
 
746
734
static struct clk func_54m_ck = {
747
735
        .name           = "func_54m_ck",
 
736
        .ops            = &clkops_null,
748
737
        .parent         = &apll54_ck,   /* can also be alt_clk */
749
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
750
 
                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
751
738
        .clkdm_name     = "wkup_clkdm",
752
739
        .init           = &omap2_init_clksel_parent,
753
740
        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
758
745
 
759
746
static struct clk core_ck = {
760
747
        .name           = "core_ck",
 
748
        .ops            = &clkops_null,
761
749
        .parent         = &dpll_ck,             /* can also be 32k */
762
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
763
 
                                ALWAYS_ENABLED | RATE_PROPAGATES,
764
750
        .clkdm_name     = "wkup_clkdm",
765
751
        .recalc         = &followparent_recalc,
766
752
};
785
771
/* The parent of this clock is not selectable on 2420. */
786
772
static struct clk func_96m_ck = {
787
773
        .name           = "func_96m_ck",
 
774
        .ops            = &clkops_null,
788
775
        .parent         = &apll96_ck,
789
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
790
 
                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
791
776
        .clkdm_name     = "wkup_clkdm",
792
777
        .init           = &omap2_init_clksel_parent,
793
778
        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
818
803
 
819
804
static struct clk func_48m_ck = {
820
805
        .name           = "func_48m_ck",
 
806
        .ops            = &clkops_null,
821
807
        .parent         = &apll96_ck,    /* 96M or Alt */
822
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
823
 
                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
824
808
        .clkdm_name     = "wkup_clkdm",
825
809
        .init           = &omap2_init_clksel_parent,
826
810
        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
833
817
 
834
818
static struct clk func_12m_ck = {
835
819
        .name           = "func_12m_ck",
 
820
        .ops            = &clkops_null,
836
821
        .parent         = &func_48m_ck,
837
822
        .fixed_div      = 4,
838
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
839
 
                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
840
823
        .clkdm_name     = "wkup_clkdm",
841
824
        .recalc         = &omap2_fixed_divisor_recalc,
842
825
};
844
827
/* Secure timer, only available in secure mode */
845
828
static struct clk wdt1_osc_ck = {
846
829
        .name           = "ck_wdt1_osc",
 
830
        .ops            = &clkops_null, /* RMK: missing? */
847
831
        .parent         = &osc_ck,
848
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
849
832
        .recalc         = &followparent_recalc,
850
833
};
851
834
 
887
870
 
888
871
static struct clk sys_clkout_src = {
889
872
        .name           = "sys_clkout_src",
 
873
        .ops            = &clkops_omap2_dflt,
890
874
        .parent         = &func_54m_ck,
891
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
892
 
                                RATE_PROPAGATES,
893
875
        .clkdm_name     = "wkup_clkdm",
894
876
        .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
895
877
        .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
918
900
 
919
901
static struct clk sys_clkout = {
920
902
        .name           = "sys_clkout",
 
903
        .ops            = &clkops_null,
921
904
        .parent         = &sys_clkout_src,
922
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
923
 
                                PARENT_CONTROLS_CLOCK,
924
905
        .clkdm_name     = "wkup_clkdm",
925
906
        .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
926
907
        .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
933
914
/* In 2430, new in 2420 ES2 */
934
915
static struct clk sys_clkout2_src = {
935
916
        .name           = "sys_clkout2_src",
 
917
        .ops            = &clkops_omap2_dflt,
936
918
        .parent         = &func_54m_ck,
937
 
        .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
938
919
        .clkdm_name     = "wkup_clkdm",
939
920
        .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
940
921
        .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
955
936
/* In 2430, new in 2420 ES2 */
956
937
static struct clk sys_clkout2 = {
957
938
        .name           = "sys_clkout2",
 
939
        .ops            = &clkops_null,
958
940
        .parent         = &sys_clkout2_src,
959
 
        .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
960
941
        .clkdm_name     = "wkup_clkdm",
961
942
        .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
962
943
        .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
968
949
 
969
950
static struct clk emul_ck = {
970
951
        .name           = "emul_ck",
 
952
        .ops            = &clkops_omap2_dflt,
971
953
        .parent         = &func_54m_ck,
972
 
        .flags          = CLOCK_IN_OMAP242X,
973
954
        .clkdm_name     = "wkup_clkdm",
974
955
        .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
975
956
        .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
1003
984
 
1004
985
static struct clk mpu_ck = {    /* Control cpu */
1005
986
        .name           = "mpu_ck",
 
987
        .ops            = &clkops_null,
1006
988
        .parent         = &core_ck,
1007
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1008
 
                                ALWAYS_ENABLED | DELAYED_APP |
1009
 
                                CONFIG_PARTICIPANT | RATE_PROPAGATES,
 
989
        .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
1010
990
        .clkdm_name     = "mpu_clkdm",
1011
991
        .init           = &omap2_init_clksel_parent,
1012
992
        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
1046
1026
 
1047
1027
static struct clk dsp_fck = {
1048
1028
        .name           = "dsp_fck",
 
1029
        .ops            = &clkops_omap2_dflt_wait,
1049
1030
        .parent         = &core_ck,
1050
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1051
 
                                CONFIG_PARTICIPANT | RATE_PROPAGATES,
 
1031
        .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
1052
1032
        .clkdm_name     = "dsp_clkdm",
1053
1033
        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1054
1034
        .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1076
1056
/* This clock does not exist as such in the TRM. */
1077
1057
static struct clk dsp_irate_ick = {
1078
1058
        .name           = "dsp_irate_ick",
 
1059
        .ops            = &clkops_null,
1079
1060
        .parent         = &dsp_fck,
1080
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1081
 
                                CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
 
1061
        .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
1082
1062
        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1083
1063
        .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
1084
1064
        .clksel         = dsp_irate_ick_clksel,
1090
1070
/* 2420 only */
1091
1071
static struct clk dsp_ick = {
1092
1072
        .name           = "dsp_ick",     /* apparently ipi and isp */
 
1073
        .ops            = &clkops_omap2_dflt_wait,
1093
1074
        .parent         = &dsp_irate_ick,
1094
 
        .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
 
1075
        .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
1095
1076
        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1096
1077
        .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
1097
1078
};
1099
1080
/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1100
1081
static struct clk iva2_1_ick = {
1101
1082
        .name           = "iva2_1_ick",
 
1083
        .ops            = &clkops_omap2_dflt_wait,
1102
1084
        .parent         = &dsp_irate_ick,
1103
 
        .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
 
1085
        .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
1104
1086
        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1105
1087
        .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1106
1088
};
1112
1094
 */
1113
1095
static struct clk iva1_ifck = {
1114
1096
        .name           = "iva1_ifck",
 
1097
        .ops            = &clkops_omap2_dflt_wait,
1115
1098
        .parent         = &core_ck,
1116
 
        .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1117
 
                                RATE_PROPAGATES | DELAYED_APP,
 
1099
        .flags          = CONFIG_PARTICIPANT | DELAYED_APP,
1118
1100
        .clkdm_name     = "iva1_clkdm",
1119
1101
        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1120
1102
        .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
1129
1111
/* IVA1 mpu/int/i/f clocks are /2 of parent */
1130
1112
static struct clk iva1_mpu_int_ifck = {
1131
1113
        .name           = "iva1_mpu_int_ifck",
 
1114
        .ops            = &clkops_omap2_dflt_wait,
1132
1115
        .parent         = &iva1_ifck,
1133
 
        .flags          = CLOCK_IN_OMAP242X,
1134
1116
        .clkdm_name     = "iva1_clkdm",
1135
1117
        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1136
1118
        .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
1175
1157
 
1176
1158
static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
1177
1159
        .name           = "core_l3_ck",
 
1160
        .ops            = &clkops_null,
1178
1161
        .parent         = &core_ck,
1179
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1180
 
                                ALWAYS_ENABLED | DELAYED_APP |
1181
 
                                CONFIG_PARTICIPANT | RATE_PROPAGATES,
 
1162
        .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
1182
1163
        .clkdm_name     = "core_l3_clkdm",
1183
1164
        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1184
1165
        .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
1204
1185
/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1205
1186
static struct clk usb_l4_ick = {        /* FS-USB interface clock */
1206
1187
        .name           = "usb_l4_ick",
 
1188
        .ops            = &clkops_omap2_dflt_wait,
1207
1189
        .parent         = &core_l3_ck,
1208
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1209
 
                                DELAYED_APP | CONFIG_PARTICIPANT,
 
1190
        .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
1210
1191
        .clkdm_name     = "core_l4_clkdm",
1211
1192
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1212
1193
        .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1238
1219
 
1239
1220
static struct clk l4_ck = {             /* used both as an ick and fck */
1240
1221
        .name           = "l4_ck",
 
1222
        .ops            = &clkops_null,
1241
1223
        .parent         = &core_l3_ck,
1242
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1243
 
                                ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
 
1224
        .flags          = DELAYED_APP,
1244
1225
        .clkdm_name     = "core_l4_clkdm",
1245
1226
        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1246
1227
        .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
1276
1257
 
1277
1258
static struct clk ssi_ssr_sst_fck = {
1278
1259
        .name           = "ssi_fck",
 
1260
        .ops            = &clkops_omap2_dflt_wait,
1279
1261
        .parent         = &core_ck,
1280
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1281
 
                                DELAYED_APP,
 
1262
        .flags          = DELAYED_APP,
1282
1263
        .clkdm_name     = "core_l3_clkdm",
1283
1264
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1284
1265
        .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1290
1271
        .set_rate       = &omap2_clksel_set_rate
1291
1272
};
1292
1273
 
 
1274
/*
 
1275
 * Presumably this is the same as SSI_ICLK.
 
1276
 * TRM contradicts itself on what clockdomain SSI_ICLK is in
 
1277
 */
 
1278
static struct clk ssi_l4_ick = {
 
1279
        .name           = "ssi_l4_ick",
 
1280
        .ops            = &clkops_omap2_dflt_wait,
 
1281
        .parent         = &l4_ck,
 
1282
        .clkdm_name     = "core_l4_clkdm",
 
1283
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 
1284
        .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
 
1285
        .recalc         = &followparent_recalc,
 
1286
};
 
1287
 
1293
1288
 
1294
1289
/*
1295
1290
 * GFX clock domain
1312
1307
 
1313
1308
static struct clk gfx_3d_fck = {
1314
1309
        .name           = "gfx_3d_fck",
 
1310
        .ops            = &clkops_omap2_dflt_wait,
1315
1311
        .parent         = &core_l3_ck,
1316
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1317
1312
        .clkdm_name     = "gfx_clkdm",
1318
1313
        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1319
1314
        .enable_bit     = OMAP24XX_EN_3D_SHIFT,
1327
1322
 
1328
1323
static struct clk gfx_2d_fck = {
1329
1324
        .name           = "gfx_2d_fck",
 
1325
        .ops            = &clkops_omap2_dflt_wait,
1330
1326
        .parent         = &core_l3_ck,
1331
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1332
1327
        .clkdm_name     = "gfx_clkdm",
1333
1328
        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1334
1329
        .enable_bit     = OMAP24XX_EN_2D_SHIFT,
1342
1337
 
1343
1338
static struct clk gfx_ick = {
1344
1339
        .name           = "gfx_ick",            /* From l3 */
 
1340
        .ops            = &clkops_omap2_dflt_wait,
1345
1341
        .parent         = &core_l3_ck,
1346
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1347
1342
        .clkdm_name     = "gfx_clkdm",
1348
1343
        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1349
1344
        .enable_bit     = OMAP_EN_GFX_SHIFT,
1372
1367
 
1373
1368
static struct clk mdm_ick = {           /* used both as a ick and fck */
1374
1369
        .name           = "mdm_ick",
 
1370
        .ops            = &clkops_omap2_dflt_wait,
1375
1371
        .parent         = &core_ck,
1376
 
        .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
 
1372
        .flags          = DELAYED_APP | CONFIG_PARTICIPANT,
1377
1373
        .clkdm_name     = "mdm_clkdm",
1378
1374
        .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1379
1375
        .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1387
1383
 
1388
1384
static struct clk mdm_osc_ck = {
1389
1385
        .name           = "mdm_osc_ck",
 
1386
        .ops            = &clkops_omap2_dflt_wait,
1390
1387
        .parent         = &osc_ck,
1391
 
        .flags          = CLOCK_IN_OMAP243X,
1392
1388
        .clkdm_name     = "mdm_clkdm",
1393
1389
        .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1394
1390
        .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1432
1428
 
1433
1429
static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
1434
1430
        .name           = "dss_ick",
 
1431
        .ops            = &clkops_omap2_dflt,
1435
1432
        .parent         = &l4_ck,       /* really both l3 and l4 */
1436
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1437
1433
        .clkdm_name     = "dss_clkdm",
1438
1434
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1439
1435
        .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1442
1438
 
1443
1439
static struct clk dss1_fck = {
1444
1440
        .name           = "dss1_fck",
 
1441
        .ops            = &clkops_omap2_dflt,
1445
1442
        .parent         = &core_ck,             /* Core or sys */
1446
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1447
 
                                DELAYED_APP,
 
1443
        .flags          = DELAYED_APP,
1448
1444
        .clkdm_name     = "dss_clkdm",
1449
1445
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1450
1446
        .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
1475
1471
 
1476
1472
static struct clk dss2_fck = {          /* Alt clk used in power management */
1477
1473
        .name           = "dss2_fck",
 
1474
        .ops            = &clkops_omap2_dflt,
1478
1475
        .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
1479
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1480
 
                                DELAYED_APP,
 
1476
        .flags          = DELAYED_APP,
1481
1477
        .clkdm_name     = "dss_clkdm",
1482
1478
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1483
1479
        .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
1490
1486
 
1491
1487
static struct clk dss_54m_fck = {       /* Alt clk used in power management */
1492
1488
        .name           = "dss_54m_fck",        /* 54m tv clk */
 
1489
        .ops            = &clkops_omap2_dflt_wait,
1493
1490
        .parent         = &func_54m_ck,
1494
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1495
1491
        .clkdm_name     = "dss_clkdm",
1496
1492
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1497
1493
        .enable_bit     = OMAP24XX_EN_TV_SHIFT,
1518
1514
 
1519
1515
static struct clk gpt1_ick = {
1520
1516
        .name           = "gpt1_ick",
 
1517
        .ops            = &clkops_omap2_dflt_wait,
1521
1518
        .parent         = &l4_ck,
1522
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1523
1519
        .clkdm_name     = "core_l4_clkdm",
1524
1520
        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1525
1521
        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1528
1524
 
1529
1525
static struct clk gpt1_fck = {
1530
1526
        .name           = "gpt1_fck",
 
1527
        .ops            = &clkops_omap2_dflt_wait,
1531
1528
        .parent         = &func_32k_ck,
1532
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1533
1529
        .clkdm_name     = "core_l4_clkdm",
1534
1530
        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1535
1531
        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
1544
1540
 
1545
1541
static struct clk gpt2_ick = {
1546
1542
        .name           = "gpt2_ick",
 
1543
        .ops            = &clkops_omap2_dflt_wait,
1547
1544
        .parent         = &l4_ck,
1548
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1549
1545
        .clkdm_name     = "core_l4_clkdm",
1550
1546
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1551
1547
        .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1554
1550
 
1555
1551
static struct clk gpt2_fck = {
1556
1552
        .name           = "gpt2_fck",
 
1553
        .ops            = &clkops_omap2_dflt_wait,
1557
1554
        .parent         = &func_32k_ck,
1558
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1559
1555
        .clkdm_name     = "core_l4_clkdm",
1560
1556
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1561
1557
        .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
1568
1564
 
1569
1565
static struct clk gpt3_ick = {
1570
1566
        .name           = "gpt3_ick",
 
1567
        .ops            = &clkops_omap2_dflt_wait,
1571
1568
        .parent         = &l4_ck,
1572
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1573
1569
        .clkdm_name     = "core_l4_clkdm",
1574
1570
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1575
1571
        .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1578
1574
 
1579
1575
static struct clk gpt3_fck = {
1580
1576
        .name           = "gpt3_fck",
 
1577
        .ops            = &clkops_omap2_dflt_wait,
1581
1578
        .parent         = &func_32k_ck,
1582
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1583
1579
        .clkdm_name     = "core_l4_clkdm",
1584
1580
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1585
1581
        .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
1592
1588
 
1593
1589
static struct clk gpt4_ick = {
1594
1590
        .name           = "gpt4_ick",
 
1591
        .ops            = &clkops_omap2_dflt_wait,
1595
1592
        .parent         = &l4_ck,
1596
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1597
1593
        .clkdm_name     = "core_l4_clkdm",
1598
1594
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1599
1595
        .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1602
1598
 
1603
1599
static struct clk gpt4_fck = {
1604
1600
        .name           = "gpt4_fck",
 
1601
        .ops            = &clkops_omap2_dflt_wait,
1605
1602
        .parent         = &func_32k_ck,
1606
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1607
1603
        .clkdm_name     = "core_l4_clkdm",
1608
1604
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1609
1605
        .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
1616
1612
 
1617
1613
static struct clk gpt5_ick = {
1618
1614
        .name           = "gpt5_ick",
 
1615
        .ops            = &clkops_omap2_dflt_wait,
1619
1616
        .parent         = &l4_ck,
1620
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1621
1617
        .clkdm_name     = "core_l4_clkdm",
1622
1618
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1623
1619
        .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1626
1622
 
1627
1623
static struct clk gpt5_fck = {
1628
1624
        .name           = "gpt5_fck",
 
1625
        .ops            = &clkops_omap2_dflt_wait,
1629
1626
        .parent         = &func_32k_ck,
1630
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1631
1627
        .clkdm_name     = "core_l4_clkdm",
1632
1628
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1633
1629
        .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
1640
1636
 
1641
1637
static struct clk gpt6_ick = {
1642
1638
        .name           = "gpt6_ick",
 
1639
        .ops            = &clkops_omap2_dflt_wait,
1643
1640
        .parent         = &l4_ck,
1644
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1645
1641
        .clkdm_name     = "core_l4_clkdm",
1646
1642
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1647
1643
        .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1650
1646
 
1651
1647
static struct clk gpt6_fck = {
1652
1648
        .name           = "gpt6_fck",
 
1649
        .ops            = &clkops_omap2_dflt_wait,
1653
1650
        .parent         = &func_32k_ck,
1654
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1655
1651
        .clkdm_name     = "core_l4_clkdm",
1656
1652
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1657
1653
        .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
1664
1660
 
1665
1661
static struct clk gpt7_ick = {
1666
1662
        .name           = "gpt7_ick",
 
1663
        .ops            = &clkops_omap2_dflt_wait,
1667
1664
        .parent         = &l4_ck,
1668
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1669
1665
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1670
1666
        .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1671
1667
        .recalc         = &followparent_recalc,
1673
1669
 
1674
1670
static struct clk gpt7_fck = {
1675
1671
        .name           = "gpt7_fck",
 
1672
        .ops            = &clkops_omap2_dflt_wait,
1676
1673
        .parent         = &func_32k_ck,
1677
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1678
1674
        .clkdm_name     = "core_l4_clkdm",
1679
1675
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1680
1676
        .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1687
1683
 
1688
1684
static struct clk gpt8_ick = {
1689
1685
        .name           = "gpt8_ick",
 
1686
        .ops            = &clkops_omap2_dflt_wait,
1690
1687
        .parent         = &l4_ck,
1691
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1692
1688
        .clkdm_name     = "core_l4_clkdm",
1693
1689
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1694
1690
        .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1697
1693
 
1698
1694
static struct clk gpt8_fck = {
1699
1695
        .name           = "gpt8_fck",
 
1696
        .ops            = &clkops_omap2_dflt_wait,
1700
1697
        .parent         = &func_32k_ck,
1701
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1702
1698
        .clkdm_name     = "core_l4_clkdm",
1703
1699
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1704
1700
        .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1711
1707
 
1712
1708
static struct clk gpt9_ick = {
1713
1709
        .name           = "gpt9_ick",
 
1710
        .ops            = &clkops_omap2_dflt_wait,
1714
1711
        .parent         = &l4_ck,
1715
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1716
1712
        .clkdm_name     = "core_l4_clkdm",
1717
1713
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1718
1714
        .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1721
1717
 
1722
1718
static struct clk gpt9_fck = {
1723
1719
        .name           = "gpt9_fck",
 
1720
        .ops            = &clkops_omap2_dflt_wait,
1724
1721
        .parent         = &func_32k_ck,
1725
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1726
1722
        .clkdm_name     = "core_l4_clkdm",
1727
1723
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1728
1724
        .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1735
1731
 
1736
1732
static struct clk gpt10_ick = {
1737
1733
        .name           = "gpt10_ick",
 
1734
        .ops            = &clkops_omap2_dflt_wait,
1738
1735
        .parent         = &l4_ck,
1739
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1740
1736
        .clkdm_name     = "core_l4_clkdm",
1741
1737
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1742
1738
        .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1745
1741
 
1746
1742
static struct clk gpt10_fck = {
1747
1743
        .name           = "gpt10_fck",
 
1744
        .ops            = &clkops_omap2_dflt_wait,
1748
1745
        .parent         = &func_32k_ck,
1749
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1750
1746
        .clkdm_name     = "core_l4_clkdm",
1751
1747
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1752
1748
        .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1759
1755
 
1760
1756
static struct clk gpt11_ick = {
1761
1757
        .name           = "gpt11_ick",
 
1758
        .ops            = &clkops_omap2_dflt_wait,
1762
1759
        .parent         = &l4_ck,
1763
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1764
1760
        .clkdm_name     = "core_l4_clkdm",
1765
1761
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1766
1762
        .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1769
1765
 
1770
1766
static struct clk gpt11_fck = {
1771
1767
        .name           = "gpt11_fck",
 
1768
        .ops            = &clkops_omap2_dflt_wait,
1772
1769
        .parent         = &func_32k_ck,
1773
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1774
1770
        .clkdm_name     = "core_l4_clkdm",
1775
1771
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1776
1772
        .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1783
1779
 
1784
1780
static struct clk gpt12_ick = {
1785
1781
        .name           = "gpt12_ick",
 
1782
        .ops            = &clkops_omap2_dflt_wait,
1786
1783
        .parent         = &l4_ck,
1787
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1788
1784
        .clkdm_name     = "core_l4_clkdm",
1789
1785
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1790
1786
        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1793
1789
 
1794
1790
static struct clk gpt12_fck = {
1795
1791
        .name           = "gpt12_fck",
 
1792
        .ops            = &clkops_omap2_dflt_wait,
1796
1793
        .parent         = &func_32k_ck,
1797
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1798
1794
        .clkdm_name     = "core_l4_clkdm",
1799
1795
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1800
1796
        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1807
1803
 
1808
1804
static struct clk mcbsp1_ick = {
1809
1805
        .name           = "mcbsp_ick",
 
1806
        .ops            = &clkops_omap2_dflt_wait,
1810
1807
        .id             = 1,
1811
1808
        .parent         = &l4_ck,
1812
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1813
1809
        .clkdm_name     = "core_l4_clkdm",
1814
1810
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1815
1811
        .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1818
1814
 
1819
1815
static struct clk mcbsp1_fck = {
1820
1816
        .name           = "mcbsp_fck",
 
1817
        .ops            = &clkops_omap2_dflt_wait,
1821
1818
        .id             = 1,
1822
1819
        .parent         = &func_96m_ck,
1823
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1824
1820
        .clkdm_name     = "core_l4_clkdm",
1825
1821
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1826
1822
        .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1829
1825
 
1830
1826
static struct clk mcbsp2_ick = {
1831
1827
        .name           = "mcbsp_ick",
 
1828
        .ops            = &clkops_omap2_dflt_wait,
1832
1829
        .id             = 2,
1833
1830
        .parent         = &l4_ck,
1834
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1835
1831
        .clkdm_name     = "core_l4_clkdm",
1836
1832
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1837
1833
        .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1840
1836
 
1841
1837
static struct clk mcbsp2_fck = {
1842
1838
        .name           = "mcbsp_fck",
 
1839
        .ops            = &clkops_omap2_dflt_wait,
1843
1840
        .id             = 2,
1844
1841
        .parent         = &func_96m_ck,
1845
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1846
1842
        .clkdm_name     = "core_l4_clkdm",
1847
1843
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1848
1844
        .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1851
1847
 
1852
1848
static struct clk mcbsp3_ick = {
1853
1849
        .name           = "mcbsp_ick",
 
1850
        .ops            = &clkops_omap2_dflt_wait,
1854
1851
        .id             = 3,
1855
1852
        .parent         = &l4_ck,
1856
 
        .flags          = CLOCK_IN_OMAP243X,
1857
1853
        .clkdm_name     = "core_l4_clkdm",
1858
1854
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1859
1855
        .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1862
1858
 
1863
1859
static struct clk mcbsp3_fck = {
1864
1860
        .name           = "mcbsp_fck",
 
1861
        .ops            = &clkops_omap2_dflt_wait,
1865
1862
        .id             = 3,
1866
1863
        .parent         = &func_96m_ck,
1867
 
        .flags          = CLOCK_IN_OMAP243X,
1868
1864
        .clkdm_name     = "core_l4_clkdm",
1869
1865
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1870
1866
        .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1873
1869
 
1874
1870
static struct clk mcbsp4_ick = {
1875
1871
        .name           = "mcbsp_ick",
 
1872
        .ops            = &clkops_omap2_dflt_wait,
1876
1873
        .id             = 4,
1877
1874
        .parent         = &l4_ck,
1878
 
        .flags          = CLOCK_IN_OMAP243X,
1879
1875
        .clkdm_name     = "core_l4_clkdm",
1880
1876
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1881
1877
        .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1884
1880
 
1885
1881
static struct clk mcbsp4_fck = {
1886
1882
        .name           = "mcbsp_fck",
 
1883
        .ops            = &clkops_omap2_dflt_wait,
1887
1884
        .id             = 4,
1888
1885
        .parent         = &func_96m_ck,
1889
 
        .flags          = CLOCK_IN_OMAP243X,
1890
1886
        .clkdm_name     = "core_l4_clkdm",
1891
1887
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1892
1888
        .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1895
1891
 
1896
1892
static struct clk mcbsp5_ick = {
1897
1893
        .name           = "mcbsp_ick",
 
1894
        .ops            = &clkops_omap2_dflt_wait,
1898
1895
        .id             = 5,
1899
1896
        .parent         = &l4_ck,
1900
 
        .flags          = CLOCK_IN_OMAP243X,
1901
1897
        .clkdm_name     = "core_l4_clkdm",
1902
1898
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1903
1899
        .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1906
1902
 
1907
1903
static struct clk mcbsp5_fck = {
1908
1904
        .name           = "mcbsp_fck",
 
1905
        .ops            = &clkops_omap2_dflt_wait,
1909
1906
        .id             = 5,
1910
1907
        .parent         = &func_96m_ck,
1911
 
        .flags          = CLOCK_IN_OMAP243X,
1912
1908
        .clkdm_name     = "core_l4_clkdm",
1913
1909
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1914
1910
        .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1917
1913
 
1918
1914
static struct clk mcspi1_ick = {
1919
1915
        .name           = "mcspi_ick",
 
1916
        .ops            = &clkops_omap2_dflt_wait,
1920
1917
        .id             = 1,
1921
1918
        .parent         = &l4_ck,
1922
1919
        .clkdm_name     = "core_l4_clkdm",
1923
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1924
1920
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1925
1921
        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1926
1922
        .recalc         = &followparent_recalc,
1928
1924
 
1929
1925
static struct clk mcspi1_fck = {
1930
1926
        .name           = "mcspi_fck",
 
1927
        .ops            = &clkops_omap2_dflt_wait,
1931
1928
        .id             = 1,
1932
1929
        .parent         = &func_48m_ck,
1933
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1934
1930
        .clkdm_name     = "core_l4_clkdm",
1935
1931
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1936
1932
        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1939
1935
 
1940
1936
static struct clk mcspi2_ick = {
1941
1937
        .name           = "mcspi_ick",
 
1938
        .ops            = &clkops_omap2_dflt_wait,
1942
1939
        .id             = 2,
1943
1940
        .parent         = &l4_ck,
1944
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1945
1941
        .clkdm_name     = "core_l4_clkdm",
1946
1942
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1947
1943
        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1950
1946
 
1951
1947
static struct clk mcspi2_fck = {
1952
1948
        .name           = "mcspi_fck",
 
1949
        .ops            = &clkops_omap2_dflt_wait,
1953
1950
        .id             = 2,
1954
1951
        .parent         = &func_48m_ck,
1955
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1956
1952
        .clkdm_name     = "core_l4_clkdm",
1957
1953
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1958
1954
        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1961
1957
 
1962
1958
static struct clk mcspi3_ick = {
1963
1959
        .name           = "mcspi_ick",
 
1960
        .ops            = &clkops_omap2_dflt_wait,
1964
1961
        .id             = 3,
1965
1962
        .parent         = &l4_ck,
1966
 
        .flags          = CLOCK_IN_OMAP243X,
1967
1963
        .clkdm_name     = "core_l4_clkdm",
1968
1964
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1969
1965
        .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1972
1968
 
1973
1969
static struct clk mcspi3_fck = {
1974
1970
        .name           = "mcspi_fck",
 
1971
        .ops            = &clkops_omap2_dflt_wait,
1975
1972
        .id             = 3,
1976
1973
        .parent         = &func_48m_ck,
1977
 
        .flags          = CLOCK_IN_OMAP243X,
1978
1974
        .clkdm_name     = "core_l4_clkdm",
1979
1975
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1980
1976
        .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1983
1979
 
1984
1980
static struct clk uart1_ick = {
1985
1981
        .name           = "uart1_ick",
 
1982
        .ops            = &clkops_omap2_dflt_wait,
1986
1983
        .parent         = &l4_ck,
1987
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1988
1984
        .clkdm_name     = "core_l4_clkdm",
1989
1985
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1990
1986
        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1993
1989
 
1994
1990
static struct clk uart1_fck = {
1995
1991
        .name           = "uart1_fck",
 
1992
        .ops            = &clkops_omap2_dflt_wait,
1996
1993
        .parent         = &func_48m_ck,
1997
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1998
1994
        .clkdm_name     = "core_l4_clkdm",
1999
1995
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2000
1996
        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
2003
1999
 
2004
2000
static struct clk uart2_ick = {
2005
2001
        .name           = "uart2_ick",
 
2002
        .ops            = &clkops_omap2_dflt_wait,
2006
2003
        .parent         = &l4_ck,
2007
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2008
2004
        .clkdm_name     = "core_l4_clkdm",
2009
2005
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2010
2006
        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2013
2009
 
2014
2010
static struct clk uart2_fck = {
2015
2011
        .name           = "uart2_fck",
 
2012
        .ops            = &clkops_omap2_dflt_wait,
2016
2013
        .parent         = &func_48m_ck,
2017
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2018
2014
        .clkdm_name     = "core_l4_clkdm",
2019
2015
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2020
2016
        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
2023
2019
 
2024
2020
static struct clk uart3_ick = {
2025
2021
        .name           = "uart3_ick",
 
2022
        .ops            = &clkops_omap2_dflt_wait,
2026
2023
        .parent         = &l4_ck,
2027
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2028
2024
        .clkdm_name     = "core_l4_clkdm",
2029
2025
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2030
2026
        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2033
2029
 
2034
2030
static struct clk uart3_fck = {
2035
2031
        .name           = "uart3_fck",
 
2032
        .ops            = &clkops_omap2_dflt_wait,
2036
2033
        .parent         = &func_48m_ck,
2037
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2038
2034
        .clkdm_name     = "core_l4_clkdm",
2039
2035
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2040
2036
        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
2043
2039
 
2044
2040
static struct clk gpios_ick = {
2045
2041
        .name           = "gpios_ick",
 
2042
        .ops            = &clkops_omap2_dflt_wait,
2046
2043
        .parent         = &l4_ck,
2047
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2048
2044
        .clkdm_name     = "core_l4_clkdm",
2049
2045
        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2050
2046
        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2053
2049
 
2054
2050
static struct clk gpios_fck = {
2055
2051
        .name           = "gpios_fck",
 
2052
        .ops            = &clkops_omap2_dflt_wait,
2056
2053
        .parent         = &func_32k_ck,
2057
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2058
2054
        .clkdm_name     = "wkup_clkdm",
2059
2055
        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2060
2056
        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
2063
2059
 
2064
2060
static struct clk mpu_wdt_ick = {
2065
2061
        .name           = "mpu_wdt_ick",
 
2062
        .ops            = &clkops_omap2_dflt_wait,
2066
2063
        .parent         = &l4_ck,
2067
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2068
2064
        .clkdm_name     = "core_l4_clkdm",
2069
2065
        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2070
2066
        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2073
2069
 
2074
2070
static struct clk mpu_wdt_fck = {
2075
2071
        .name           = "mpu_wdt_fck",
 
2072
        .ops            = &clkops_omap2_dflt_wait,
2076
2073
        .parent         = &func_32k_ck,
2077
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2078
2074
        .clkdm_name     = "wkup_clkdm",
2079
2075
        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2080
2076
        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
2083
2079
 
2084
2080
static struct clk sync_32k_ick = {
2085
2081
        .name           = "sync_32k_ick",
 
2082
        .ops            = &clkops_omap2_dflt_wait,
2086
2083
        .parent         = &l4_ck,
2087
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2088
 
                                ENABLE_ON_INIT,
 
2084
        .flags          = ENABLE_ON_INIT,
2089
2085
        .clkdm_name     = "core_l4_clkdm",
2090
2086
        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2091
2087
        .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
2094
2090
 
2095
2091
static struct clk wdt1_ick = {
2096
2092
        .name           = "wdt1_ick",
 
2093
        .ops            = &clkops_omap2_dflt_wait,
2097
2094
        .parent         = &l4_ck,
2098
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2099
2095
        .clkdm_name     = "core_l4_clkdm",
2100
2096
        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2101
2097
        .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
2104
2100
 
2105
2101
static struct clk omapctrl_ick = {
2106
2102
        .name           = "omapctrl_ick",
 
2103
        .ops            = &clkops_omap2_dflt_wait,
2107
2104
        .parent         = &l4_ck,
2108
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2109
 
                                ENABLE_ON_INIT,
 
2105
        .flags          = ENABLE_ON_INIT,
2110
2106
        .clkdm_name     = "core_l4_clkdm",
2111
2107
        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2112
2108
        .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
2115
2111
 
2116
2112
static struct clk icr_ick = {
2117
2113
        .name           = "icr_ick",
 
2114
        .ops            = &clkops_omap2_dflt_wait,
2118
2115
        .parent         = &l4_ck,
2119
 
        .flags          = CLOCK_IN_OMAP243X,
2120
2116
        .clkdm_name     = "core_l4_clkdm",
2121
2117
        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2122
2118
        .enable_bit     = OMAP2430_EN_ICR_SHIFT,
2125
2121
 
2126
2122
static struct clk cam_ick = {
2127
2123
        .name           = "cam_ick",
 
2124
        .ops            = &clkops_omap2_dflt,
2128
2125
        .parent         = &l4_ck,
2129
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2130
2126
        .clkdm_name     = "core_l4_clkdm",
2131
2127
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2132
2128
        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2140
2136
 */
2141
2137
static struct clk cam_fck = {
2142
2138
        .name           = "cam_fck",
 
2139
        .ops            = &clkops_omap2_dflt,
2143
2140
        .parent         = &func_96m_ck,
2144
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2145
2141
        .clkdm_name     = "core_l3_clkdm",
2146
2142
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2147
2143
        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
2150
2146
 
2151
2147
static struct clk mailboxes_ick = {
2152
2148
        .name           = "mailboxes_ick",
 
2149
        .ops            = &clkops_omap2_dflt_wait,
2153
2150
        .parent         = &l4_ck,
2154
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2155
2151
        .clkdm_name     = "core_l4_clkdm",
2156
2152
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2157
2153
        .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
2160
2156
 
2161
2157
static struct clk wdt4_ick = {
2162
2158
        .name           = "wdt4_ick",
 
2159
        .ops            = &clkops_omap2_dflt_wait,
2163
2160
        .parent         = &l4_ck,
2164
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2165
2161
        .clkdm_name     = "core_l4_clkdm",
2166
2162
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2167
2163
        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2170
2166
 
2171
2167
static struct clk wdt4_fck = {
2172
2168
        .name           = "wdt4_fck",
 
2169
        .ops            = &clkops_omap2_dflt_wait,
2173
2170
        .parent         = &func_32k_ck,
2174
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2175
2171
        .clkdm_name     = "core_l4_clkdm",
2176
2172
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2177
2173
        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
2180
2176
 
2181
2177
static struct clk wdt3_ick = {
2182
2178
        .name           = "wdt3_ick",
 
2179
        .ops            = &clkops_omap2_dflt_wait,
2183
2180
        .parent         = &l4_ck,
2184
 
        .flags          = CLOCK_IN_OMAP242X,
2185
2181
        .clkdm_name     = "core_l4_clkdm",
2186
2182
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2187
2183
        .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2190
2186
 
2191
2187
static struct clk wdt3_fck = {
2192
2188
        .name           = "wdt3_fck",
 
2189
        .ops            = &clkops_omap2_dflt_wait,
2193
2190
        .parent         = &func_32k_ck,
2194
 
        .flags          = CLOCK_IN_OMAP242X,
2195
2191
        .clkdm_name     = "core_l4_clkdm",
2196
2192
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2197
2193
        .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
2200
2196
 
2201
2197
static struct clk mspro_ick = {
2202
2198
        .name           = "mspro_ick",
 
2199
        .ops            = &clkops_omap2_dflt_wait,
2203
2200
        .parent         = &l4_ck,
2204
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2205
2201
        .clkdm_name     = "core_l4_clkdm",
2206
2202
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2207
2203
        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2210
2206
 
2211
2207
static struct clk mspro_fck = {
2212
2208
        .name           = "mspro_fck",
 
2209
        .ops            = &clkops_omap2_dflt_wait,
2213
2210
        .parent         = &func_96m_ck,
2214
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2215
2211
        .clkdm_name     = "core_l4_clkdm",
2216
2212
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2217
2213
        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
2220
2216
 
2221
2217
static struct clk mmc_ick = {
2222
2218
        .name           = "mmc_ick",
 
2219
        .ops            = &clkops_omap2_dflt_wait,
2223
2220
        .parent         = &l4_ck,
2224
 
        .flags          = CLOCK_IN_OMAP242X,
2225
2221
        .clkdm_name     = "core_l4_clkdm",
2226
2222
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2227
2223
        .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2230
2226
 
2231
2227
static struct clk mmc_fck = {
2232
2228
        .name           = "mmc_fck",
 
2229
        .ops            = &clkops_omap2_dflt_wait,
2233
2230
        .parent         = &func_96m_ck,
2234
 
        .flags          = CLOCK_IN_OMAP242X,
2235
2231
        .clkdm_name     = "core_l4_clkdm",
2236
2232
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2237
2233
        .enable_bit     = OMAP2420_EN_MMC_SHIFT,
2240
2236
 
2241
2237
static struct clk fac_ick = {
2242
2238
        .name           = "fac_ick",
 
2239
        .ops            = &clkops_omap2_dflt_wait,
2243
2240
        .parent         = &l4_ck,
2244
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2245
2241
        .clkdm_name     = "core_l4_clkdm",
2246
2242
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2247
2243
        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2250
2246
 
2251
2247
static struct clk fac_fck = {
2252
2248
        .name           = "fac_fck",
 
2249
        .ops            = &clkops_omap2_dflt_wait,
2253
2250
        .parent         = &func_12m_ck,
2254
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2255
2251
        .clkdm_name     = "core_l4_clkdm",
2256
2252
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2257
2253
        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
2260
2256
 
2261
2257
static struct clk eac_ick = {
2262
2258
        .name           = "eac_ick",
 
2259
        .ops            = &clkops_omap2_dflt_wait,
2263
2260
        .parent         = &l4_ck,
2264
 
        .flags          = CLOCK_IN_OMAP242X,
2265
2261
        .clkdm_name     = "core_l4_clkdm",
2266
2262
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2267
2263
        .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2270
2266
 
2271
2267
static struct clk eac_fck = {
2272
2268
        .name           = "eac_fck",
 
2269
        .ops            = &clkops_omap2_dflt_wait,
2273
2270
        .parent         = &func_96m_ck,
2274
 
        .flags          = CLOCK_IN_OMAP242X,
2275
2271
        .clkdm_name     = "core_l4_clkdm",
2276
2272
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2277
2273
        .enable_bit     = OMAP2420_EN_EAC_SHIFT,
2280
2276
 
2281
2277
static struct clk hdq_ick = {
2282
2278
        .name           = "hdq_ick",
 
2279
        .ops            = &clkops_omap2_dflt_wait,
2283
2280
        .parent         = &l4_ck,
2284
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2285
2281
        .clkdm_name     = "core_l4_clkdm",
2286
2282
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2287
2283
        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2290
2286
 
2291
2287
static struct clk hdq_fck = {
2292
2288
        .name           = "hdq_fck",
 
2289
        .ops            = &clkops_omap2_dflt_wait,
2293
2290
        .parent         = &func_12m_ck,
2294
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2295
2291
        .clkdm_name     = "core_l4_clkdm",
2296
2292
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2297
2293
        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
2300
2296
 
2301
2297
static struct clk i2c2_ick = {
2302
2298
        .name           = "i2c_ick",
 
2299
        .ops            = &clkops_omap2_dflt_wait,
2303
2300
        .id             = 2,
2304
2301
        .parent         = &l4_ck,
2305
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2306
2302
        .clkdm_name     = "core_l4_clkdm",
2307
2303
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2308
2304
        .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2311
2307
 
2312
2308
static struct clk i2c2_fck = {
2313
2309
        .name           = "i2c_fck",
 
2310
        .ops            = &clkops_omap2_dflt_wait,
2314
2311
        .id             = 2,
2315
2312
        .parent         = &func_12m_ck,
2316
 
        .flags          = CLOCK_IN_OMAP242X,
2317
2313
        .clkdm_name     = "core_l4_clkdm",
2318
2314
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2319
2315
        .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
2321
2317
};
2322
2318
 
2323
2319
static struct clk i2chs2_fck = {
2324
 
        .name           = "i2chs_fck",
 
2320
        .name           = "i2c_fck",
 
2321
        .ops            = &clkops_omap2_dflt_wait,
2325
2322
        .id             = 2,
2326
2323
        .parent         = &func_96m_ck,
2327
 
        .flags          = CLOCK_IN_OMAP243X,
2328
2324
        .clkdm_name     = "core_l4_clkdm",
2329
2325
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2330
2326
        .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
2333
2329
 
2334
2330
static struct clk i2c1_ick = {
2335
2331
        .name           = "i2c_ick",
 
2332
        .ops            = &clkops_omap2_dflt_wait,
2336
2333
        .id             = 1,
2337
2334
        .parent         = &l4_ck,
2338
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2339
2335
        .clkdm_name     = "core_l4_clkdm",
2340
2336
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2341
2337
        .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2344
2340
 
2345
2341
static struct clk i2c1_fck = {
2346
2342
        .name           = "i2c_fck",
 
2343
        .ops            = &clkops_omap2_dflt_wait,
2347
2344
        .id             = 1,
2348
2345
        .parent         = &func_12m_ck,
2349
 
        .flags          = CLOCK_IN_OMAP242X,
2350
2346
        .clkdm_name     = "core_l4_clkdm",
2351
2347
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2352
2348
        .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
2354
2350
};
2355
2351
 
2356
2352
static struct clk i2chs1_fck = {
2357
 
        .name           = "i2chs_fck",
 
2353
        .name           = "i2c_fck",
 
2354
        .ops            = &clkops_omap2_dflt_wait,
2358
2355
        .id             = 1,
2359
2356
        .parent         = &func_96m_ck,
2360
 
        .flags          = CLOCK_IN_OMAP243X,
2361
2357
        .clkdm_name     = "core_l4_clkdm",
2362
2358
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2363
2359
        .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
2366
2362
 
2367
2363
static struct clk gpmc_fck = {
2368
2364
        .name           = "gpmc_fck",
 
2365
        .ops            = &clkops_null, /* RMK: missing? */
2369
2366
        .parent         = &core_l3_ck,
2370
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2371
 
                                ENABLE_ON_INIT,
 
2367
        .flags          = ENABLE_ON_INIT,
2372
2368
        .clkdm_name     = "core_l3_clkdm",
2373
2369
        .recalc         = &followparent_recalc,
2374
2370
};
2375
2371
 
2376
2372
static struct clk sdma_fck = {
2377
2373
        .name           = "sdma_fck",
 
2374
        .ops            = &clkops_null, /* RMK: missing? */
2378
2375
        .parent         = &core_l3_ck,
2379
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2380
2376
        .clkdm_name     = "core_l3_clkdm",
2381
2377
        .recalc         = &followparent_recalc,
2382
2378
};
2383
2379
 
2384
2380
static struct clk sdma_ick = {
2385
2381
        .name           = "sdma_ick",
 
2382
        .ops            = &clkops_null, /* RMK: missing? */
2386
2383
        .parent         = &l4_ck,
2387
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2388
2384
        .clkdm_name     = "core_l3_clkdm",
2389
2385
        .recalc         = &followparent_recalc,
2390
2386
};
2391
2387
 
2392
2388
static struct clk vlynq_ick = {
2393
2389
        .name           = "vlynq_ick",
 
2390
        .ops            = &clkops_omap2_dflt_wait,
2394
2391
        .parent         = &core_l3_ck,
2395
 
        .flags          = CLOCK_IN_OMAP242X,
2396
2392
        .clkdm_name     = "core_l3_clkdm",
2397
2393
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2398
2394
        .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2426
2422
 
2427
2423
static struct clk vlynq_fck = {
2428
2424
        .name           = "vlynq_fck",
 
2425
        .ops            = &clkops_omap2_dflt_wait,
2429
2426
        .parent         = &func_96m_ck,
2430
 
        .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
 
2427
        .flags          = DELAYED_APP,
2431
2428
        .clkdm_name     = "core_l3_clkdm",
2432
2429
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2433
2430
        .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
2442
2439
 
2443
2440
static struct clk sdrc_ick = {
2444
2441
        .name           = "sdrc_ick",
 
2442
        .ops            = &clkops_omap2_dflt_wait,
2445
2443
        .parent         = &l4_ck,
2446
 
        .flags          = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
 
2444
        .flags          = ENABLE_ON_INIT,
2447
2445
        .clkdm_name     = "core_l4_clkdm",
2448
2446
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2449
2447
        .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
2452
2450
 
2453
2451
static struct clk des_ick = {
2454
2452
        .name           = "des_ick",
 
2453
        .ops            = &clkops_omap2_dflt_wait,
2455
2454
        .parent         = &l4_ck,
2456
 
        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2457
2455
        .clkdm_name     = "core_l4_clkdm",
2458
2456
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2459
2457
        .enable_bit     = OMAP24XX_EN_DES_SHIFT,
2462
2460
 
2463
2461
static struct clk sha_ick = {
2464
2462
        .name           = "sha_ick",
 
2463
        .ops            = &clkops_omap2_dflt_wait,
2465
2464
        .parent         = &l4_ck,
2466
 
        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2467
2465
        .clkdm_name     = "core_l4_clkdm",
2468
2466
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2469
2467
        .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
2472
2470
 
2473
2471
static struct clk rng_ick = {
2474
2472
        .name           = "rng_ick",
 
2473
        .ops            = &clkops_omap2_dflt_wait,
2475
2474
        .parent         = &l4_ck,
2476
 
        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2477
2475
        .clkdm_name     = "core_l4_clkdm",
2478
2476
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2479
2477
        .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
2482
2480
 
2483
2481
static struct clk aes_ick = {
2484
2482
        .name           = "aes_ick",
 
2483
        .ops            = &clkops_omap2_dflt_wait,
2485
2484
        .parent         = &l4_ck,
2486
 
        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2487
2485
        .clkdm_name     = "core_l4_clkdm",
2488
2486
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2489
2487
        .enable_bit     = OMAP24XX_EN_AES_SHIFT,
2492
2490
 
2493
2491
static struct clk pka_ick = {
2494
2492
        .name           = "pka_ick",
 
2493
        .ops            = &clkops_omap2_dflt_wait,
2495
2494
        .parent         = &l4_ck,
2496
 
        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2497
2495
        .clkdm_name     = "core_l4_clkdm",
2498
2496
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2499
2497
        .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
2502
2500
 
2503
2501
static struct clk usb_fck = {
2504
2502
        .name           = "usb_fck",
 
2503
        .ops            = &clkops_omap2_dflt_wait,
2505
2504
        .parent         = &func_48m_ck,
2506
 
        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2507
2505
        .clkdm_name     = "core_l3_clkdm",
2508
2506
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2509
2507
        .enable_bit     = OMAP24XX_EN_USB_SHIFT,
2512
2510
 
2513
2511
static struct clk usbhs_ick = {
2514
2512
        .name           = "usbhs_ick",
 
2513
        .ops            = &clkops_omap2_dflt_wait,
2515
2514
        .parent         = &core_l3_ck,
2516
 
        .flags          = CLOCK_IN_OMAP243X,
2517
2515
        .clkdm_name     = "core_l3_clkdm",
2518
2516
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2519
2517
        .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
2522
2520
 
2523
2521
static struct clk mmchs1_ick = {
2524
2522
        .name           = "mmchs_ick",
2525
 
        .id             = 1,
 
2523
        .ops            = &clkops_omap2_dflt_wait,
2526
2524
        .parent         = &l4_ck,
2527
 
        .flags          = CLOCK_IN_OMAP243X,
2528
2525
        .clkdm_name     = "core_l4_clkdm",
2529
2526
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2530
2527
        .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2533
2530
 
2534
2531
static struct clk mmchs1_fck = {
2535
2532
        .name           = "mmchs_fck",
2536
 
        .id             = 1,
 
2533
        .ops            = &clkops_omap2_dflt_wait,
2537
2534
        .parent         = &func_96m_ck,
2538
 
        .flags          = CLOCK_IN_OMAP243X,
2539
2535
        .clkdm_name     = "core_l3_clkdm",
2540
2536
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2541
2537
        .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
2544
2540
 
2545
2541
static struct clk mmchs2_ick = {
2546
2542
        .name           = "mmchs_ick",
2547
 
        .id             = 2,
 
2543
        .ops            = &clkops_omap2_dflt_wait,
 
2544
        .id             = 1,
2548
2545
        .parent         = &l4_ck,
2549
 
        .flags          = CLOCK_IN_OMAP243X,
2550
2546
        .clkdm_name     = "core_l4_clkdm",
2551
2547
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2552
2548
        .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2555
2551
 
2556
2552
static struct clk mmchs2_fck = {
2557
2553
        .name           = "mmchs_fck",
2558
 
        .id             = 2,
 
2554
        .ops            = &clkops_omap2_dflt_wait,
 
2555
        .id             = 1,
2559
2556
        .parent         = &func_96m_ck,
2560
 
        .flags          = CLOCK_IN_OMAP243X,
2561
2557
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2562
2558
        .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
2563
2559
        .recalc         = &followparent_recalc,
2565
2561
 
2566
2562
static struct clk gpio5_ick = {
2567
2563
        .name           = "gpio5_ick",
 
2564
        .ops            = &clkops_omap2_dflt_wait,
2568
2565
        .parent         = &l4_ck,
2569
 
        .flags          = CLOCK_IN_OMAP243X,
2570
2566
        .clkdm_name     = "core_l4_clkdm",
2571
2567
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2572
2568
        .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2575
2571
 
2576
2572
static struct clk gpio5_fck = {
2577
2573
        .name           = "gpio5_fck",
 
2574
        .ops            = &clkops_omap2_dflt_wait,
2578
2575
        .parent         = &func_32k_ck,
2579
 
        .flags          = CLOCK_IN_OMAP243X,
2580
2576
        .clkdm_name     = "core_l4_clkdm",
2581
2577
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2582
2578
        .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
2585
2581
 
2586
2582
static struct clk mdm_intc_ick = {
2587
2583
        .name           = "mdm_intc_ick",
 
2584
        .ops            = &clkops_omap2_dflt_wait,
2588
2585
        .parent         = &l4_ck,
2589
 
        .flags          = CLOCK_IN_OMAP243X,
2590
2586
        .clkdm_name     = "core_l4_clkdm",
2591
2587
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2592
2588
        .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
2595
2591
 
2596
2592
static struct clk mmchsdb1_fck = {
2597
2593
        .name           = "mmchsdb_fck",
2598
 
        .id             = 1,
 
2594
        .ops            = &clkops_omap2_dflt_wait,
2599
2595
        .parent         = &func_32k_ck,
2600
 
        .flags          = CLOCK_IN_OMAP243X,
2601
2596
        .clkdm_name     = "core_l4_clkdm",
2602
2597
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2603
2598
        .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
2606
2601
 
2607
2602
static struct clk mmchsdb2_fck = {
2608
2603
        .name           = "mmchsdb_fck",
2609
 
        .id             = 2,
 
2604
        .ops            = &clkops_omap2_dflt_wait,
 
2605
        .id             = 1,
2610
2606
        .parent         = &func_32k_ck,
2611
 
        .flags          = CLOCK_IN_OMAP243X,
2612
2607
        .clkdm_name     = "core_l4_clkdm",
2613
2608
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2614
2609
        .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
2631
2626
 */
2632
2627
static struct clk virt_prcm_set = {
2633
2628
        .name           = "virt_prcm_set",
2634
 
        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2635
 
                                VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
 
2629
        .ops            = &clkops_null,
 
2630
        .flags          = DELAYED_APP,
2636
2631
        .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
2637
2632
        .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
2638
2633
        .set_rate       = &omap2_select_table_rate,
2639
2634
        .round_rate     = &omap2_round_to_table_rate,
2640
2635
};
2641
2636
 
2642
 
static struct clk *onchip_24xx_clks[] __initdata = {
2643
 
        /* external root sources */
2644
 
        &func_32k_ck,
2645
 
        &osc_ck,
2646
 
        &sys_ck,
2647
 
        &alt_ck,
2648
 
        /* internal analog sources */
2649
 
        &dpll_ck,
2650
 
        &apll96_ck,
2651
 
        &apll54_ck,
2652
 
        /* internal prcm root sources */
2653
 
        &func_54m_ck,
2654
 
        &core_ck,
2655
 
        &func_96m_ck,
2656
 
        &func_48m_ck,
2657
 
        &func_12m_ck,
2658
 
        &wdt1_osc_ck,
2659
 
        &sys_clkout_src,
2660
 
        &sys_clkout,
2661
 
        &sys_clkout2_src,
2662
 
        &sys_clkout2,
2663
 
        &emul_ck,
2664
 
        /* mpu domain clocks */
2665
 
        &mpu_ck,
2666
 
        /* dsp domain clocks */
2667
 
        &dsp_fck,
2668
 
        &dsp_irate_ick,
2669
 
        &dsp_ick,               /* 242x */
2670
 
        &iva2_1_ick,            /* 243x */
2671
 
        &iva1_ifck,             /* 242x */
2672
 
        &iva1_mpu_int_ifck,     /* 242x */
2673
 
        /* GFX domain clocks */
2674
 
        &gfx_3d_fck,
2675
 
        &gfx_2d_fck,
2676
 
        &gfx_ick,
2677
 
        /* Modem domain clocks */
2678
 
        &mdm_ick,
2679
 
        &mdm_osc_ck,
2680
 
        /* DSS domain clocks */
2681
 
        &dss_ick,
2682
 
        &dss1_fck,
2683
 
        &dss2_fck,
2684
 
        &dss_54m_fck,
2685
 
        /* L3 domain clocks */
2686
 
        &core_l3_ck,
2687
 
        &ssi_ssr_sst_fck,
2688
 
        &usb_l4_ick,
2689
 
        /* L4 domain clocks */
2690
 
        &l4_ck,                 /* used as both core_l4 and wu_l4 */
2691
 
        /* virtual meta-group clock */
2692
 
        &virt_prcm_set,
2693
 
        /* general l4 interface ck, multi-parent functional clk */
2694
 
        &gpt1_ick,
2695
 
        &gpt1_fck,
2696
 
        &gpt2_ick,
2697
 
        &gpt2_fck,
2698
 
        &gpt3_ick,
2699
 
        &gpt3_fck,
2700
 
        &gpt4_ick,
2701
 
        &gpt4_fck,
2702
 
        &gpt5_ick,
2703
 
        &gpt5_fck,
2704
 
        &gpt6_ick,
2705
 
        &gpt6_fck,
2706
 
        &gpt7_ick,
2707
 
        &gpt7_fck,
2708
 
        &gpt8_ick,
2709
 
        &gpt8_fck,
2710
 
        &gpt9_ick,
2711
 
        &gpt9_fck,
2712
 
        &gpt10_ick,
2713
 
        &gpt10_fck,
2714
 
        &gpt11_ick,
2715
 
        &gpt11_fck,
2716
 
        &gpt12_ick,
2717
 
        &gpt12_fck,
2718
 
        &mcbsp1_ick,
2719
 
        &mcbsp1_fck,
2720
 
        &mcbsp2_ick,
2721
 
        &mcbsp2_fck,
2722
 
        &mcbsp3_ick,
2723
 
        &mcbsp3_fck,
2724
 
        &mcbsp4_ick,
2725
 
        &mcbsp4_fck,
2726
 
        &mcbsp5_ick,
2727
 
        &mcbsp5_fck,
2728
 
        &mcspi1_ick,
2729
 
        &mcspi1_fck,
2730
 
        &mcspi2_ick,
2731
 
        &mcspi2_fck,
2732
 
        &mcspi3_ick,
2733
 
        &mcspi3_fck,
2734
 
        &uart1_ick,
2735
 
        &uart1_fck,
2736
 
        &uart2_ick,
2737
 
        &uart2_fck,
2738
 
        &uart3_ick,
2739
 
        &uart3_fck,
2740
 
        &gpios_ick,
2741
 
        &gpios_fck,
2742
 
        &mpu_wdt_ick,
2743
 
        &mpu_wdt_fck,
2744
 
        &sync_32k_ick,
2745
 
        &wdt1_ick,
2746
 
        &omapctrl_ick,
2747
 
        &icr_ick,
2748
 
        &cam_fck,
2749
 
        &cam_ick,
2750
 
        &mailboxes_ick,
2751
 
        &wdt4_ick,
2752
 
        &wdt4_fck,
2753
 
        &wdt3_ick,
2754
 
        &wdt3_fck,
2755
 
        &mspro_ick,
2756
 
        &mspro_fck,
2757
 
        &mmc_ick,
2758
 
        &mmc_fck,
2759
 
        &fac_ick,
2760
 
        &fac_fck,
2761
 
        &eac_ick,
2762
 
        &eac_fck,
2763
 
        &hdq_ick,
2764
 
        &hdq_fck,
2765
 
        &i2c1_ick,
2766
 
        &i2c1_fck,
2767
 
        &i2chs1_fck,
2768
 
        &i2c2_ick,
2769
 
        &i2c2_fck,
2770
 
        &i2chs2_fck,
2771
 
        &gpmc_fck,
2772
 
        &sdma_fck,
2773
 
        &sdma_ick,
2774
 
        &vlynq_ick,
2775
 
        &vlynq_fck,
2776
 
        &sdrc_ick,
2777
 
        &des_ick,
2778
 
        &sha_ick,
2779
 
        &rng_ick,
2780
 
        &aes_ick,
2781
 
        &pka_ick,
2782
 
        &usb_fck,
2783
 
        &usbhs_ick,
2784
 
        &mmchs1_ick,
2785
 
        &mmchs1_fck,
2786
 
        &mmchs2_ick,
2787
 
        &mmchs2_fck,
2788
 
        &gpio5_ick,
2789
 
        &gpio5_fck,
2790
 
        &mdm_intc_ick,
2791
 
        &mmchsdb1_fck,
2792
 
        &mmchsdb2_fck,
2793
 
};
2794
 
 
2795
2637
#endif
2796
2638