12
10
static int enable_pid_filtering = 1;
13
11
module_param(enable_pid_filtering, int, 0444);
14
MODULE_PARM_DESC(enable_pid_filtering, "enable hardware pid filtering: supported values: 0 (fullts), 1");
12
MODULE_PARM_DESC(enable_pid_filtering,
13
"enable hardware pid filtering: supported values: 0 (fullts), 1");
16
static int irq_chk_intv;
15
static int irq_chk_intv = 100;
17
16
module_param(irq_chk_intv, int, 0644);
18
MODULE_PARM_DESC(irq_chk_intv, "set the interval for IRQ watchdog (currently just debugging).");
17
MODULE_PARM_DESC(irq_chk_intv, "set the interval for IRQ streaming watchdog.");
20
19
#ifdef CONFIG_DVB_B2C2_FLEXCOP_DEBUG
21
20
#define dprintk(level,args...) \
26
25
#define DEBSTATUS " (debugging is not enabled)"
29
#define deb_info(args...) dprintk(0x01,args)
30
#define deb_reg(args...) dprintk(0x02,args)
31
#define deb_ts(args...) dprintk(0x04,args)
32
#define deb_irq(args...) dprintk(0x08,args)
33
#define deb_chk(args...) dprintk(0x10,args)
28
#define deb_info(args...) dprintk(0x01, args)
29
#define deb_reg(args...) dprintk(0x02, args)
30
#define deb_ts(args...) dprintk(0x04, args)
31
#define deb_irq(args...) dprintk(0x08, args)
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#define deb_chk(args...) dprintk(0x10, args)
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35
module_param(debug, int, 0644);
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MODULE_PARM_DESC(debug, "set debug level (1=info,2=regs,4=TS,8=irqdma (|-able))." DEBSTATUS);
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MODULE_PARM_DESC(debug,
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"set debug level (1=info,2=regs,4=TS,8=irqdma,16=check (|-able))."
39
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#define DRIVER_VERSION "0.1"
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#define DRIVER_NAME "Technisat/B2C2 FlexCop II/IIb/III Digital TV PCI Driver"
50
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void __iomem *io_mem;
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/* buffersize (at least for DMA1, need to be % 188 == 0,
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* this logic is required */
53
/* buffersize (at least for DMA1, need to be % 188 == 0,
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* this logic is required */
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#define FC_DEFAULT_DMA1_BUFSIZE (1280 * 188)
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#define FC_DEFAULT_DMA2_BUFSIZE (10 * 188)
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struct flexcop_dma dma[2];
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int active_dma1_addr; /* 0 = addr0 of dma1; 1 = addr1 of dma1 */
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u32 last_dma1_cur_pos; /* position of the pointer last time the timer/packet irq occured */
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u32 last_dma1_cur_pos;
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/* position of the pointer last time the timer/packet irq occured */
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66
spinlock_t irq_lock;
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67
unsigned long last_irq;
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struct delayed_work irq_check_work;
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struct flexcop_device *fc_dev;
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static int lastwreg,lastwval,lastrreg,lastrval;
73
static int lastwreg, lastwval, lastrreg, lastrval;
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static flexcop_ibi_value flexcop_pci_read_ibi_reg (struct flexcop_device *fc, flexcop_ibi_register r)
75
static flexcop_ibi_value flexcop_pci_read_ibi_reg(struct flexcop_device *fc,
76
flexcop_ibi_register r)
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struct flexcop_pci *fc_pci = fc->bus_specific;
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flexcop_ibi_value v;
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if (lastrreg != r || lastrval != v.raw) {
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lastrreg = r; lastrval = v.raw;
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deb_reg("new rd: %3x: %08x\n",r,v.raw);
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deb_reg("new rd: %3x: %08x\n", r, v.raw);
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static int flexcop_pci_write_ibi_reg(struct flexcop_device *fc, flexcop_ibi_register r, flexcop_ibi_value v)
90
static int flexcop_pci_write_ibi_reg(struct flexcop_device *fc,
91
flexcop_ibi_register r, flexcop_ibi_value v)
89
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struct flexcop_pci *fc_pci = fc->bus_specific;
91
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if (lastwreg != r || lastwval != v.raw) {
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lastwreg = r; lastwval = v.raw;
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deb_reg("new wr: %3x: %08x\n",r,v.raw);
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deb_reg("new wr: %3x: %08x\n", r, v.raw);
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100
writel(v.raw, fc_pci->io_mem + r);
103
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container_of(work, struct flexcop_pci, irq_check_work.work);
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struct flexcop_device *fc = fc_pci->fc_dev;
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flexcop_ibi_value v = fc->read_ibi_reg(fc,sram_dest_reg_714);
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flexcop_dump_reg(fc_pci->fc_dev,dma1_000,4);
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if (v.sram_dest_reg_714.net_ovflow_error)
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deb_chk("sram net_ovflow_error\n");
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if (v.sram_dest_reg_714.media_ovflow_error)
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deb_chk("sram media_ovflow_error\n");
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if (v.sram_dest_reg_714.cai_ovflow_error)
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deb_chk("sram cai_ovflow_error\n");
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if (v.sram_dest_reg_714.cai_ovflow_error)
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deb_chk("sram cai_ovflow_error\n");
112
if (fc_pci->count == fc_pci->count_prev) {
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deb_chk("no IRQ since the last check\n");
114
if (fc_pci->stream_problem++ == 3) {
115
struct dvb_demux_feed *feed;
116
deb_info("flexcop-pci: stream problem, resetting pid filter\n");
118
spin_lock_irq(&fc->demux.lock);
119
list_for_each_entry(feed, &fc->demux.feed_list,
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flexcop_pid_feed_control(fc, feed, 0);
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list_for_each_entry(feed, &fc->demux.feed_list,
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flexcop_pid_feed_control(fc, feed, 1);
128
spin_unlock_irq(&fc->demux.lock);
130
fc_pci->stream_problem = 0;
133
fc_pci->stream_problem = 0;
134
fc_pci->count_prev = fc_pci->count;
119
138
schedule_delayed_work(&fc_pci->irq_check_work,
120
139
msecs_to_jiffies(irq_chk_intv < 100 ? 100 : irq_chk_intv));
146
164
deb_chk("Transport error\n");
148
166
if ((fc_pci->count % 1000) == 0)
149
deb_chk("%d valid irq took place so far\n",fc_pci->count);
167
deb_chk("%d valid irq took place so far\n", fc_pci->count);
151
169
if (v.irq_20c.DMA1_IRQ_Status == 1) {
152
170
if (fc_pci->active_dma1_addr == 0)
153
flexcop_pass_dmx_packets(fc_pci->fc_dev,fc_pci->dma[0].cpu_addr0,fc_pci->dma[0].size / 188);
171
flexcop_pass_dmx_packets(fc_pci->fc_dev,
172
fc_pci->dma[0].cpu_addr0,
173
fc_pci->dma[0].size / 188);
155
flexcop_pass_dmx_packets(fc_pci->fc_dev,fc_pci->dma[0].cpu_addr1,fc_pci->dma[0].size / 188);
175
flexcop_pass_dmx_packets(fc_pci->fc_dev,
176
fc_pci->dma[0].cpu_addr1,
177
fc_pci->dma[0].size / 188);
157
179
deb_irq("page change to page: %d\n",!fc_pci->active_dma1_addr);
158
180
fc_pci->active_dma1_addr = !fc_pci->active_dma1_addr;
159
} else if (v.irq_20c.DMA1_Timer_Status == 1) {
160
181
/* for the timer IRQ we only can use buffer dmx feeding, because we don't have
161
182
* complete TS packets when reading from the DMA memory */
183
} else if (v.irq_20c.DMA1_Timer_Status == 1) {
162
184
dma_addr_t cur_addr =
163
185
fc->read_ibi_reg(fc,dma1_008).dma_0x8.dma_cur_addr << 2;
164
186
u32 cur_pos = cur_addr - fc_pci->dma[0].dma_addr0;
166
deb_irq("%u irq: %08x cur_addr: %llx: cur_pos: %08x, last_cur_pos: %08x ",
188
deb_irq("%u irq: %08x cur_addr: %llx: cur_pos: %08x, "
189
"last_cur_pos: %08x ",
167
190
jiffies_to_usecs(jiffies - fc_pci->last_irq),
168
191
v.raw, (unsigned long long)cur_addr, cur_pos,
169
192
fc_pci->last_dma1_cur_pos);
173
196
* pass the data from last_cur_pos to the buffer end to the demux
175
198
if (cur_pos < fc_pci->last_dma1_cur_pos) {
176
deb_irq(" end was reached: passing %d bytes ",(fc_pci->dma[0].size*2 - 1) - fc_pci->last_dma1_cur_pos);
199
deb_irq(" end was reached: passing %d bytes ",
200
(fc_pci->dma[0].size*2 - 1) -
201
fc_pci->last_dma1_cur_pos);
177
202
flexcop_pass_dmx_data(fc_pci->fc_dev,
178
fc_pci->dma[0].cpu_addr0 + fc_pci->last_dma1_cur_pos,
179
(fc_pci->dma[0].size*2) - fc_pci->last_dma1_cur_pos);
203
fc_pci->dma[0].cpu_addr0 +
204
fc_pci->last_dma1_cur_pos,
205
(fc_pci->dma[0].size*2) -
206
fc_pci->last_dma1_cur_pos);
180
207
fc_pci->last_dma1_cur_pos = 0;
183
210
if (cur_pos > fc_pci->last_dma1_cur_pos) {
184
deb_irq(" passing %d bytes ",cur_pos - fc_pci->last_dma1_cur_pos);
211
deb_irq(" passing %d bytes ",
212
cur_pos - fc_pci->last_dma1_cur_pos);
185
213
flexcop_pass_dmx_data(fc_pci->fc_dev,
186
fc_pci->dma[0].cpu_addr0 + fc_pci->last_dma1_cur_pos,
187
cur_pos - fc_pci->last_dma1_cur_pos);
214
fc_pci->dma[0].cpu_addr0 +
215
fc_pci->last_dma1_cur_pos,
216
cur_pos - fc_pci->last_dma1_cur_pos);
191
220
fc_pci->last_dma1_cur_pos = cur_pos;
194
deb_irq("isr for flexcop called, apparently without reason (%08x)\n",v.raw);
223
deb_irq("isr for flexcop called, "
224
"apparently without reason (%08x)\n", v.raw);
198
spin_unlock_irqrestore(&fc_pci->irq_lock,flags);
228
spin_unlock_irqrestore(&fc_pci->irq_lock, flags);
205
234
struct flexcop_pci *fc_pci = fc->bus_specific;
207
flexcop_dma_config(fc,&fc_pci->dma[0],FC_DMA_1);
208
flexcop_dma_config(fc,&fc_pci->dma[1],FC_DMA_2);
210
flexcop_dma_config_timer(fc,FC_DMA_1,0);
212
flexcop_dma_xfer_control(fc,FC_DMA_1,FC_DMA_SUBADDR_0 | FC_DMA_SUBADDR_1,1);
236
flexcop_dma_config(fc, &fc_pci->dma[0], FC_DMA_1);
237
flexcop_dma_config(fc, &fc_pci->dma[1], FC_DMA_2);
238
flexcop_dma_config_timer(fc, FC_DMA_1, 0);
239
flexcop_dma_xfer_control(fc, FC_DMA_1,
240
FC_DMA_SUBADDR_0 | FC_DMA_SUBADDR_1, 1);
213
241
deb_irq("DMA xfer enabled\n");
215
243
fc_pci->last_dma1_cur_pos = 0;
216
flexcop_dma_control_timer_irq(fc,FC_DMA_1,1);
244
flexcop_dma_control_timer_irq(fc, FC_DMA_1, 1);
217
245
deb_irq("IRQ enabled\n");
219
// fc_pci->active_dma1_addr = 0;
220
// flexcop_dma_control_size_irq(fc,FC_DMA_1,1);
222
if (irq_chk_intv > 0)
223
schedule_delayed_work(&fc_pci->irq_check_work,
224
msecs_to_jiffies(irq_chk_intv < 100 ? 100 : irq_chk_intv));
246
fc_pci->count_prev = fc_pci->count;
226
if (irq_chk_intv > 0)
227
cancel_delayed_work(&fc_pci->irq_check_work);
229
flexcop_dma_control_timer_irq(fc,FC_DMA_1,0);
248
flexcop_dma_control_timer_irq(fc, FC_DMA_1, 0);
230
249
deb_irq("IRQ disabled\n");
232
// flexcop_dma_control_size_irq(fc,FC_DMA_1,0);
234
flexcop_dma_xfer_control(fc,FC_DMA_1,FC_DMA_SUBADDR_0 | FC_DMA_SUBADDR_1,0);
251
flexcop_dma_xfer_control(fc, FC_DMA_1,
252
FC_DMA_SUBADDR_0 | FC_DMA_SUBADDR_1, 0);
235
253
deb_irq("DMA xfer disabled\n");
241
258
static int flexcop_pci_dma_init(struct flexcop_pci *fc_pci)
244
if ((ret = flexcop_dma_allocate(fc_pci->pdev,&fc_pci->dma[0],FC_DEFAULT_DMA1_BUFSIZE)) != 0)
261
ret = flexcop_dma_allocate(fc_pci->pdev, &fc_pci->dma[0],
262
FC_DEFAULT_DMA1_BUFSIZE);
247
if ((ret = flexcop_dma_allocate(fc_pci->pdev,&fc_pci->dma[1],FC_DEFAULT_DMA2_BUFSIZE)) != 0) {
266
ret = flexcop_dma_allocate(fc_pci->pdev, &fc_pci->dma[1],
267
FC_DEFAULT_DMA2_BUFSIZE);
248
269
flexcop_dma_free(&fc_pci->dma[0]);
252
flexcop_sram_set_dest(fc_pci->fc_dev,FC_SRAM_DEST_MEDIA | FC_SRAM_DEST_NET, FC_SRAM_DEST_TARGET_DMA1);
253
flexcop_sram_set_dest(fc_pci->fc_dev,FC_SRAM_DEST_CAO | FC_SRAM_DEST_CAI, FC_SRAM_DEST_TARGET_DMA2);
273
flexcop_sram_set_dest(fc_pci->fc_dev, FC_SRAM_DEST_MEDIA |
274
FC_SRAM_DEST_NET, FC_SRAM_DEST_TARGET_DMA1);
275
flexcop_sram_set_dest(fc_pci->fc_dev, FC_SRAM_DEST_CAO |
276
FC_SRAM_DEST_CAI, FC_SRAM_DEST_TARGET_DMA2);
255
277
fc_pci->init_state |= FC_PCI_DMA_INIT;