8
8
* This file contains structures and definitions for the
9
9
* Alacritech Sahara host interface
12
/*******************************************************************************
14
*******************************************************************************/
15
struct SXG_UCODE_REGS {
16
// Address 0 - 0x3F = Command codes 0-15 for TCB 0. Excode 0
17
u32 Icr; // Code = 0 (extended), ExCode = 0 - Int control
18
u32 RsvdReg1; // Code = 1 - TOE -NA
19
u32 RsvdReg2; // Code = 2 - TOE -NA
20
u32 RsvdReg3; // Code = 3 - TOE -NA
21
u32 RsvdReg4; // Code = 4 - TOE -NA
22
u32 RsvdReg5; // Code = 5 - TOE -NA
23
u32 CardUp; // Code = 6 - Microcode initialized when 1
24
u32 RsvdReg7; // Code = 7 - TOE -NA
25
u32 CodeNotUsed[8]; // Codes 8-15 not used. ExCode = 0
26
// This brings us to ExCode 1 at address 0x40 = Interrupt status pointer
27
u32 Isp; // Code = 0 (extended), ExCode = 1
28
u32 PadEx1[15]; // Codes 1-15 not used with extended codes
29
// ExCode 2 = Interrupt Status Register
30
u32 Isr; // Code = 0 (extended), ExCode = 2
10
******************************************************************/
15
struct sxg_ucode_regs {
16
/* Address 0 - 0x3F = Command codes 0-15 for TCB 0. Excode 0 */
17
u32 Icr; /* Code = 0 (extended), ExCode = 0 - Int control */
18
u32 RsvdReg1; /* Code = 1 - TOE -NA */
19
u32 RsvdReg2; /* Code = 2 - TOE -NA */
20
u32 RsvdReg3; /* Code = 3 - TOE -NA */
21
u32 RsvdReg4; /* Code = 4 - TOE -NA */
22
u32 RsvdReg5; /* Code = 5 - TOE -NA */
23
u32 CardUp; /* Code = 6 - Microcode initialized when 1 */
24
u32 RsvdReg7; /* Code = 7 - TOE -NA */
25
u32 ConfigStat; /* Code = 8 - Configuration data load status */
26
u32 RsvdReg9; /* Code = 9 - TOE -NA */
27
u32 CodeNotUsed[6]; /* Codes 10-15 not used. ExCode = 0 */
28
/* This brings us to ExCode 1 at address 0x40 = Interrupt status pointer */
29
u32 Isp; /* Code = 0 (extended), ExCode = 1 */
30
u32 PadEx1[15]; /* Codes 1-15 not used with extended codes */
31
/* ExCode 2 = Interrupt Status Register */
32
u32 Isr; /* Code = 0 (extended), ExCode = 2 */
32
// ExCode 3 = Event base register. Location of event rings
33
u32 EventBase; // Code = 0 (extended), ExCode = 3
34
/* ExCode 3 = Event base register. Location of event rings */
35
u32 EventBase; /* Code = 0 (extended), ExCode = 3 */
35
// ExCode 4 = Event ring size
36
u32 EventSize; // Code = 0 (extended), ExCode = 4
37
/* ExCode 4 = Event ring size */
38
u32 EventSize; /* Code = 0 (extended), ExCode = 4 */
38
// ExCode 5 = TCB Buffers base address
39
u32 TcbBase; // Code = 0 (extended), ExCode = 5
40
/* ExCode 5 = TCB Buffers base address */
41
u32 TcbBase; /* Code = 0 (extended), ExCode = 5 */
41
// ExCode 6 = TCB Composite Buffers base address
42
u32 TcbCompBase; // Code = 0 (extended), ExCode = 6
43
/* ExCode 6 = TCB Composite Buffers base address */
44
u32 TcbCompBase; /* Code = 0 (extended), ExCode = 6 */
44
// ExCode 7 = Transmit ring base address
45
u32 XmtBase; // Code = 0 (extended), ExCode = 7
46
/* ExCode 7 = Transmit ring base address */
47
u32 XmtBase; /* Code = 0 (extended), ExCode = 7 */
47
// ExCode 8 = Transmit ring size
48
u32 XmtSize; // Code = 0 (extended), ExCode = 8
49
/* ExCode 8 = Transmit ring size */
50
u32 XmtSize; /* Code = 0 (extended), ExCode = 8 */
50
// ExCode 9 = Receive ring base address
51
u32 RcvBase; // Code = 0 (extended), ExCode = 9
52
/* ExCode 9 = Receive ring base address */
53
u32 RcvBase; /* Code = 0 (extended), ExCode = 9 */
53
// ExCode 10 = Receive ring size
54
u32 RcvSize; // Code = 0 (extended), ExCode = 10
55
/* ExCode 10 = Receive ring size */
56
u32 RcvSize; /* Code = 0 (extended), ExCode = 10 */
56
// ExCode 11 = Read EEPROM Config
57
u32 Config; // Code = 0 (extended), ExCode = 11
58
/* ExCode 11 = Read EEPROM/Flash Config */
59
u32 Config; /* Code = 0 (extended), ExCode = 11 */
59
// ExCode 12 = Multicast bits 31:0
60
u32 McastLow; // Code = 0 (extended), ExCode = 12
61
/* ExCode 12 = Multicast bits 31:0 */
62
u32 McastLow; /* Code = 0 (extended), ExCode = 12 */
62
// ExCode 13 = Multicast bits 63:32
63
u32 McastHigh; // Code = 0 (extended), ExCode = 13
64
/* ExCode 13 = Multicast bits 63:32 */
65
u32 McastHigh; /* Code = 0 (extended), ExCode = 13 */
66
u32 Ping; // Code = 0 (extended), ExCode = 14
67
/* ExCode 14 = Ping */
68
u32 Ping; /* Code = 0 (extended), ExCode = 14 */
68
// ExCode 15 = Link MTU
69
u32 LinkMtu; // Code = 0 (extended), ExCode = 15
70
/* ExCode 15 = Link MTU */
71
u32 LinkMtu; /* Code = 0 (extended), ExCode = 15 */
71
// ExCode 16 = Download synchronization
72
u32 LoadSync; // Code = 0 (extended), ExCode = 16
73
/* ExCode 16 = Download synchronization */
74
u32 LoadSync; /* Code = 0 (extended), ExCode = 16 */
74
// ExCode 17 = Upper DRAM address bits on 32-bit systems
75
u32 Upper; // Code = 0 (extended), ExCode = 17
76
/* ExCode 17 = Upper DRAM address bits on 32-bit systems */
77
u32 Upper; /* Code = 0 (extended), ExCode = 17 */
77
// ExCode 18 = Slowpath Send Index Address
78
u32 SPSendIndex; // Code = 0 (extended), ExCode = 18
79
/* ExCode 18 = Slowpath Send Index Address */
80
u32 SPSendIndex; /* Code = 0 (extended), ExCode = 18 */
80
u32 RsvdXF; // Code = 0 (extended), ExCode = 19
82
/* ExCode 19 = Get ucode statistics */
83
u32 GetUcodeStats; /* Code = 0 (extended), ExCode = 19 */
82
// ExCode 20 = Aggregation
83
u32 Aggregation; // Code = 0 (extended), ExCode = 20
85
/* ExCode 20 = Aggregation - See sxgmisc.c:SxgSetInterruptAggregation */
86
u32 Aggregation; /* Code = 0 (extended), ExCode = 20 */
85
// ExCode 21 = Receive MDL push timer
86
u32 PushTicks; // Code = 0 (extended), ExCode = 21
88
/* ExCode 21 = Receive MDL push timer */
89
u32 PushTicks; /* Code = 0 (extended), ExCode = 21 */
89
u32 AckFrequency; // Code = 0 (extended), ExCode = 22
91
/* ExCode 22 = ACK Frequency */
92
u32 AckFrequency; /* Code = 0 (extended), ExCode = 22 */
94
/* ExCode 23 = TOE NA */
97
/* ExCode 24 = TOE NA */
98
u32 RsvdReg25; // Code = 0 (extended), ExCode = 25
100
/* ExCode 25 = TOE NA */
101
u32 RsvdReg25; /* Code = 0 (extended), ExCode = 25 */
100
// ExCode 26 = Receive checksum requirements
101
u32 ReceiveChecksum; // Code = 0 (extended), ExCode = 26
103
/* ExCode 26 = Receive checksum requirements */
104
u32 ReceiveChecksum; /* Code = 0 (extended), ExCode = 26 */
103
// ExCode 27 = RSS Requirements
104
u32 Rss; // Code = 0 (extended), ExCode = 27
106
/* ExCode 27 = RSS Requirements */
107
u32 Rss; /* Code = 0 (extended), ExCode = 27 */
106
// ExCode 28 = RSS Table
107
u32 RssTable; // Code = 0 (extended), ExCode = 28
109
/* ExCode 28 = RSS Table */
110
u32 RssTable; /* Code = 0 (extended), ExCode = 28 */
109
// ExCode 29 = Event ring release entries
110
u32 EventRelease; // Code = 0 (extended), ExCode = 29
112
/* ExCode 29 = Event ring release entries */
113
u32 EventRelease; /* Code = 0 (extended), ExCode = 29 */
112
// ExCode 30 = Number of receive bufferlist commands on ring 0
113
u32 RcvCmd; // Code = 0 (extended), ExCode = 30
115
/* ExCode 30 = Number of receive bufferlist commands on ring 0 */
116
u32 RcvCmd; /* Code = 0 (extended), ExCode = 30 */
115
// ExCode 31 = slowpath transmit command - Data[31:0] = 1
116
u32 XmtCmd; // Code = 0 (extended), ExCode = 31
118
/* ExCode 31 = slowpath transmit command - Data[31:0] = 1 */
119
u32 XmtCmd; /* Code = 0 (extended), ExCode = 31 */
118
// ExCode 32 = Dump command
119
u32 DumpCmd; // Code = 0 (extended), ExCode = 32
121
/* ExCode 32 = Dump command */
122
u32 DumpCmd; /* Code = 0 (extended), ExCode = 32 */
121
// ExCode 33 = Debug command
122
u32 DebugCmd; // Code = 0 (extended), ExCode = 33
124
/* ExCode 33 = Debug command */
125
u32 DebugCmd; /* Code = 0 (extended), ExCode = 33 */
124
// There are 128 possible extended commands - each of account for 16
125
// words (including the non-relevent base command codes 1-15).
126
// Pad for the remainder of these here to bring us to the next CPU
127
// base. As extended codes are added, reduce the first array value in
128
// the following field
129
u32 PadToNextCpu[94][16]; // 94 = 128 - 34 (34 = Excodes 0 - 33)
128
* There are 128 possible extended commands - each of account for 16
129
* words (including the non-relevent base command codes 1-15).
130
* Pad for the remainder of these here to bring us to the next CPU
131
* base. As extended codes are added, reduce the first array value in
132
* the following field
134
u32 PadToNextCpu[94][16]; /* 94 = 128 - 34 (34 = Excodes 0 - 33)*/
132
// Interrupt control register (0) values
137
/* Interrupt control register (0) values */
133
138
#define SXG_ICR_DISABLE 0x00000000
134
139
#define SXG_ICR_ENABLE 0x00000001
135
140
#define SXG_ICR_MASK 0x00000002
270
290
* ||------- ISTCPIP
271
291
* |-------- SCERR
293
************************************************************************/
274
294
#pragma pack(push, 1)
276
u32 Pad[1]; // not used
277
u32 SndUna; // SndUna value
278
u32 Resid; // receive MDL resid
296
u32 Pad[1]; /* not used */
297
u32 SndUna; /* SndUna value */
298
u32 Resid; /* receive MDL resid */
280
void *HostHandle; // Receive host handle
300
void * HostHandle; /* Receive host handle */
301
u32 Rsvd1; /* TOE NA */
304
u32 Rsvd2; /* TOE NA */
287
u32 Toeplitz; // RSS Toeplitz hash
307
u32 Toeplitz; /* RSS Toeplitz hash */
289
ushort Rsvd3; // TOE NA
290
ushort HdrOffset; // Slowpath
309
ushort Rsvd3; /* TOE NA */
310
ushort HdrOffset; /* Slowpath */
293
unsigned char Rsvd4; // TOE NA
294
unsigned char Code; // Event code
295
unsigned char CommandIndex; // New ring index
296
unsigned char Status; // Event status
313
unsigned char Rsvd4; /* TOE NA */
314
unsigned char Code; /* Event code */
315
unsigned char CommandIndex; /* New ring index */
316
unsigned char Status; /* Event status */
298
318
#pragma pack(pop)
300
// Event code definitions
301
#define EVENT_CODE_BUFFERS 0x01 // Receive buffer list command (ring 0)
302
#define EVENT_CODE_SLOWRCV 0x02 // Slowpath receive
303
#define EVENT_CODE_UNUSED 0x04 // Was slowpath commands complete
306
#define EVENT_STATUS_VALID 0x80 // Entry valid
309
#define EVENT_STATUS_ERROR 0x40 // Completed with error. Index in next byte
310
#define EVENT_STATUS_TCPIP4 0x20 // TCPIPv4 frame
311
#define EVENT_STATUS_TCPBAD 0x10 // Bad TCP checksum
312
#define EVENT_STATUS_IPBAD 0x08 // Bad IP checksum
313
#define EVENT_STATUS_RCVERR 0x04 // Slowpath receive error
314
#define EVENT_STATUS_IPONLY 0x02 // IP frame
315
#define EVENT_STATUS_TCPIP6 0x01 // TCPIPv6 frame
316
#define EVENT_STATUS_TCPIP 0x21 // Combination of v4 and v6
319
// Size must be power of 2, between 128 and 16k
320
#define EVENT_RING_SIZE 4096 // ??
321
#define EVENT_RING_BATCH 16 // Hand entries back 16 at a time.
322
#define EVENT_BATCH_LIMIT 256 // Stop processing events after 256 (16 * 16)
324
struct SXG_EVENT_RING {
325
struct SXG_EVENT Ring[EVENT_RING_SIZE];
320
/* Event code definitions */
321
#define EVENT_CODE_BUFFERS 0x01 /* Receive buffer list command (ring 0) */
322
#define EVENT_CODE_SLOWRCV 0x02 /* Slowpath receive */
323
#define EVENT_CODE_UNUSED 0x04 /* Was slowpath commands complete */
326
#define EVENT_STATUS_VALID 0x80 /* Entry valid */
328
/* Slowpath status */
329
#define EVENT_STATUS_ERROR 0x40 /* Completed with error. Index in next byte */
330
#define EVENT_STATUS_TCPIP4 0x20 /* TCPIPv4 frame */
331
#define EVENT_STATUS_TCPBAD 0x10 /* Bad TCP checksum */
332
#define EVENT_STATUS_IPBAD 0x08 /* Bad IP checksum */
333
#define EVENT_STATUS_RCVERR 0x04 /* Slowpath receive error */
334
#define EVENT_STATUS_IPONLY 0x02 /* IP frame */
335
#define EVENT_STATUS_TCPIP6 0x01 /* TCPIPv6 frame */
336
#define EVENT_STATUS_TCPIP 0x21 /* Combination of v4 and v6 */
340
* Size must be power of 2, between 128 and 16k
342
#define EVENT_RING_SIZE 4096
343
#define EVENT_RING_BATCH 16 /* Hand entries back 16 at a time. */
344
/* Stop processing events after 4096 (256 * 16) */
345
#define EVENT_BATCH_LIMIT 256
347
struct sxg_event_ring {
348
struct sxg_event Ring[EVENT_RING_SIZE];
328
/***************************************************************************
332
***************************************************************************/
333
// Maximum number of TCBS supported by hardware/microcode
352
/* Maximum number of TCBS supported by hardware/microcode */
334
353
#define SXG_MAX_TCB 4096
335
// Minimum TCBs before we fail initialization
354
/* Minimum TCBs before we fail initialization */
336
355
#define SXG_MIN_TCB 512
338
// The bucket is determined by bits 11:4 of the toeplitz if we support 4k
339
// offloaded connections, 10:4 if we support 2k and so on.
358
* The bucket is determined by bits 11:4 of the toeplitz if we support 4k
359
* offloaded connections, 10:4 if we support 2k and so on.
340
361
#define SXG_TCB_BUCKET_SHIFT 4
341
#define SXG_TCB_PER_BUCKET 16
342
#define SXG_TCB_BUCKET_MASK 0xFF0 // Bucket portion of TCB ID
343
#define SXG_TCB_ELEMENT_MASK 0x00F // Element within bucket
344
#define SXG_TCB_BUCKETS 256 // 256 * 16 = 4k
346
#define SXG_TCB_BUFFER_SIZE 512 // ASSERT format is correct
348
#define SXG_TCB_RCVQ_SIZE 736
362
#define SXG_TCB_PER_BUCKET 16
363
#define SXG_TCB_BUCKET_MASK 0xFF0 /* Bucket portion of TCB ID */
364
#define SXG_TCB_ELEMENT_MASK 0x00F /* Element within bucket */
365
#define SXG_TCB_BUCKETS 256 /* 256 * 16 = 4k */
367
#define SXG_TCB_BUFFER_SIZE 512 /* ASSERT format is correct */
369
#define SXG_TCB_RCVQ_SIZE 736
350
371
#define SXG_TCB_COMPOSITE_BUFFER_SIZE 1024
352
#define SXG_LOCATE_TCP_FRAME_HDR(_TcpObject, _IPv6) \
353
(((_TcpObject)->VlanId) ? \
354
((_IPv6) ? /* Vlan frame header = yes */ \
355
&(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp6.SxgTcp : \
356
&(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp.SxgTcp) : \
357
((_IPv6) ? /* Vlan frame header = No */ \
358
&(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp6.SxgTcp : \
373
#define SXG_LOCATE_TCP_FRAME_HDR(_TcpObject, _IPv6) \
374
(((_TcpObject)->VlanId) ? \
375
((_IPv6) ? /* Vlan frame header = yes */ \
376
&(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp6.SxgTcp: \
377
&(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp.SxgTcp): \
378
((_IPv6) ? /* Vlan frame header = No */ \
379
&(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp6.SxgTcp : \
359
380
&(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp.SxgTcp))
361
#define SXG_LOCATE_IP_FRAME_HDR(_TcpObject) \
362
(_TcpObject)->VlanId ? \
363
&(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp.Ip : \
382
#define SXG_LOCATE_IP_FRAME_HDR(_TcpObject) \
383
(_TcpObject)->VlanId ? \
384
&(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp.Ip: \
364
385
&(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp.Ip
366
#define SXG_LOCATE_IP6_FRAME_HDR(_TcpObject) \
367
(_TcpObject)->VlanId ? \
368
&(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp6.Ip : \
387
#define SXG_LOCATE_IP6_FRAME_HDR(TcpObject) \
388
(_TcpObject)->VlanId ? \
389
&(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp6.Ip: \
369
390
&(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp6.Ip
372
// Horrible kludge to distinguish dumb-nic, slowpath, and
373
// fastpath traffic. Decrement the HopLimit by one
374
// for slowpath, two for fastpath. This assumes the limit is measurably
375
// greater than two, which I think is reasonable.
376
// Obviously this is DBG only. Maybe remove later, or #if 0 so we
377
// can set it when needed
378
#define SXG_DBG_HOP_LIMIT(_TcpObject, _FastPath) { \
379
PIPV6_HDR _Ip6FrameHdr; \
380
if((_TcpObject)->IPv6) { \
381
_Ip6FrameHdr = SXG_LOCATE_IP6_FRAME_HDR((_TcpObject)); \
383
_Ip6FrameHdr->HopLimit = (_TcpObject)->Cached.TtlOrHopLimit - 2; \
385
_Ip6FrameHdr->HopLimit = (_TcpObject)->Cached.TtlOrHopLimit - 1; \
394
* Horrible kludge to distinguish dumb-nic, slowpath, and
395
* fastpath traffic. Decrement the HopLimit by one
396
* for slowpath, two for fastpath. This assumes the limit is measurably
397
* greater than two, which I think is reasonable.
398
* Obviously this is DBG only. Maybe remove later, or #if 0 so we
399
* can set it when needed
401
#define SXG_DBG_HOP_LIMIT(_TcpObject, _FastPath) { \
402
PIPV6_HDR _Ip6FrameHdr; \
403
if ((_TcpObject)->IPv6) { \
404
_Ip6FrameHdr = SXG_LOCATE_IP6_FRAME_HDR((_TcpObject)); \
406
_Ip6FrameHdr->HopLimit = \
407
(_TcpObject)->Cached.TtlOrHopLimit - 2; \
409
_Ip6FrameHdr->HopLimit = \
410
(_TcpObject)->Cached.TtlOrHopLimit - 1; \
390
// Do nothing with free build
415
/* Do nothing with free build */
391
416
#define SXG_DBG_HOP_LIMIT(_TcpObject, _FastPath)
394
/***************************************************************************
395
* Receive and transmit rings
396
***************************************************************************/
419
/* Receive and transmit rings */
397
420
#define SXG_MAX_RING_SIZE 256
398
#define SXG_XMT_RING_SIZE 128 // Start with 128
399
#define SXG_RCV_RING_SIZE 128 // Start with 128
421
#define SXG_XMT_RING_SIZE 128 /* Start with 128 */
422
#define SXG_RCV_RING_SIZE 128 /* Start with 128 */
400
423
#define SXG_MAX_ENTRIES 4096
424
#define SXG_JUMBO_RCV_RING_SIZE 32
402
// Structure and macros to manage a ring
403
struct SXG_RING_INFO {
404
unsigned char Head; // Where we add entries - Note unsigned char:RING_SIZE
405
unsigned char Tail; // Where we pull off completed entries
406
ushort Size; // Ring size - Must be multiple of 2
407
void *Context[SXG_MAX_RING_SIZE]; // Shadow ring
426
/* Structure and macros to manage a ring */
427
struct sxg_ring_info {
428
/* Where we add entries - Note unsigned char:RING_SIZE */
430
unsigned char Tail; /* Where we pull off completed entries */
431
ushort Size; /* Ring size - Must be multiple of 2 */
432
void * Context[SXG_MAX_RING_SIZE]; /* Shadow ring */
410
#define SXG_INITIALIZE_RING(_ring, _size) { \
413
(_ring).Size = (_size); \
435
#define SXG_INITIALIZE_RING(_ring, _size) { \
438
(_ring).Size = (_size); \
415
#define SXG_ADVANCE_INDEX(_index, _size) ((_index) = ((_index) + 1) & ((_size) - 1))
416
#define SXG_PREVIOUS_INDEX(_index, _size) (((_index) - 1) &((_size) - 1))
441
#define SXG_ADVANCE_INDEX(_index, _size) \
442
((_index) = ((_index) + 1) & ((_size) - 1))
443
#define SXG_PREVIOUS_INDEX(_index, _size) \
444
(((_index) - 1) &((_size) - 1))
417
445
#define SXG_RING_EMPTY(_ring) ((_ring)->Head == (_ring)->Tail)
418
#define SXG_RING_FULL(_ring) ((((_ring)->Head + 1) & ((_ring)->Size - 1)) == (_ring)->Tail)
419
#define SXG_RING_ADVANCE_HEAD(_ring) SXG_ADVANCE_INDEX((_ring)->Head, ((_ring)->Size))
420
#define SXG_RING_RETREAT_HEAD(_ring) ((_ring)->Head = \
421
SXG_PREVIOUS_INDEX((_ring)->Head, (_ring)->Size))
422
#define SXG_RING_ADVANCE_TAIL(_ring) { \
423
ASSERT((_ring)->Tail != (_ring)->Head); \
424
SXG_ADVANCE_INDEX((_ring)->Tail, ((_ring)->Size)); \
446
#define SXG_RING_FULL(_ring) \
447
((((_ring)->Head + 1) & ((_ring)->Size - 1)) == (_ring)->Tail)
448
#define SXG_RING_ADVANCE_HEAD(_ring) \
449
SXG_ADVANCE_INDEX((_ring)->Head, ((_ring)->Size))
450
#define SXG_RING_RETREAT_HEAD(_ring) ((_ring)->Head = \
451
SXG_PREVIOUS_INDEX((_ring)->Head, (_ring)->Size))
452
#define SXG_RING_ADVANCE_TAIL(_ring) { \
453
ASSERT((_ring)->Tail != (_ring)->Head); \
454
SXG_ADVANCE_INDEX((_ring)->Tail, ((_ring)->Size)); \
426
// Set cmd to the next available ring entry, set the shadow context
427
// entry and advance the ring.
428
// The appropriate lock must be held when calling this macro
429
#define SXG_GET_CMD(_ring, _ringinfo, _cmd, _context) { \
430
if(SXG_RING_FULL(_ringinfo)) { \
433
(_cmd) = &(_ring)->Descriptors[(_ringinfo)->Head]; \
457
* Set cmd to the next available ring entry, set the shadow context
458
* entry and advance the ring.
459
* The appropriate lock must be held when calling this macro
461
#define SXG_GET_CMD(_ring, _ringinfo, _cmd, _context) { \
462
if(SXG_RING_FULL(_ringinfo)) { \
465
(_cmd) = &(_ring)->Descriptors[(_ringinfo)->Head]; \
434
466
(_ringinfo)->Context[(_ringinfo)->Head] = (void *)(_context);\
435
SXG_RING_ADVANCE_HEAD(_ringinfo); \
439
// Abort the previously allocated command by retreating the head.
440
// NOTE - The appopriate lock MUST NOT BE DROPPED between the SXG_GET_CMD
441
// and SXG_ABORT_CMD calls.
442
#define SXG_ABORT_CMD(_ringinfo) { \
443
ASSERT(!(SXG_RING_EMPTY(_ringinfo))); \
444
SXG_RING_RETREAT_HEAD(_ringinfo); \
445
(_ringinfo)->Context[(_ringinfo)->Head] = NULL; \
448
// For the given ring, return a pointer to the tail cmd and context,
449
// clear the context and advance the tail
450
#define SXG_RETURN_CMD(_ring, _ringinfo, _cmd, _context) { \
451
(_cmd) = &(_ring)->Descriptors[(_ringinfo)->Tail]; \
467
SXG_RING_ADVANCE_HEAD(_ringinfo); \
472
* Abort the previously allocated command by retreating the head.
473
* NOTE - The appopriate lock MUST NOT BE DROPPED between the SXG_GET_CMD
474
* and SXG_ABORT_CMD calls.
476
#define SXG_ABORT_CMD(_ringinfo) { \
477
ASSERT(!(SXG_RING_EMPTY(_ringinfo))); \
478
SXG_RING_RETREAT_HEAD(_ringinfo); \
479
(_ringinfo)->Context[(_ringinfo)->Head] = NULL; \
483
* For the given ring, return a pointer to the tail cmd and context,
484
* clear the context and advance the tail
486
#define SXG_RETURN_CMD(_ring, _ringinfo, _cmd, _context) { \
487
(_cmd) = &(_ring)->Descriptors[(_ringinfo)->Tail]; \
452
488
(_context) = (_ringinfo)->Context[(_ringinfo)->Tail]; \
453
(_ringinfo)->Context[(_ringinfo)->Tail] = NULL; \
454
SXG_RING_ADVANCE_TAIL(_ringinfo); \
457
/***************************************************************************
489
(_ringinfo)->Context[(_ringinfo)->Tail] = NULL; \
490
SXG_RING_ADVANCE_TAIL(_ringinfo); \
494
* For a given ring find out how much the first pointer is ahead of
495
* the second pointer. "ahead" recognises the fact that the ring can wrap
497
static inline int sxg_ring_get_forward_diff (struct sxg_ring_info *ringinfo,
499
if ((a < 0 || a > ringinfo->Size ) || (b < 0 || b > ringinfo->Size))
501
if (a > b) /* _a is lagging _b and _b has not wrapped around */
504
return ((ringinfo->Size - (b - a)));
507
/***************************************************************
459
508
* Host Command Buffer - commands to INIC via the Cmd Rings
461
***************************************************************************/
464
511
* .___________________.___________________.
465
512
* |<-------------- Sgl Low -------------->|
597
645
* DMA data into, and a virtual address, which is given back
598
646
* to the host in the "HostHandle" portion of an event.
599
647
* The receive descriptor data structure is defined below
600
* as SXG_RCV_DATA_DESCRIPTOR, and the corresponding block
601
* is defined as SXG_RCV_DESCRIPTOR_BLOCK.
648
* as sxg_rcv_data_descriptor, and the corresponding block
649
* is defined as sxg_rcv_descriptor_block.
603
651
* This receive descriptor block is given to the card by filling
604
* in the Sgl field of a SXG_CMD entry from pAdapt->RcvRings[0]
652
* in the Sgl field of a sxg_cmd entry from pAdapt->RcvRings[0]
605
653
* with the physical address of the receive descriptor block.
607
655
* Both the receive buffers and the receive descriptor blocks
608
656
* require additional data structures to maintain them
609
657
* on a free queue and contain other information associated with them.
610
* Those data structures are defined as the SXG_RCV_DATA_BUFFER_HDR
611
* and SXG_RCV_DESCRIPTOR_BLOCK_HDR respectively.
658
* Those data structures are defined as the sxg_rcv_data_buffer_hdr
659
* and sxg_rcv_descriptor_block_hdr respectively.
613
661
* Since both the receive buffers and the receive descriptor block
614
662
* must be accessible by the card, both must be allocated out of
615
663
* shared memory. To ensure that we always have a descriptor
616
664
* block available for every 128 buffers, we allocate all of
617
665
* these resources together in a single block. This entire
618
* block is managed by a SXG_RCV_BLOCK_HDR, who's sole purpose
666
* block is managed by a struct sxg_rcv_block_hdr, who's sole purpose
619
667
* is to maintain address information so that the entire block
620
668
* can be free later.
622
670
* Further complicating matters is the fact that the receive
623
671
* buffers must be variable in length in order to accomodate
624
672
* jumbo frame configurations. We configure the buffer
625
* length so that the buffer and it's corresponding SXG_RCV_DATA_BUFFER_HDR
626
* structure add up to an even boundary. Then we place the
627
* remaining data structures after 128 of them as shown in
628
* the following diagram:
673
* length so that the buffer and it's corresponding struct
674
* sxg_rcv_data_buffer_hdr structure add up to an even
675
* boundary. Then we place the remaining data structures after 128
676
* of them as shown in the following diagram:
630
678
* _________________________________________
632
680
* | Variable length receive buffer #1 |
633
681
* |_________________________________________|
635
* | SXG_RCV_DATA_BUFFER_HDR #1 |
683
* | sxg_rcv_data_buffer_hdr #1 |
636
684
* |_________________________________________| <== Even 2k or 10k boundary
638
686
* | ... repeat 2-128 .. |
639
687
* |_________________________________________|
641
* | SXG_RCV_DESCRIPTOR_BLOCK |
642
* | Contains SXG_RCV_DATA_DESCRIPTOR * 128 |
643
* |_________________________________________|
645
* | SXG_RCV_DESCRIPTOR_BLOCK_HDR |
646
* |_________________________________________|
648
* | SXG_RCV_BLOCK_HDR |
689
* | struct sxg_rcv_descriptor_block |
690
* | Contains sxg_rcv_data_descriptor * 128 |
691
* |_________________________________________|
693
* | struct sxg_rcv_descriptor_block_hdr |
694
* |_________________________________________|
696
* | struct sxg_rcv_block_hdr |
649
697
* |_________________________________________|
651
699
* Memory consumption:
653
* Buffers and SXG_RCV_DATA_BUFFER_HDR = 2k * 128 = 256k
654
* + SXG_RCV_DESCRIPTOR_BLOCK = 2k
655
* + SXG_RCV_DESCRIPTOR_BLOCK_HDR = ~32
656
* + SXG_RCV_BLOCK_HDR = ~32
701
* Buffers and sxg_rcv_data_buffer_hdr = 2k * 128 = 256k
702
* + struct sxg_rcv_descriptor_block = 2k
703
* + struct sxg_rcv_descriptor_block_hdr = ~32
704
* + struct sxg_rcv_block_hdr = ~32
657
705
* => Total = ~258k/block
660
* Buffers and SXG_RCV_DATA_BUFFER_HDR = 10k * 128 = 1280k
661
* + SXG_RCV_DESCRIPTOR_BLOCK = 2k
662
* + SXG_RCV_DESCRIPTOR_BLOCK_HDR = ~32
663
* + SXG_RCV_BLOCK_HDR = ~32
708
* Buffers and sxg_rcv_data_buffer_hdr = 10k * 128 = 1280k
709
* + struct sxg_rcv_descriptor_block = 2k
710
* + struct sxg_rcv_descriptor_block_hdr = ~32
711
* + struct sxg_rcv_block_hdr = ~32
664
712
* => Total = ~1282k/block
666
***************************************************************************/
667
#define SXG_RCV_DATA_BUFFERS 4096 // Amount to give to the card
668
#define SXG_INITIAL_RCV_DATA_BUFFERS 8192 // Initial pool of buffers
669
#define SXG_MIN_RCV_DATA_BUFFERS 2048 // Minimum amount and when to get more
670
#define SXG_MAX_RCV_BLOCKS 128 // = 16384 receive buffers
715
#define SXG_RCV_DATA_BUFFERS 8192 /* Amount to give to the card */
716
#define SXG_INITIAL_RCV_DATA_BUFFERS 16384 /* Initial pool of buffers */
717
/* Minimum amount and when to get more */
718
#define SXG_MIN_RCV_DATA_BUFFERS 4096
719
#define SXG_MAX_RCV_BLOCKS 256 /* = 32k receive buffers */
720
/* Amount to give to the card in case of jumbo frames */
721
#define SXG_JUMBO_RCV_DATA_BUFFERS 2048
722
/* Initial pool of buffers in case of jumbo buffers */
723
#define SXG_INITIAL_JUMBO_RCV_DATA_BUFFERS 4096
724
#define SXG_MIN_JUMBO_RCV_DATA_BUFFERS 1024
672
// Receive buffer header
673
struct SXG_RCV_DATA_BUFFER_HDR {
674
dma_addr_t PhysicalAddress; // Buffer physical address
675
// Note - DO NOT USE the VirtualAddress field to locate data.
676
// Use the sxg.h:SXG_RECEIVE_DATA_LOCATION macro instead.
677
void *VirtualAddress; // Start of buffer
678
struct LIST_ENTRY FreeList; // Free queue of buffers
679
struct SXG_RCV_DATA_BUFFER_HDR *Next; // Fastpath data buffer queue
680
u32 Size; // Buffer size
681
u32 ByteOffset; // See SXG_RESTORE_MDL_OFFSET
682
unsigned char State; // See SXG_BUFFER state above
683
unsigned char Status; // Event status (to log PUSH)
684
struct sk_buff *skb; // Double mapped (nbl and pkt)
726
/* Receive buffer header */
727
struct sxg_rcv_data_buffer_hdr {
728
dma64_addr_t PhysicalAddress; /* Buffer physical address */
730
* Note - DO NOT USE the VirtualAddress field to locate data.
731
* Use the sxg.h:SXG_RECEIVE_DATA_LOCATION macro instead.
733
struct list_entry FreeList; /* Free queue of buffers */
734
unsigned char State; /* See SXG_BUFFER state above */
735
struct sk_buff * skb; /* Double mapped (nbl and pkt)*/
687
// SxgSlowReceive uses the PACKET (skb) contained
688
// in the SXG_RCV_DATA_BUFFER_HDR when indicating dumb-nic data
739
* SxgSlowReceive uses the PACKET (skb) contained
740
* in the struct sxg_rcv_data_buffer_hdr when indicating dumb-nic data
689
742
#define SxgDumbRcvPacket skb
691
#define SXG_RCV_DATA_HDR_SIZE 256 // Space for SXG_RCV_DATA_BUFFER_HDR
692
#define SXG_RCV_DATA_BUFFER_SIZE 2048 // Non jumbo = 2k including HDR
693
#define SXG_RCV_JUMBO_BUFFER_SIZE 10240 // jumbo = 10k including HDR
744
/* Space for struct sxg_rcv_data_buffer_hdr */
745
#define SXG_RCV_DATA_HDR_SIZE sizeof(struct sxg_rcv_data_buffer_hdr)
746
/* Non jumbo = 2k including HDR */
747
#define SXG_RCV_DATA_BUFFER_SIZE 2048
748
/* jumbo = 10k including HDR */
749
#define SXG_RCV_JUMBO_BUFFER_SIZE 10240
695
// Receive data descriptor
696
struct SXG_RCV_DATA_DESCRIPTOR {
751
/* Receive data descriptor */
752
struct sxg_rcv_data_descriptor {
698
struct sk_buff *VirtualAddress; // Host handle
699
u64 ForceTo8Bytes; // Force x86 to 8-byte boundary
754
struct sk_buff *VirtualAddress; /* Host handle */
755
u64 ForceTo8Bytes; /*Force x86 to 8-byte boundary*/
701
dma_addr_t PhysicalAddress;
757
dma64_addr_t PhysicalAddress;
704
// Receive descriptor block
760
/* Receive descriptor block */
705
761
#define SXG_RCV_DESCRIPTORS_PER_BLOCK 128
706
#define SXG_RCV_DESCRIPTOR_BLOCK_SIZE 2048 // For sanity check
708
struct SXG_RCV_DESCRIPTOR_BLOCK {
709
struct SXG_RCV_DATA_DESCRIPTOR Descriptors[SXG_RCV_DESCRIPTORS_PER_BLOCK];
712
// Receive descriptor block header
713
struct SXG_RCV_DESCRIPTOR_BLOCK_HDR {
714
void *VirtualAddress; // Start of 2k buffer
715
dma_addr_t PhysicalAddress; // ..and it's physical address
716
struct LIST_ENTRY FreeList; // Free queue of descriptor blocks
717
unsigned char State; // See SXG_BUFFER state above
720
// Receive block header
721
struct SXG_RCV_BLOCK_HDR {
722
void *VirtualAddress; // Start of virtual memory
723
dma_addr_t PhysicalAddress; // ..and it's physical address
724
struct LIST_ENTRY AllList; // Queue of all SXG_RCV_BLOCKS
727
// Macros to determine data structure offsets into receive block
728
#define SXG_RCV_BLOCK_SIZE(_Buffersize) \
762
#define SXG_RCV_DESCRIPTOR_BLOCK_SIZE 2048 /* For sanity check */
764
struct sxg_rcv_descriptor_block {
765
struct sxg_rcv_data_descriptor Descriptors[SXG_RCV_DESCRIPTORS_PER_BLOCK];
768
/* Receive descriptor block header */
769
struct sxg_rcv_descriptor_block_hdr {
770
void *VirtualAddress; /* start of 2k buffer */
771
dma64_addr_t PhysicalAddress;/* and it's physical address */
772
struct list_entry FreeList;/* free queue of descriptor blocks */
773
unsigned char State; /* see sxg_buffer state above */
776
/* Receive block header */
777
struct sxg_rcv_block_hdr {
778
void *VirtualAddress; /* Start of virtual memory */
779
dma64_addr_t PhysicalAddress;/* ..and it's physical address*/
780
struct list_entry AllList; /* Queue of all SXG_RCV_BLOCKS*/
783
/* Macros to determine data structure offsets into receive block */
784
#define SXG_RCV_BLOCK_SIZE(_Buffersize) \
729
785
(((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK) + \
730
(sizeof(struct SXG_RCV_DESCRIPTOR_BLOCK)) + \
731
(sizeof(struct SXG_RCV_DESCRIPTOR_BLOCK_HDR)) + \
732
(sizeof(struct SXG_RCV_BLOCK_HDR)))
786
(sizeof(struct sxg_rcv_descriptor_block)) + \
787
(sizeof(struct sxg_rcv_descriptor_block_hdr)) + \
788
(sizeof(struct sxg_rcv_block_hdr)))
733
789
#define SXG_RCV_BUFFER_DATA_SIZE(_Buffersize) \
734
790
((_Buffersize) - SXG_RCV_DATA_HDR_SIZE)
735
791
#define SXG_RCV_DATA_BUFFER_HDR_OFFSET(_Buffersize) \
736
792
((_Buffersize) - SXG_RCV_DATA_HDR_SIZE)
737
#define SXG_RCV_DESCRIPTOR_BLOCK_OFFSET(_Buffersize) \
793
#define SXG_RCV_DESCRIPTOR_BLOCK_OFFSET(_Buffersize) \
738
794
((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK)
739
#define SXG_RCV_DESCRIPTOR_BLOCK_HDR_OFFSET(_Buffersize) \
795
#define SXG_RCV_DESCRIPTOR_BLOCK_HDR_OFFSET(_Buffersize) \
740
796
(((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK) + \
741
(sizeof(struct SXG_RCV_DESCRIPTOR_BLOCK)))
797
(sizeof(struct sxg_rcv_descriptor_block)))
742
798
#define SXG_RCV_BLOCK_HDR_OFFSET(_Buffersize) \
743
799
(((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK) + \
744
(sizeof(struct SXG_RCV_DESCRIPTOR_BLOCK)) + \
745
(sizeof(struct SXG_RCV_DESCRIPTOR_BLOCK_HDR)))
747
// Use the miniport reserved portion of the NBL to locate
748
// our SXG_RCV_DATA_BUFFER_HDR structure.
749
struct SXG_RCV_NBL_RESERVED {
750
struct SXG_RCV_DATA_BUFFER_HDR *RcvDataBufferHdr;
754
#define SXG_RCV_NBL_BUFFER_HDR(_NBL) (((PSXG_RCV_NBL_RESERVED)NET_BUFFER_LIST_MINIPORT_RESERVED(_NBL))->RcvDataBufferHdr)
756
/***************************************************************************
757
* Scatter gather list buffer
758
***************************************************************************/
759
#define SXG_INITIAL_SGL_BUFFERS 8192 // Initial pool of SGL buffers
760
#define SXG_MIN_SGL_BUFFERS 2048 // Minimum amount and when to get more
761
#define SXG_MAX_SGL_BUFFERS 16384 // Maximum to allocate (note ADAPT:ushort)
763
// Self identifying structure type
800
(sizeof(struct sxg_rcv_descriptor_block)) + \
801
(sizeof(struct sxg_rcv_descriptor_block_hdr)))
803
/* Scatter gather list buffer */
804
#define SXG_INITIAL_SGL_BUFFERS 8192 /* Initial pool of SGL buffers */
805
#define SXG_MIN_SGL_BUFFERS 2048 /* Minimum amount and when to get more*/
806
/* Maximum to allocate (note ADAPT:ushort) */
807
#define SXG_MAX_SGL_BUFFERS 16384
810
* SXG_SGL_POOL_PROPERTIES - This structure is used to define a pool of SGL
811
* buffers. These buffers are allocated out of shared memory and used to
812
* contain a physical scatter gather list structure that is shared
815
* We split our SGL buffers into multiple pools based on size. The motivation
816
* is that some applications perform very large I/Os (1MB for example), so
817
* we need to be able to allocate an SGL to accommodate such a request.
818
* But such an SGL would require 256 24-byte SG entries - ~6k.
819
* Given that the vast majority of I/Os are much smaller than 1M, allocating
820
* a single pool of SGL buffers would be a horribly inefficient use of
823
* The following structure includes two fields relating to its size.
824
* The NBSize field specifies the largest NET_BUFFER that can be handled
825
* by the particular pool. The SGEntries field defines the size, in
826
* entries, of the SGL for that pool. The SGEntries is determined by
827
* dividing the NBSize by the expected page size (4k), and then padding
828
* it by some appropriate amount as insurance (20% or so..??).
830
struct sxg_sgl_pool_properties {
831
u32 NBSize; /* Largest NET_BUFFER size for this pool */
832
ushort SGEntries; /* Number of entries in SGL */
833
ushort InitialBuffers; /* Number to allocate at initializationtime */
834
ushort MinBuffers; /* When to get more */
835
ushort MaxBuffers; /* When to stop */
836
ushort PerCpuThreshold;/* See sxgh.h:SXG_RESOURCES */
840
* At the moment I'm going to statically initialize 4 pools:
841
* 100k buffer pool: The vast majority of the expected buffers are expected
842
* to be less than or equal to 100k. At 30 entries per and
843
* 8k initial buffers amounts to ~4MB of memory
844
* NOTE - This used to be 64K with 20 entries, but during
845
* WHQL NDIS 6.0 Testing (2c_mini6stress) MS does their
846
* best to send absurd NBL's with ridiculous SGLs, we
847
* have received 400byte sends contained in SGL's that
849
* 1M buffer pool: Buffers between 64k and 1M. Allocate 256 initial
850
* buffers with 300 entries each => ~2MB of memory
851
* 5M buffer pool: Not expected often, if at all. 32 initial buffers
852
* at 1500 entries each => ~1MB of memory
853
* 10M buffer pool: Not expected at all, except under pathelogical conditions.
854
* Allocate one at initialization time.
855
* Note - 10M is the current limit of what we can realistically
856
* support due to the sahara SGL bug described in the
857
* SAHARA SGL WORKAROUND below. We will likely adjust the
858
* number of pools and/or pool properties over time.
860
#define SXG_NUM_SGL_POOLS 4
861
#define INITIALIZE_SGL_POOL_PROPERTIES \
862
struct sxg_sgl_pool_properties SxgSglPoolProperties[SXG_NUM_SGL_POOLS] =\
864
{ 102400, 30, 8192, 2048, 16384, 256}, \
865
{ 1048576, 300, 256, 128, 1024, 16}, \
866
{ 5252880, 1500, 32, 16, 512, 0}, \
867
{10485760, 2700, 2, 4, 32, 0}, \
870
extern struct sxg_sgl_pool_properties SxgSglPoolProperties[];
872
#define SXG_MAX_SGL_BUFFER_SIZE \
873
SxgSglPoolProperties[SXG_NUM_SGL_POOLS - 1].NBSize
876
* SAHARA SGL WORKAROUND!!
877
* The current Sahara card uses a 16-bit counter when advancing
878
* SGL address locations. This means that if an SGL crosses
879
* a 64k boundary, the hardware will actually skip back to
880
* the start of the previous 64k boundary, with obviously
881
* undesirable results.
883
* We currently workaround this issue by allocating SGL buffers
884
* in 64k blocks and skipping over buffers that straddle the boundary.
886
#define SXG_INVALID_SGL(phys_addr,len) \
887
(((phys_addr >> 16) != ( (phys_addr + len) >> 16 )))
890
* Allocate SGLs in blocks so we can skip over invalid entries.
891
* We allocation 64k worth of SGL buffers, including the
892
* struct sxg_sgl_block_hdr, plus one for padding
894
#define SXG_SGL_BLOCK_SIZE 65536
895
#define SXG_SGL_ALLOCATION_SIZE(_Pool) \
896
SXG_SGL_BLOCK_SIZE + SXG_SGL_SIZE(_Pool)
898
struct sxg_sgl_block_hdr {
899
ushort Pool; /* Associated SGL pool */
900
/* struct sxg_scatter_gather blocks */
901
struct list_entry List;
902
dma64_addr_t PhysicalAddress;/* physical address */
906
* The following definition denotes the maximum block of memory that the
907
* card can DMA to.It is specified in the call to NdisMRegisterScatterGatherDma.
908
* For now, use the same value as used in the Slic/Oasis driver, which
909
* is 128M. That should cover any expected MDL that I can think of.
911
#define SXG_MAX_PHYS_MAP (1024 * 1024 * 128)
913
/* Self identifying structure type */
764
914
enum SXG_SGL_TYPE {
765
SXG_SGL_DUMB, // Dumb NIC SGL
766
SXG_SGL_SLOW, // Slowpath protocol header - see below
767
SXG_SGL_CHIMNEY // Chimney offload SGL
770
// Note - the description below is Microsoft specific
772
// The following definition specifies the amount of shared memory to allocate
773
// for the SCATTER_GATHER_LIST portion of the SXG_SCATTER_GATHER data structure.
774
// The following considerations apply when setting this value:
775
// - First, the Sahara card is designed to read the Microsoft SGL structure
776
// straight out of host memory. This means that the SGL must reside in
777
// shared memory. If the length here is smaller than the SGL for the
778
// NET_BUFFER, then NDIS will allocate its own buffer. The buffer
779
// that NDIS allocates is not in shared memory, so when this happens,
780
// the SGL will need to be copied to a set of SXG_SCATTER_GATHER buffers.
781
// In other words.. we don't want this value to be too small.
782
// - On the other hand.. we're allocating up to 16k of these things. If
783
// we make this too big, we start to consume a ton of memory..
784
// At the moment, I'm going to limit the number of SG entries to 150.
785
// If each entry maps roughly 4k, then this should cover roughly 600kB
786
// NET_BUFFERs. Furthermore, since each entry is 24 bytes, the total
787
// SGE portion of the structure consumes 3600 bytes, which should allow
788
// the entire SXG_SCATTER_GATHER structure to reside comfortably within
789
// a 4k block, providing the remaining fields stay under 500 bytes.
791
// So with 150 entries, the SXG_SCATTER_GATHER structure becomes roughly
792
// 4k. At 16k of them, that amounts to 64M of shared memory. A ton, but
794
#define SXG_SGL_ENTRIES 150
796
// The ucode expects an NDIS SGL structure that
797
// is formatted for an x64 system. When running
798
// on an x64 system, we can simply hand the NDIS SGL
799
// to the card directly. For x86 systems we must reconstruct
800
// the SGL. The following structure defines an x64
801
// formatted SGL entry
803
dma64_addr_t Address; // same as wdm.h
804
u32 Length; // same as wdm.h
805
u32 CompilerPad; // The compiler pads to 8-bytes
806
u64 Reserved; // u32 * in wdm.h. Force to 8 bytes
809
struct SCATTER_GATHER_ELEMENT {
810
dma64_addr_t Address; // same as wdm.h
811
u32 Length; // same as wdm.h
812
u32 CompilerPad; // The compiler pads to 8-bytes
813
u64 Reserved; // u32 * in wdm.h. Force to 8 bytes
816
struct SCATTER_GATHER_LIST {
817
u32 NumberOfElements;
819
struct SCATTER_GATHER_ELEMENT Elements[];
822
// The card doesn't care about anything except elements, so
823
// we can leave the u32 * reserved field alone in the following
824
// SGL structure. But redefine from wdm.h:SCATTER_GATHER_LIST so
825
// we can specify SXG_X64_SGE and define a fixed number of elements
827
u32 NumberOfElements;
829
struct SXG_X64_SGE Elements[SXG_SGL_ENTRIES];
832
struct SXG_SCATTER_GATHER {
833
enum SXG_SGL_TYPE Type; // FIRST! Dumb-nic or offload
834
void *adapter; // Back pointer to adapter
835
struct LIST_ENTRY FreeList; // Free SXG_SCATTER_GATHER blocks
836
struct LIST_ENTRY AllList; // All SXG_SCATTER_GATHER blocks
837
dma_addr_t PhysicalAddress; // physical address
838
unsigned char State; // See SXG_BUFFER state above
839
unsigned char CmdIndex; // Command ring index
840
struct sk_buff *DumbPacket; // Associated Packet
841
u32 Direction; // For asynchronous completions
842
u32 CurOffset; // Current SGL offset
843
u32 SglRef; // SGL reference count
844
struct VLAN_HDR VlanTag; // VLAN tag to be inserted into SGL
845
struct SCATTER_GATHER_LIST *pSgl; // SGL Addr. Possibly &Sgl
846
struct SXG_X64_SGL Sgl; // SGL handed to card
915
SXG_SGL_DUMB, /* Dumb NIC SGL */
916
SXG_SGL_SLOW, /* Slowpath protocol header - see below */
917
SXG_SGL_CHIMNEY /* Chimney offload SGL */
921
* The ucode expects an NDIS SGL structure that
922
* is formatted for an x64 system. When running
923
* on an x64 system, we can simply hand the NDIS SGL
924
* to the card directly. For x86 systems we must reconstruct
925
* the SGL. The following structure defines an x64
926
* formatted SGL entry
929
dma64_addr_t Address; /* same as wdm.h */
930
u32 Length; /* same as wdm.h */
931
u32 CompilerPad; /* The compiler pads to 8-bytes */
932
u64 Reserved; /* u32 * in wdm.h. Force to 8 bytes */
936
* Our SGL structure - Essentially the same as
937
* wdm.h:SCATTER_GATHER_LIST. Note the variable number of
938
* elements based on the pool specified above
941
u32 NumberOfElements;
943
struct sxg_x64_sge Elements[1]; /* Variable */
946
struct sxg_scatter_gather {
947
enum SXG_SGL_TYPE Type; /* FIRST! Dumb-nic or offload */
948
ushort Pool; /* Associated SGL pool */
949
ushort Entries; /* SGL total entries */
950
void * adapter; /* Back pointer to adapter */
951
/* Free struct sxg_scatter_gather blocks */
952
struct list_entry FreeList;
953
/* All struct sxg_scatter_gather blocks */
954
struct list_entry AllList;
955
dma64_addr_t PhysicalAddress;/* physical address */
956
unsigned char State; /* See SXG_BUFFER state above */
957
unsigned char CmdIndex; /* Command ring index */
958
struct sk_buff *DumbPacket; /* Associated Packet */
959
/* For asynchronous completions */
961
u32 CurOffset; /* Current SGL offset */
962
u32 SglRef; /* SGL reference count */
963
struct vlan_hdr VlanTag; /* VLAN tag to be inserted into SGL */
964
struct sxg_x64_sgl *pSgl; /* SGL Addr. Possibly &Sgl */
965
struct sxg_x64_sgl Sgl; /* SGL handed to card */
969
* Note - the "- 1" is because struct sxg_scatter_gather=>struct sxg_x64_sgl
972
#define SXG_SGL_SIZE(_Pool) \
973
(sizeof(struct sxg_scatter_gather) + \
974
((SxgSglPoolProperties[_Pool].SGEntries - 1) * \
975
sizeof(struct sxg_x64_sge)))
977
/* Force NDIS to give us it's own buffer so we can reformat to our own */
978
#define SXG_SGL_BUFFER(_SxgSgl) NULL
979
#define SXG_SGL_BUFFER_LENGTH(_SxgSgl) 0
980
#define SXG_SGL_BUF_SIZE 0
849
983
#if defined(CONFIG_X86_64)
850
#define SXG_SGL_BUFFER(_SxgSgl) (&_SxgSgl->Sgl)
851
#define SXG_SGL_BUF_SIZE sizeof(struct SXG_X64_SGL)
984
#define SXG_SGL_BUFFER(_SxgSgl) (&_SxgSgl->Sgl)
985
#define SXG_SGL_BUFFER_LENGTH(_SxgSgl) ((_SxgSgl)->Entries * \
986
sizeof(struct sxg_x64_sge))
987
#define SXG_SGL_BUF_SIZE sizeof(struct sxg_x64_sgl)
852
988
#elif defined(CONFIG_X86)
853
989
// Force NDIS to give us it's own buffer so we can reformat to our own
854
#define SXG_SGL_BUFFER(_SxgSgl) NULL
990
#define SXG_SGL_BUFFER(_SxgSgl) NULL
991
#define SXG_SGL_BUFFER_LENGTH(_SxgSgl) 0
855
992
#define SXG_SGL_BUF_SIZE 0
857
994
#error staging: sxg: driver is for X86 only!
997
/* Microcode statistics */
998
struct sxg_ucode_stats {
999
u32 RPDQOflow; /* PDQ overflow (unframed ie dq & drop 1st) */
1000
u32 XDrops; /* Xmt drops due to no xmt buffer */
1001
u32 ERDrops; /* Rcv drops due to ER full */
1002
u32 NBDrops; /* Rcv drops due to out of host buffers */
1003
u32 PQDrops; /* Rcv drops due to PDQ full */
1004
/* Rcv drops due to bad frame: no link addr match, frlen > max */
1006
u32 UPDrops; /* Rcv drops due to UPFq full */
1007
u32 XNoBufs; /* Xmt drop due to no DRAM Xmit buffer or PxyBuf */
1011
* Macros for handling the Offload engine values
1013
/* Number of positions to shift Network Header Length before passing to card */
1014
#define SXG_NW_HDR_LEN_SHIFT 2
added
removed
drivers/staging/sxg/sxghif.h
