43
40
#define DEBUG_VAR 1
47
static struct imxfb_rgb def_rgb_16 = {
48
.red = { .offset = 8, .length = 4, },
49
.green = { .offset = 4, .length = 4, },
50
.blue = { .offset = 0, .length = 4, },
51
.transp = { .offset = 0, .length = 0, },
42
#define DRIVER_NAME "imx-fb"
46
#define LCDC_SIZE 0x04
47
#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
49
#ifdef CONFIG_ARCH_MX1
50
#define SIZE_YMAX(y) ((y) & 0x1ff)
52
#define SIZE_YMAX(y) ((y) & 0x3ff)
56
#define VPW_VPW(x) ((x) & 0x3ff)
58
#define LCDC_CPOS 0x0C
59
#define CPOS_CC1 (1<<31)
60
#define CPOS_CC0 (1<<30)
61
#define CPOS_OP (1<<28)
62
#define CPOS_CXP(x) (((x) & 3ff) << 16)
64
#ifdef CONFIG_ARCH_MX1
65
#define CPOS_CYP(y) ((y) & 0x1ff)
67
#define CPOS_CYP(y) ((y) & 0x3ff)
70
#define LCDC_LCWHB 0x10
71
#define LCWHB_BK_EN (1<<31)
72
#define LCWHB_CW(w) (((w) & 0x1f) << 24)
73
#define LCWHB_CH(h) (((h) & 0x1f) << 16)
74
#define LCWHB_BD(x) ((x) & 0xff)
76
#define LCDC_LCHCC 0x14
78
#ifdef CONFIG_ARCH_MX1
79
#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
80
#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
81
#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
83
#define LCHCC_CUR_COL_R(r) (((r) & 0x3f) << 12)
84
#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 6)
85
#define LCHCC_CUR_COL_B(b) ((b) & 0x3f)
91
#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
92
#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
93
#define HCR_H_WAIT_2(x) ((x) & 0xff)
96
#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
97
#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
98
#define VCR_V_WAIT_2(x) ((x) & 0xff)
100
#define LCDC_POS 0x24
101
#define POS_POS(x) ((x) & 1f)
103
#define LCDC_LSCR1 0x28
104
/* bit fields in imxfb.h */
106
#define LCDC_PWMR 0x2C
107
/* bit fields in imxfb.h */
109
#define LCDC_DMACR 0x30
110
/* bit fields in imxfb.h */
112
#define LCDC_RMCR 0x34
114
#ifdef CONFIG_ARCH_MX1
115
#define RMCR_LCDC_EN (1<<1)
117
#define RMCR_LCDC_EN 0
120
#define RMCR_SELF_REF (1<<0)
122
#define LCDC_LCDICR 0x38
123
#define LCDICR_INT_SYN (1<<2)
124
#define LCDICR_INT_CON (1)
126
#define LCDC_LCDISR 0x40
127
#define LCDISR_UDR_ERR (1<<3)
128
#define LCDISR_ERR_RES (1<<2)
129
#define LCDISR_EOF (1<<1)
130
#define LCDISR_BOF (1<<0)
133
* These are the bitfields for each
134
* display depth that we support.
137
struct fb_bitfield red;
138
struct fb_bitfield green;
139
struct fb_bitfield blue;
140
struct fb_bitfield transp;
144
struct platform_device *pdev;
153
* These are the addresses we mapped
154
* the framebuffer memory region to.
161
dma_addr_t screen_dma;
171
u_int cmap_inverse:1,
175
void (*lcd_power)(int);
176
void (*backlight_power)(int);
179
#define IMX_NAME "IMX"
182
* Minimum X and Y resolutions
187
/* Actually this really is 18bit support, the lowest 2 bits of each colour
188
* are unused in hardware. We claim to have 24bit support to make software
189
* like X work, which does not support 18bit.
191
static struct imxfb_rgb def_rgb_18 = {
192
.red = {.offset = 16, .length = 8,},
193
.green = {.offset = 8, .length = 8,},
194
.blue = {.offset = 0, .length = 8,},
195
.transp = {.offset = 0, .length = 0,},
198
static struct imxfb_rgb def_rgb_16_tft = {
199
.red = {.offset = 11, .length = 5,},
200
.green = {.offset = 5, .length = 6,},
201
.blue = {.offset = 0, .length = 5,},
202
.transp = {.offset = 0, .length = 0,},
205
static struct imxfb_rgb def_rgb_16_stn = {
206
.red = {.offset = 8, .length = 4,},
207
.green = {.offset = 4, .length = 4,},
208
.blue = {.offset = 0, .length = 4,},
209
.transp = {.offset = 0, .length = 0,},
54
212
static struct imxfb_rgb def_rgb_8 = {
55
.red = { .offset = 0, .length = 8, },
56
.green = { .offset = 0, .length = 8, },
57
.blue = { .offset = 0, .length = 8, },
58
.transp = { .offset = 0, .length = 0, },
213
.red = {.offset = 0, .length = 8,},
214
.green = {.offset = 0, .length = 8,},
215
.blue = {.offset = 0, .length = 8,},
216
.transp = {.offset = 0, .length = 0,},
61
static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *info);
219
static int imxfb_activate_var(struct fb_var_screeninfo *var,
220
struct fb_info *info);
63
222
static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
340
505
info->fix.id, var->lower_margin);
343
LCDC_HCR = HCR_H_WIDTH(var->hsync_len) |
344
HCR_H_WAIT_1(var->left_margin) |
345
HCR_H_WAIT_2(var->right_margin);
347
LCDC_VCR = VCR_V_WIDTH(var->vsync_len) |
348
VCR_V_WAIT_1(var->upper_margin) |
349
VCR_V_WAIT_2(var->lower_margin);
351
LCDC_SIZE = SIZE_XMAX(var->xres) | SIZE_YMAX(var->yres);
353
LCDC_PWMR = fbi->pwmr;
354
LCDC_LSCR1 = fbi->lscr1;
355
LCDC_DMACR = fbi->dmacr;
508
writel(HCR_H_WIDTH(var->hsync_len - 1) |
509
HCR_H_WAIT_1(var->right_margin - 1) |
510
HCR_H_WAIT_2(var->left_margin - 3),
511
fbi->regs + LCDC_HCR);
513
writel(VCR_V_WIDTH(var->vsync_len) |
514
VCR_V_WAIT_1(var->lower_margin) |
515
VCR_V_WAIT_2(var->upper_margin),
516
fbi->regs + LCDC_VCR);
518
writel(SIZE_XMAX(var->xres) | SIZE_YMAX(var->yres),
519
fbi->regs + LCDC_SIZE);
521
lcd_clk = clk_get_rate(fbi->clk);
522
tmp = var->pixclock * (unsigned long long)lcd_clk;
523
do_div(tmp, 1000000);
524
if (do_div(tmp, 1000000) > 500000)
526
pcr = (unsigned int)tmp;
529
printk(KERN_WARNING "Must limit pixel clock to %uHz\n",
533
/* add sync polarities */
534
pcr |= fbi->pcr & ~0x3F;
536
writel(pcr, fbi->regs + LCDC_PCR);
537
writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
538
writel(fbi->lscr1, fbi->regs + LCDC_LSCR1);
539
writel(fbi->dmacr, fbi->regs + LCDC_DMACR);
360
static void imxfb_setup_gpio(struct imxfb_info *fbi)
364
LCDC_RMCR &= ~(RMCR_LCDC_EN | RMCR_SELF_REF);
366
if( fbi->pcr & PCR_TFT )
369
width = 1 << ((fbi->pcr >> 28) & 0x3);
373
imx_gpio_mode(PD30_PF_LD15);
374
imx_gpio_mode(PD29_PF_LD14);
375
imx_gpio_mode(PD28_PF_LD13);
376
imx_gpio_mode(PD27_PF_LD12);
377
imx_gpio_mode(PD26_PF_LD11);
378
imx_gpio_mode(PD25_PF_LD10);
379
imx_gpio_mode(PD24_PF_LD9);
380
imx_gpio_mode(PD23_PF_LD8);
382
imx_gpio_mode(PD22_PF_LD7);
383
imx_gpio_mode(PD21_PF_LD6);
384
imx_gpio_mode(PD20_PF_LD5);
385
imx_gpio_mode(PD19_PF_LD4);
387
imx_gpio_mode(PD18_PF_LD3);
388
imx_gpio_mode(PD17_PF_LD2);
390
imx_gpio_mode(PD16_PF_LD1);
392
imx_gpio_mode(PD15_PF_LD0);
395
/* initialize GPIOs */
396
imx_gpio_mode(PD6_PF_LSCLK);
397
imx_gpio_mode(PD11_PF_CONTRAST);
398
imx_gpio_mode(PD14_PF_FLM_VSYNC);
399
imx_gpio_mode(PD13_PF_LP_HSYNC);
400
imx_gpio_mode(PD12_PF_ACD_OE);
402
/* These are only needed for Sharp HR TFT displays */
403
if (fbi->pcr & PCR_SHARP) {
404
imx_gpio_mode(PD7_PF_REV);
405
imx_gpio_mode(PD8_PF_CLS);
406
imx_gpio_mode(PD9_PF_PS);
407
imx_gpio_mode(PD10_PF_SPL_SPR);
413
546
* Power management hooks. Note that we won't be called from IRQ context,
435
570
#define imxfb_resume NULL
438
static int __init imxfb_init_fbinfo(struct device *dev)
573
static int __init imxfb_init_fbinfo(struct platform_device *pdev)
440
struct imxfb_mach_info *inf = dev->platform_data;
441
struct fb_info *info = dev_get_drvdata(dev);
575
struct imx_fb_platform_data *pdata = pdev->dev.platform_data;
576
struct fb_info *info = dev_get_drvdata(&pdev->dev);
442
577
struct imxfb_info *fbi = info->par;
444
579
pr_debug("%s\n",__func__);
446
info->pseudo_palette = kmalloc( sizeof(u32) * 16, GFP_KERNEL);
581
info->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL);
447
582
if (!info->pseudo_palette)
450
585
memset(fbi, 0, sizeof(struct imxfb_info));
453
587
strlcpy(info->fix.id, IMX_NAME, sizeof(info->fix.id));
455
info->fix.type = FB_TYPE_PACKED_PIXELS;
589
info->fix.type = FB_TYPE_PACKED_PIXELS;
456
590
info->fix.type_aux = 0;
457
591
info->fix.xpanstep = 0;
458
592
info->fix.ypanstep = 0;
459
593
info->fix.ywrapstep = 0;
460
info->fix.accel = FB_ACCEL_NONE;
594
info->fix.accel = FB_ACCEL_NONE;
462
596
info->var.nonstd = 0;
463
597
info->var.activate = FB_ACTIVATE_NOW;
464
598
info->var.height = -1;
465
599
info->var.width = -1;
466
600
info->var.accel_flags = 0;
467
info->var.vmode = FB_VMODE_NONINTERLACED;
601
info->var.vmode = FB_VMODE_NONINTERLACED;
469
603
info->fbops = &imxfb_ops;
470
info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST;
472
fbi->rgb[RGB_16] = &def_rgb_16;
473
fbi->rgb[RGB_8] = &def_rgb_8;
475
fbi->max_xres = inf->xres;
476
info->var.xres = inf->xres;
477
info->var.xres_virtual = inf->xres;
478
fbi->max_yres = inf->yres;
479
info->var.yres = inf->yres;
480
info->var.yres_virtual = inf->yres;
481
fbi->max_bpp = inf->bpp;
482
info->var.bits_per_pixel = inf->bpp;
483
info->var.nonstd = inf->nonstd;
484
info->var.pixclock = inf->pixclock;
485
info->var.hsync_len = inf->hsync_len;
486
info->var.left_margin = inf->left_margin;
487
info->var.right_margin = inf->right_margin;
488
info->var.vsync_len = inf->vsync_len;
489
info->var.upper_margin = inf->upper_margin;
490
info->var.lower_margin = inf->lower_margin;
491
info->var.sync = inf->sync;
492
info->var.grayscale = inf->cmap_greyscale;
493
fbi->cmap_inverse = inf->cmap_inverse;
494
fbi->cmap_static = inf->cmap_static;
496
fbi->lscr1 = inf->lscr1;
497
fbi->dmacr = inf->dmacr;
498
fbi->pwmr = inf->pwmr;
499
fbi->lcd_power = inf->lcd_power;
500
fbi->backlight_power = inf->backlight_power;
604
info->flags = FBINFO_FLAG_DEFAULT |
607
fbi->max_xres = pdata->xres;
608
info->var.xres = pdata->xres;
609
info->var.xres_virtual = pdata->xres;
610
fbi->max_yres = pdata->yres;
611
info->var.yres = pdata->yres;
612
info->var.yres_virtual = pdata->yres;
613
fbi->max_bpp = pdata->bpp;
614
info->var.bits_per_pixel = pdata->bpp;
615
info->var.nonstd = pdata->nonstd;
616
info->var.pixclock = pdata->pixclock;
617
info->var.hsync_len = pdata->hsync_len;
618
info->var.left_margin = pdata->left_margin;
619
info->var.right_margin = pdata->right_margin;
620
info->var.vsync_len = pdata->vsync_len;
621
info->var.upper_margin = pdata->upper_margin;
622
info->var.lower_margin = pdata->lower_margin;
623
info->var.sync = pdata->sync;
624
info->var.grayscale = pdata->cmap_greyscale;
625
fbi->cmap_inverse = pdata->cmap_inverse;
626
fbi->cmap_static = pdata->cmap_static;
627
fbi->pcr = pdata->pcr;
628
fbi->lscr1 = pdata->lscr1;
629
fbi->dmacr = pdata->dmacr;
630
fbi->pwmr = pdata->pwmr;
631
fbi->lcd_power = pdata->lcd_power;
632
fbi->backlight_power = pdata->backlight_power;
501
633
info->fix.smem_len = fbi->max_xres * fbi->max_yres *
502
634
fbi->max_bpp / 8;
508
* Allocates the DRAM memory for the frame buffer. This buffer is
509
* remapped into a non-cached, non-buffered, memory region to
510
* allow pixel writes to occur without flushing the cache.
511
* Once this area is remapped, all virtual memory access to the
512
* video memory should occur at the new region.
514
static int __init imxfb_map_video_memory(struct fb_info *info)
516
struct imxfb_info *fbi = info->par;
518
fbi->map_size = PAGE_ALIGN(info->fix.smem_len);
519
fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
520
&fbi->map_dma,GFP_KERNEL);
523
info->screen_base = fbi->map_cpu;
524
fbi->screen_cpu = fbi->map_cpu;
525
fbi->screen_dma = fbi->map_dma;
526
info->fix.smem_start = fbi->screen_dma;
529
return fbi->map_cpu ? 0 : -ENOMEM;
532
639
static int __init imxfb_probe(struct platform_device *pdev)
534
641
struct imxfb_info *fbi;
535
642
struct fb_info *info;
536
struct imxfb_mach_info *inf;
643
struct imx_fb_platform_data *pdata;
537
644
struct resource *res;
540
647
printk("i.MX Framebuffer driver\n");
542
649
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
546
inf = pdev->dev.platform_data;
653
pdata = pdev->dev.platform_data;
548
655
dev_err(&pdev->dev,"No platform_data available\n");
552
659
info = framebuffer_alloc(sizeof(struct imxfb_info), &pdev->dev);
558
665
platform_set_drvdata(pdev, info);
560
ret = imxfb_init_fbinfo(&pdev->dev);
667
ret = imxfb_init_fbinfo(pdev);
562
669
goto failed_init;
564
res = request_mem_region(res->start, res->end - res->start + 1, "IMXFB");
671
res = request_mem_region(res->start, resource_size(res),
570
if (!inf->fixed_screen_cpu) {
571
ret = imxfb_map_video_memory(info);
678
fbi->clk = clk_get(&pdev->dev, NULL);
679
if (IS_ERR(fbi->clk)) {
680
ret = PTR_ERR(fbi->clk);;
681
dev_err(&pdev->dev, "unable to get clock: %d\n", ret);
682
goto failed_getclock;
685
fbi->regs = ioremap(res->start, resource_size(res));
686
if (fbi->regs == NULL) {
687
printk(KERN_ERR"Cannot map frame buffer registers\n");
691
if (!pdata->fixed_screen_cpu) {
692
fbi->map_size = PAGE_ALIGN(info->fix.smem_len);
693
fbi->map_cpu = dma_alloc_writecombine(&pdev->dev,
694
fbi->map_size, &fbi->map_dma, GFP_KERNEL);
573
697
dev_err(&pdev->dev, "Failed to allocate video RAM: %d\n", ret);
702
info->screen_base = fbi->map_cpu;
703
fbi->screen_cpu = fbi->map_cpu;
704
fbi->screen_dma = fbi->map_dma;
705
info->fix.smem_start = fbi->screen_dma;
578
707
/* Fixed framebuffer mapping enables location of the screen in eSRAM */
579
fbi->map_cpu = inf->fixed_screen_cpu;
580
fbi->map_dma = inf->fixed_screen_dma;
708
fbi->map_cpu = pdata->fixed_screen_cpu;
709
fbi->map_dma = pdata->fixed_screen_dma;
581
710
info->screen_base = fbi->map_cpu;
582
711
fbi->screen_cpu = fbi->map_cpu;
583
712
fbi->screen_dma = fbi->map_dma;
584
713
info->fix.smem_start = fbi->screen_dma;
717
ret = pdata->init(fbi->pdev);
719
goto failed_platform_init;
588
723
* This makes sure that our colour bitfield
589
724
* descriptors are correctly initialised.
591
726
imxfb_check_var(&info->var, info);
593
ret = fb_alloc_cmap(&info->cmap, 1<<info->var.bits_per_pixel, 0);
728
ret = fb_alloc_cmap(&info->cmap, 1 << info->var.bits_per_pixel, 0);
595
730
goto failed_cmap;
597
imxfb_setup_gpio(fbi);
599
732
imxfb_set_par(info);
600
733
ret = register_framebuffer(info);