203
203
/** Bit 0 - SSE3 - Supports SSE3 or not. */
204
204
unsigned u1SSE3 : 1;
206
unsigned u2Reserved1 : 2;
206
unsigned u1Reserved1 : 1;
207
/** Bit 2 - DS Area 64-bit layout. */
208
unsigned u1DTE64 : 1;
207
209
/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
208
210
unsigned u1Monitor : 1;
209
211
/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
210
212
unsigned u1CPLDS : 1;
211
213
/** Bit 5 - VMX - Virtual Machine Technology. */
212
214
unsigned u1VMX : 1;
214
unsigned u1Reserved2 : 1;
215
/** Bit 6 - SMX: Safer Mode Extensions. */
215
217
/** Bit 7 - EST - Enh. SpeedStep Tech. */
216
218
unsigned u1EST : 1;
217
219
/** Bit 8 - TM2 - Terminal Monitor 2. */
221
223
/** Bit 10 - CNTX-ID - L1 Context ID. */
222
224
unsigned u1CNTXID : 1;
224
unsigned u2Reserved4 : 2;
226
unsigned u2Reserved2 : 2;
225
227
/** Bit 13 - CX16 - CMPXCHG16B. */
226
228
unsigned u1CX16 : 1;
227
229
/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
228
230
unsigned u1TPRUpdate : 1;
230
unsigned u17Reserved5 : 17;
231
/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
234
unsigned u2Reserved3 : 2;
235
/** Bit 18 - Direct Cache Access. */
237
/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
238
unsigned u1SSE4_1 : 1;
239
/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
240
unsigned u1SSE4_2 : 1;
241
/** Bit 21 - x2APIC. */
242
unsigned u1x2APIC : 1;
243
/** Bit 22 - MOVBE - Supports MOVBE. */
244
unsigned u1MOVBE : 1;
245
/** Bit 23 - POPCNT - Supports POPCNT. */
246
unsigned u1POPCNT : 1;
248
unsigned u2Reserved4 : 2;
249
/** Bit 26 - XSAVE - Supports XSAVE. */
250
unsigned u1XSAVE : 1;
251
/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
252
unsigned u1OSXSAVE : 1;
254
unsigned u4Reserved5 : 4;
232
255
} X86CPUIDFEATECX;
233
256
/** Pointer to CPUID Feature Information - ECX. */
234
257
typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
332
355
/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
333
356
#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
357
/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
358
#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
334
359
/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
335
360
#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
336
361
/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
337
362
#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
338
363
/** ECX Bit 5 - VMX - Virtual Machine Technology. */
339
364
#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
365
/** ECX Bit 6 - SMX - Safer Mode Extensions. */
366
#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
340
367
/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
341
368
#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
342
369
/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
349
376
#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
350
377
/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
351
378
#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
379
/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
380
#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
381
/** ECX Bit 18 - DCA - Direct Cache Access. */
382
#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
383
/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
384
#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
385
/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
386
#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
352
387
/** ECX Bit 21 - x2APIC support. */
353
388
#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
389
/** ECX Bit 22 - MOVBE instruction. */
390
#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
354
391
/** ECX Bit 23 - POPCOUNT instruction. */
355
392
#define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
393
/** ECX Bit 26 - XSAVE instruction. */
394
#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
395
/** ECX Bit 27 - OSXSAVE instruction. */
396
#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
358
399
/** Bit 0 - FPU - x87 FPU on Chip. */
2219
2260
/** Pointer to const descriptor table entry. */
2220
2261
typedef const X86DESC64 *PCX86DESC64;
2222
#if HC_ARCH_BITS == 64
2223
typedef X86DESC64 X86DESCHC;
2224
typedef X86DESC64 *PX86DESCHC;
2226
typedef X86DESC X86DESCHC;
2227
typedef X86DESC *PX86DESCHC;
2230
2263
/** @def X86DESC64_BASE
2231
2264
* Return the base of a 64-bit descriptor.
2233
#define X86DESC64_BASE(desc) \
2266
#define X86DESC64_BASE(desc) /*ASM-NOINC*/ \
2234
2267
( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2235
2268
| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2236
2269
| ( (desc).Gen.u8BaseHigh1 << 16) \
2237
2270
| ( (desc).Gen.u16BaseLow ) )
2274
/** @name Host system descriptor table entry - Use with care!
2276
/** Host system descriptor table entry. */
2277
#if HC_ARCH_BITS == 64
2278
typedef X86DESC64 X86DESCHC;
2280
typedef X86DESC X86DESCHC;
2282
/** Pointer to a host system descriptor table entry. */
2283
#if HC_ARCH_BITS == 64
2284
typedef PX86DESC64 PX86DESCHC;
2286
typedef PX86DESC PX86DESCHC;
2288
/** Pointer to a const host system descriptor table entry. */
2289
#if HC_ARCH_BITS == 64
2290
typedef PCX86DESC64 PCX86DESCHC;
2292
typedef PCX86DESC PCX86DESCHC;
2240
2297
/** @name Selector Descriptor Types.
2504
2561
#define X86_SEL_SHIFT 3
2507
* The shift used to convert a selector from and to index an index (C).
2509
#define AMD64_SEL_SHIFT 4
2511
/** @def X86_SEL_SHIFT_HC
2512
* This is for use with X86DESCHC. */
2513
#if HC_ARCH_BITS == 64
2514
#define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
2516
#define X86_SEL_SHIFT_HC X86_SEL_SHIFT
2520
2564
* The mask used to mask off the table indicator and CPL of an selector.
2522
2566
#define X86_SEL_MASK 0xfff8