1
/* mach64_drm.h -- Public header for the mach64 driver -*- linux-c -*-
2
* Created: Thu Nov 30 20:04:32 2000 by gareth@valinux.com
5
* Copyright 2000 Gareth Hughes
6
* Copyright 2002 Frank C. Earl
7
* Copyright 2002-2003 Leif Delgass
10
* Permission is hereby granted, free of charge, to any person obtaining a
11
* copy of this software and associated documentation files (the "Software"),
12
* to deal in the Software without restriction, including without limitation
13
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
14
* and/or sell copies of the Software, and to permit persons to whom the
15
* Software is furnished to do so, subject to the following conditions:
17
* The above copyright notice and this permission notice (including the next
18
* paragraph) shall be included in all copies or substantial portions of the
21
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
22
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
23
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
24
* THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
25
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
26
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29
* Gareth Hughes <gareth@valinux.com>
30
* Frank C. Earl <fearl@airmail.net>
31
* Leif Delgass <ldelgass@retinalburn.net>
34
#ifndef __MACH64_DRM_H__
35
#define __MACH64_DRM_H__
37
/* WARNING: If you change any of these defines, make sure to change the
38
* defines in the Xserver file (mach64_sarea.h)
40
#ifndef __MACH64_SAREA_DEFINES__
41
#define __MACH64_SAREA_DEFINES__
43
/* What needs to be changed for the current vertex buffer?
44
* GH: We're going to be pedantic about this. We want the card to do as
45
* little as possible, so let's avoid having it fetch a whole bunch of
46
* register values that don't change all that often, if at all.
48
#define MACH64_UPLOAD_DST_OFF_PITCH 0x0001
49
#define MACH64_UPLOAD_Z_OFF_PITCH 0x0002
50
#define MACH64_UPLOAD_Z_ALPHA_CNTL 0x0004
51
#define MACH64_UPLOAD_SCALE_3D_CNTL 0x0008
52
#define MACH64_UPLOAD_DP_FOG_CLR 0x0010
53
#define MACH64_UPLOAD_DP_WRITE_MASK 0x0020
54
#define MACH64_UPLOAD_DP_PIX_WIDTH 0x0040
55
#define MACH64_UPLOAD_SETUP_CNTL 0x0080
56
#define MACH64_UPLOAD_MISC 0x0100
57
#define MACH64_UPLOAD_TEXTURE 0x0200
58
#define MACH64_UPLOAD_TEX0IMAGE 0x0400
59
#define MACH64_UPLOAD_TEX1IMAGE 0x0800
60
#define MACH64_UPLOAD_CLIPRECTS 0x1000 /* handled client-side */
61
#define MACH64_UPLOAD_CONTEXT 0x00ff
62
#define MACH64_UPLOAD_ALL 0x1fff
66
#define MACH64_BUFFER_SIZE 16384
68
/* Max number of swaps allowed on the ring
69
* before the client must wait
71
#define MACH64_MAX_QUEUED_FRAMES 3
73
/* Byte offsets for host blit buffer data
75
#define MACH64_HOSTDATA_BLIT_OFFSET 104
77
/* Keep these small for testing.
79
#define MACH64_NR_SAREA_CLIPRECTS 8
81
#define MACH64_CARD_HEAP 0
82
#define MACH64_AGP_HEAP 1
83
#define MACH64_NR_TEX_HEAPS 2
84
#define MACH64_NR_TEX_REGIONS 64
85
#define MACH64_LOG_TEX_GRANULARITY 16
87
#define MACH64_TEX_MAXLEVELS 1
89
#define MACH64_NR_CONTEXT_REGS 15
90
#define MACH64_NR_TEXTURE_REGS 4
92
#endif /* __MACH64_SAREA_DEFINES__ */
95
unsigned int dst_off_pitch;
97
unsigned int z_off_pitch;
99
unsigned int alpha_tst_cntl;
101
unsigned int scale_3d_cntl;
103
unsigned int sc_left_right;
104
unsigned int sc_top_bottom;
106
unsigned int dp_fog_clr;
107
unsigned int dp_write_mask;
108
unsigned int dp_pix_width;
112
unsigned int clr_cmp_cntl;
113
unsigned int gui_traj_cntl;
115
unsigned int setup_cntl;
117
unsigned int tex_size_pitch;
118
unsigned int tex_cntl;
119
unsigned int secondary_tex_off;
120
unsigned int tex_offset;
121
} drm_mach64_context_regs_t;
123
typedef struct drm_mach64_sarea {
124
/* The channel for communication of state information to the kernel
125
* on firing a vertex dma buffer.
127
drm_mach64_context_regs_t context_state;
129
unsigned int vertsize;
131
/* The current cliprects, or a subset thereof.
133
drm_clip_rect_t boxes[MACH64_NR_SAREA_CLIPRECTS];
136
/* Counters for client-side throttling of rendering clients.
138
unsigned int frames_queued;
140
/* Texture memory LRU.
142
drm_tex_region_t tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS +
144
unsigned int tex_age[MACH64_NR_TEX_HEAPS];
146
} drm_mach64_sarea_t;
148
/* WARNING: If you change any of these defines, make sure to change the
149
* defines in the Xserver file (mach64_common.h)
152
/* Mach64 specific ioctls
153
* The device specific ioctl range is 0x40 to 0x79.
156
#define DRM_MACH64_INIT 0x00
157
#define DRM_MACH64_IDLE 0x01
158
#define DRM_MACH64_RESET 0x02
159
#define DRM_MACH64_SWAP 0x03
160
#define DRM_MACH64_CLEAR 0x04
161
#define DRM_MACH64_VERTEX 0x05
162
#define DRM_MACH64_BLIT 0x06
163
#define DRM_MACH64_FLUSH 0x07
164
#define DRM_MACH64_GETPARAM 0x08
166
#define DRM_IOCTL_MACH64_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_INIT, drm_mach64_init_t)
167
#define DRM_IOCTL_MACH64_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_IDLE )
168
#define DRM_IOCTL_MACH64_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_RESET )
169
#define DRM_IOCTL_MACH64_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_SWAP )
170
#define DRM_IOCTL_MACH64_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_CLEAR, drm_mach64_clear_t)
171
#define DRM_IOCTL_MACH64_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_VERTEX, drm_mach64_vertex_t)
172
#define DRM_IOCTL_MACH64_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_BLIT, drm_mach64_blit_t)
173
#define DRM_IOCTL_MACH64_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_FLUSH )
174
#define DRM_IOCTL_MACH64_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_MACH64_GETPARAM, drm_mach64_getparam_t)
176
/* Buffer flags for clears
178
#define MACH64_FRONT 0x1
179
#define MACH64_BACK 0x2
180
#define MACH64_DEPTH 0x4
182
/* Primitive types for vertex buffers
184
#define MACH64_PRIM_POINTS 0x00000000
185
#define MACH64_PRIM_LINES 0x00000001
186
#define MACH64_PRIM_LINE_LOOP 0x00000002
187
#define MACH64_PRIM_LINE_STRIP 0x00000003
188
#define MACH64_PRIM_TRIANGLES 0x00000004
189
#define MACH64_PRIM_TRIANGLE_STRIP 0x00000005
190
#define MACH64_PRIM_TRIANGLE_FAN 0x00000006
191
#define MACH64_PRIM_QUADS 0x00000007
192
#define MACH64_PRIM_QUAD_STRIP 0x00000008
193
#define MACH64_PRIM_POLYGON 0x00000009
195
typedef enum _drm_mach64_dma_mode_t {
196
MACH64_MODE_DMA_ASYNC,
197
MACH64_MODE_DMA_SYNC,
199
} drm_mach64_dma_mode_t;
201
typedef struct drm_mach64_init {
203
DRM_MACH64_INIT_DMA = 0x01,
204
DRM_MACH64_CLEANUP_DMA = 0x02
207
unsigned long sarea_priv_offset;
209
drm_mach64_dma_mode_t dma_mode;
212
unsigned int front_offset, front_pitch;
213
unsigned int back_offset, back_pitch;
215
unsigned int depth_bpp;
216
unsigned int depth_offset, depth_pitch;
218
unsigned long fb_offset;
219
unsigned long mmio_offset;
220
unsigned long ring_offset;
221
unsigned long buffers_offset;
222
unsigned long agp_textures_offset;
225
typedef struct drm_mach64_clear {
228
unsigned int clear_color;
229
unsigned int clear_depth;
230
} drm_mach64_clear_t;
232
typedef struct drm_mach64_vertex {
234
void *buf; /* Address of vertex buffer */
235
unsigned long used; /* Number of bytes in buffer */
236
int discard; /* Client finished with buffer? */
237
} drm_mach64_vertex_t;
239
typedef struct drm_mach64_blit {
245
unsigned short width, height;
248
typedef struct drm_mach64_getparam {
250
MACH64_PARAM_FRAMES_QUEUED = 0x01,
251
MACH64_PARAM_IRQ_NR = 0x02
254
} drm_mach64_getparam_t;