42
42
static struct rc_instruction *emit1(
43
43
struct radeon_compiler * c, struct rc_instruction * after,
44
rc_opcode Opcode, rc_saturate_mode Saturate, struct rc_dst_register DstReg,
45
struct rc_src_register SrcReg)
44
rc_opcode Opcode, struct rc_sub_instruction * base,
45
struct rc_dst_register DstReg, struct rc_src_register SrcReg)
47
47
struct rc_instruction *fpi = rc_insert_new_instruction(c, after);
50
memcpy(&fpi->U.I, base, sizeof(struct rc_sub_instruction));
49
53
fpi->U.I.Opcode = Opcode;
50
fpi->U.I.SaturateMode = Saturate;
51
54
fpi->U.I.DstReg = DstReg;
52
55
fpi->U.I.SrcReg[0] = SrcReg;
56
59
static struct rc_instruction *emit2(
57
60
struct radeon_compiler * c, struct rc_instruction * after,
58
rc_opcode Opcode, rc_saturate_mode Saturate, struct rc_dst_register DstReg,
61
rc_opcode Opcode, struct rc_sub_instruction * base,
62
struct rc_dst_register DstReg,
59
63
struct rc_src_register SrcReg0, struct rc_src_register SrcReg1)
61
65
struct rc_instruction *fpi = rc_insert_new_instruction(c, after);
68
memcpy(&fpi->U.I, base, sizeof(struct rc_sub_instruction));
63
71
fpi->U.I.Opcode = Opcode;
64
fpi->U.I.SaturateMode = Saturate;
65
72
fpi->U.I.DstReg = DstReg;
66
73
fpi->U.I.SrcReg[0] = SrcReg0;
67
74
fpi->U.I.SrcReg[1] = SrcReg1;
71
78
static struct rc_instruction *emit3(
72
79
struct radeon_compiler * c, struct rc_instruction * after,
73
rc_opcode Opcode, rc_saturate_mode Saturate, struct rc_dst_register DstReg,
80
rc_opcode Opcode, struct rc_sub_instruction * base,
81
struct rc_dst_register DstReg,
74
82
struct rc_src_register SrcReg0, struct rc_src_register SrcReg1,
75
83
struct rc_src_register SrcReg2)
77
85
struct rc_instruction *fpi = rc_insert_new_instruction(c, after);
88
memcpy(&fpi->U.I, base, sizeof(struct rc_sub_instruction));
79
91
fpi->U.I.Opcode = Opcode;
80
fpi->U.I.SaturateMode = Saturate;
81
92
fpi->U.I.DstReg = DstReg;
82
93
fpi->U.I.SrcReg[0] = SrcReg0;
83
94
fpi->U.I.SrcReg[1] = SrcReg1;
221
232
struct rc_src_register src = inst->U.I.SrcReg[0];
223
234
src.Negate = RC_MASK_NONE;
224
emit1(c, inst->Prev, RC_OPCODE_MOV, inst->U.I.SaturateMode, inst->U.I.DstReg, src);
235
emit1(c, inst->Prev, RC_OPCODE_MOV, &inst->U.I, inst->U.I.DstReg, src);
225
236
rc_remove_instruction(inst);
241
252
struct rc_dst_register dst = try_to_reuse_dst(c, inst);
242
253
emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dst, negate(inst->U.I.SrcReg[0]));
243
emit2(c, inst->Prev, RC_OPCODE_ADD, inst->U.I.SaturateMode, inst->U.I.DstReg,
254
emit2(c, inst->Prev, RC_OPCODE_ADD, &inst->U.I, inst->U.I.DstReg,
244
255
inst->U.I.SrcReg[0], srcreg(RC_FILE_TEMPORARY, dst.Index));
245
256
rc_remove_instruction(inst);
256
267
struct rc_dst_register dst = try_to_reuse_dst(c, inst);
257
268
emit2(c, inst->Prev, RC_OPCODE_MIN, 0, dst,
258
269
inst->U.I.SrcReg[0], inst->U.I.SrcReg[2]);
259
emit2(c, inst->Prev, RC_OPCODE_MAX, inst->U.I.SaturateMode, inst->U.I.DstReg,
270
emit2(c, inst->Prev, RC_OPCODE_MAX, &inst->U.I, inst->U.I.DstReg,
260
271
srcreg(RC_FILE_TEMPORARY, dst.Index), inst->U.I.SrcReg[1]);
261
272
rc_remove_instruction(inst);
272
283
src1.Negate &= ~(RC_MASK_Z | RC_MASK_W);
273
284
src1.Swizzle &= ~(63 << (3 * 2));
274
285
src1.Swizzle |= (RC_SWIZZLE_ZERO << (3 * 2)) | (RC_SWIZZLE_ZERO << (3 * 3));
275
emit2(c, inst->Prev, RC_OPCODE_DP3, inst->U.I.SaturateMode, inst->U.I.DstReg, src0, src1);
286
emit2(c, inst->Prev, RC_OPCODE_DP3, &inst->U.I, inst->U.I.DstReg, src0, src1);
276
287
rc_remove_instruction(inst);
283
294
src0.Negate &= ~RC_MASK_W;
284
295
src0.Swizzle &= ~(7 << (3 * 3));
285
296
src0.Swizzle |= RC_SWIZZLE_ONE << (3 * 3);
286
emit2(c, inst->Prev, RC_OPCODE_DP4, inst->U.I.SaturateMode, inst->U.I.DstReg, src0, inst->U.I.SrcReg[1]);
297
emit2(c, inst->Prev, RC_OPCODE_DP4, &inst->U.I, inst->U.I.DstReg, src0, inst->U.I.SrcReg[1]);
287
298
rc_remove_instruction(inst);
294
305
static void transform_DST(struct radeon_compiler* c,
295
306
struct rc_instruction* inst)
297
emit2(c, inst->Prev, RC_OPCODE_MUL, inst->U.I.SaturateMode, inst->U.I.DstReg,
308
emit2(c, inst->Prev, RC_OPCODE_MUL, &inst->U.I, inst->U.I.DstReg,
298
309
swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_ONE, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_ONE),
299
310
swizzle(inst->U.I.SrcReg[1], RC_SWIZZLE_ONE, RC_SWIZZLE_Y, RC_SWIZZLE_ONE, RC_SWIZZLE_W));
300
311
rc_remove_instruction(inst);
306
317
struct rc_dst_register dst = try_to_reuse_dst(c, inst);
307
318
emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dst, inst->U.I.SrcReg[0]);
308
emit2(c, inst->Prev, RC_OPCODE_ADD, inst->U.I.SaturateMode, inst->U.I.DstReg,
319
emit2(c, inst->Prev, RC_OPCODE_ADD, &inst->U.I, inst->U.I.DstReg,
309
320
inst->U.I.SrcReg[0], negate(srcreg(RC_FILE_TEMPORARY, dst.Index)));
310
321
rc_remove_instruction(inst);
379
390
swizzle_wwww(srctemp));
381
392
/* tmp.z = (tmp.x > 0) ? tmp.w : 0.0 */
382
emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode,
393
emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I,
383
394
dstregtmpmask(temp, RC_MASK_Z),
384
395
negate(swizzle_xxxx(srctemp)),
385
396
swizzle_wwww(srctemp),
388
399
/* tmp.x, tmp.y, tmp.w = 1.0, tmp.x, 1.0 */
389
emit1(c, inst->Prev, RC_OPCODE_MOV, inst->U.I.SaturateMode,
400
emit1(c, inst->Prev, RC_OPCODE_MOV, &inst->U.I,
390
401
dstregtmpmask(temp, RC_MASK_XYW),
391
402
swizzle(srctemp, RC_SWIZZLE_ONE, RC_SWIZZLE_X, RC_SWIZZLE_ONE, RC_SWIZZLE_ONE));
401
412
emit2(c, inst->Prev, RC_OPCODE_ADD, 0,
403
414
inst->U.I.SrcReg[1], negate(inst->U.I.SrcReg[2]));
404
emit3(c, inst->Prev, RC_OPCODE_MAD, inst->U.I.SaturateMode,
415
emit3(c, inst->Prev, RC_OPCODE_MAD, &inst->U.I,
405
416
inst->U.I.DstReg,
406
417
inst->U.I.SrcReg[0], srcreg(RC_FILE_TEMPORARY, dst.Index), inst->U.I.SrcReg[2]);
419
430
emit1(c, inst->Prev, RC_OPCODE_LG2, 0, tempdst, swizzle_xxxx(inst->U.I.SrcReg[0]));
420
431
emit2(c, inst->Prev, RC_OPCODE_MUL, 0, tempdst, tempsrc, swizzle_xxxx(inst->U.I.SrcReg[1]));
421
emit1(c, inst->Prev, RC_OPCODE_EX2, inst->U.I.SaturateMode, inst->U.I.DstReg, tempsrc);
432
emit1(c, inst->Prev, RC_OPCODE_EX2, &inst->U.I, inst->U.I.DstReg, tempsrc);
423
434
rc_remove_instruction(inst);
472
483
struct rc_dst_register dst = try_to_reuse_dst(c, inst);
474
485
emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dst, inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
475
emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
486
emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
476
487
negate(absolute(srcreg(RC_FILE_TEMPORARY, dst.Index))), builtin_zero, builtin_one);
478
489
rc_remove_instruction(inst);
481
492
static void transform_SFL(struct radeon_compiler* c,
482
493
struct rc_instruction* inst)
484
emit1(c, inst->Prev, RC_OPCODE_MOV, inst->U.I.SaturateMode, inst->U.I.DstReg, builtin_zero);
495
emit1(c, inst->Prev, RC_OPCODE_MOV, &inst->U.I, inst->U.I.DstReg, builtin_zero);
485
496
rc_remove_instruction(inst);
491
502
struct rc_dst_register dst = try_to_reuse_dst(c, inst);
493
504
emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dst, inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
494
emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
505
emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
495
506
srcreg(RC_FILE_TEMPORARY, dst.Index), builtin_zero, builtin_one);
497
508
rc_remove_instruction(inst);
503
514
struct rc_dst_register dst = try_to_reuse_dst(c, inst);
505
516
emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dst, negate(inst->U.I.SrcReg[0]), inst->U.I.SrcReg[1]);
506
emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
517
emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
507
518
srcreg(RC_FILE_TEMPORARY, dst.Index), builtin_one, builtin_zero);
509
520
rc_remove_instruction(inst);
515
526
struct rc_dst_register dst = try_to_reuse_dst(c, inst);
517
528
emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dst, negate(inst->U.I.SrcReg[0]), inst->U.I.SrcReg[1]);
518
emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
529
emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
519
530
srcreg(RC_FILE_TEMPORARY, dst.Index), builtin_zero, builtin_one);
521
532
rc_remove_instruction(inst);
527
538
struct rc_dst_register dst = try_to_reuse_dst(c, inst);
529
540
emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dst, inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
530
emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
541
emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
531
542
srcreg(RC_FILE_TEMPORARY, dst.Index), builtin_one, builtin_zero);
533
544
rc_remove_instruction(inst);
539
550
struct rc_dst_register dst = try_to_reuse_dst(c, inst);
541
552
emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dst, inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
542
emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
553
emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
543
554
negate(absolute(srcreg(RC_FILE_TEMPORARY, dst.Index))), builtin_one, builtin_zero);
545
556
rc_remove_instruction(inst);
604
615
emit2(c, inst->Prev, RC_OPCODE_MUL, 0, dst,
605
616
swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_W),
606
617
swizzle(inst->U.I.SrcReg[1], RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_W));
607
emit3(c, inst->Prev, RC_OPCODE_MAD, inst->U.I.SaturateMode, inst->U.I.DstReg,
618
emit3(c, inst->Prev, RC_OPCODE_MAD, &inst->U.I, inst->U.I.DstReg,
608
619
swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_W),
609
620
swizzle(inst->U.I.SrcReg[1], RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_W),
610
621
negate(srcreg(RC_FILE_TEMPORARY, dst.Index)));
719
730
src1.Negate &= ~RC_MASK_W;
720
731
src1.Swizzle &= ~(7 << (3 * 3));
721
732
src1.Swizzle |= RC_SWIZZLE_ZERO << (3 * 3);
722
emit2(c, inst->Prev, RC_OPCODE_DP4, inst->U.I.SaturateMode, inst->U.I.DstReg, src0, src1);
733
emit2(c, inst->Prev, RC_OPCODE_DP4, &inst->U.I, inst->U.I.DstReg, src0, src1);
723
734
rc_remove_instruction(inst);
1043
1054
unsigned srctmp)
1045
1056
if (inst->U.I.Opcode == RC_OPCODE_COS) {
1046
emit1(c, inst->Prev, RC_OPCODE_COS, inst->U.I.SaturateMode, inst->U.I.DstReg,
1057
emit1(c, inst->Prev, RC_OPCODE_COS, &inst->U.I, inst->U.I.DstReg,
1047
1058
srcregswz(RC_FILE_TEMPORARY, srctmp, RC_SWIZZLE_WWWW));
1048
1059
} else if (inst->U.I.Opcode == RC_OPCODE_SIN) {
1049
emit1(c, inst->Prev, RC_OPCODE_SIN, inst->U.I.SaturateMode,
1060
emit1(c, inst->Prev, RC_OPCODE_SIN, &inst->U.I,
1050
1061
inst->U.I.DstReg, srcregswz(RC_FILE_TEMPORARY, srctmp, RC_SWIZZLE_WWWW));
1051
1062
} else if (inst->U.I.Opcode == RC_OPCODE_SCS) {
1052
1063
struct rc_dst_register moddst = inst->U.I.DstReg;
1054
1065
if (inst->U.I.DstReg.WriteMask & RC_MASK_X) {
1055
1066
moddst.WriteMask = RC_MASK_X;
1056
emit1(c, inst->Prev, RC_OPCODE_COS, inst->U.I.SaturateMode, moddst,
1067
emit1(c, inst->Prev, RC_OPCODE_COS, &inst->U.I, moddst,
1057
1068
srcregswz(RC_FILE_TEMPORARY, srctmp, RC_SWIZZLE_WWWW));
1059
1070
if (inst->U.I.DstReg.WriteMask & RC_MASK_Y) {
1060
1071
moddst.WriteMask = RC_MASK_Y;
1061
emit1(c, inst->Prev, RC_OPCODE_SIN, inst->U.I.SaturateMode, moddst,
1072
emit1(c, inst->Prev, RC_OPCODE_SIN, &inst->U.I, moddst,
1062
1073
srcregswz(RC_FILE_TEMPORARY, srctmp, RC_SWIZZLE_WWWW));