3
3
;==========================================================================
4
; $Id: p18f4580.inc,v 1.1 2004/07/24 03:00:02 craigfranklin Exp $
4
; $Id: p18f4580.inc,v 1.3 2005/03/24 04:08:44 craigfranklin Exp $
5
5
; MPASM PIC18F4580 processor include
7
; (c) Copyright 1999-2004 Microchip Technology, All rights reserved
7
; (c) Copyright 1999-2005 Microchip Technology, All rights reserved
8
8
;==========================================================================
4325
4319
__BADRAM H'0F8E'-H'0F91'
4326
4320
__BADRAM H'0F97'-H'0F9A'
4327
4321
__BADRAM H'0F9C'
4328
4323
__BADRAM H'0FB9'
4329
4324
__BADRAM H'0FD4'
4331
4326
;==========================================================================
4328
; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been
4329
; superseded by the CONFIG directive. The following settings
4330
; are available for this device.
4332
; Oscillator Selection bits:
4336
; OSC = RC External RC with OSC2 as divide by 4 clock out
4337
; OSC = EC EC with OSC2 as divide by 4 clock out
4338
; OSC = ECIO EC with OSC2 as RA6
4339
; OSC = HSPLL HS with HW enabled 4xPLL
4340
; OSC = RCIO External RC with OSC2 as RA6
4341
; OSC = IRCIO67 Internal RC with OSC2 as RA6 and OSC1 as RA7
4342
; OSC = IRCIO7 Internal RC with OSC1 as RA7 and OSC2 as divide by 4 clock out
4343
; OSC = ERC1 External RC with OSC2 as divide by 4 clock out
4344
; OSC = ERC External RC with OSC2 as divide by 4 clock out
4346
; Fail Safe Clock Monitor:
4347
; FCMENB = OFF Disabled
4348
; FCMENB = ON Enabled
4350
; Internal External Osc. Switch:
4351
; IESOB = OFF Disabled
4352
; IESOB = ON Enabled
4356
; PWRT = OFF Disabled
4359
; BOR = OFF Disabled
4360
; BOR = SBORENCTRL Controlled by SBOREN
4361
; BOR = BOACTIVE Enabled whenever Part is Active - SBOREN Disabled
4362
; BOR = BOHW Enabled in HW, SBOREN disabled
4364
; Brown Out Voltage:
4371
; WDT = OFF HW Disabled - SW Controlled
4372
; WDT = ON HW Enabled - SW Disabled
4374
; Watchdog Postscaler:
4385
; WDTPS = 1024 1:1024
4386
; WDTPS = 2048 1:2048
4387
; WDTPS = 4096 1:4096
4388
; WDTPS = 8192 1:8192
4389
; WDTPS = 16384 1:16384
4390
; WDTPS = 32768 1:32768
4393
; MCLRE = OFF Disabled
4394
; MCLRE = ON Enabled
4396
; Low Power Timer1 Oscillator:
4397
; LPT1OSC = OFF Timer1 Low Power Oscillator disabled
4398
; LPT1OSC = ON Timer1 Low Power Oscillator Active
4400
; Port B Pins Configured for A/D:
4401
; PBADEN = OFF Port B<4> and Port B<1:0> Configured as Digital I/O Pins on Reset
4402
; PBADEN = ON Port B<4> and Port B<1:0> Configured as Analog Pins on Reset
4405
; DEBUG = ON Enabled
4406
; DEBUG = OFF Disabled
4408
; Extended Instruction Set CPU:
4409
; XINST = OFF Disabled
4410
; XINST = ON Enabled
4413
; BBSIZ = 1024 1K words (2K bytes) Boot Block
4414
; BBSIZ = 2048 2K words (4K bytes) Boot Block
4416
; Low Voltage Programming:
4417
; LVP = OFF Disabled
4420
; Stack Overflow/Underflow Reset:
4421
; STVREN = OFF Disabled
4422
; STVREN = ON Enabled
4424
; Code Protection Block 0:
4426
; CP0 = OFF Disabled
4428
; Code Protection Block 1:
4430
; CP1 = OFF Disabled
4432
; Code Protection Block 2:
4434
; CP2 = OFF Disabled
4436
; Code Protection Block 3:
4438
; CP3 = OFF Disabled
4440
; Boot Block Code Protection:
4442
; CPB = OFF Disabled
4444
; Data EEPROM Code Protection:
4446
; CPD = OFF Disabled
4448
; Write Protection Block 0:
4450
; WRT0 = OFF Disabled
4452
; Write Protection Block 1:
4454
; WRT1 = OFF Disabled
4456
; Write Protection Block 2:
4458
; WRT2 = OFF Disabled
4460
; Write Protection Block 3:
4462
; WRT3 = OFF Disabled
4464
; Boot Block Write Protection:
4466
; WRTB = OFF Disabled
4468
; Configuration Register Write Protection:
4470
; WRTC = OFF Disabled
4472
; Data EEPROM Write Protection:
4474
; WRTD = OFF Disabled
4476
; Table Read Protection Block 0:
4477
; EBTR0 = ON Enabled
4478
; EBTR0 = OFF Disabled
4480
; Table Read Protection Block 1:
4481
; EBTR1 = ON Enabled
4482
; EBTR1 = OFF Disabled
4484
; Table Read Protection Block 2:
4485
; EBTR2 = ON Enabled
4486
; EBTR2 = OFF Disabled
4488
; Table Read Protection Block 3:
4489
; EBTR3 = ON Enabled
4490
; EBTR3 = OFF Disabled
4492
; Boot Block Table Read Protection:
4493
; EBTRB = ON Enabled
4494
; EBTRB = OFF Disabled
4496
;==========================================================================
4497
;==========================================================================
4333
4499
; Configuration Bits
4433
4599
_XINST_OFF_4L EQU H'BF' ; Disabled
4434
4600
_XINST_ON_4L EQU H'FF' ; Enabled
4436
_BBSIZ_1Kword_4L EQU H'EF' ; 1Kwords (2Kbytes) Boot Block
4437
_BBSIZ_2Kwords_4L EQU H'FF' ; 2Kwords (4Kbytes) Boot Block
4602
_BBSIZ_1024_4L EQU H'EF' ; 1K words (2K bytes) Boot Block
4603
_BBSIZ_2048_4L EQU H'FF' ; 2K words (4K bytes) Boot Block
4439
4605
_LVP_OFF_4L EQU H'FB' ; Disabled
4440
4606
_LVP_ON_4L EQU H'FF' ; Enabled