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/*******************************************************************************
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Intel PRO/1000 Linux driver
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Copyright(c) 1999 - 2008 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Linux NICS <linux.nics@intel.com>
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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FILE_LICENCE ( GPL2_OR_LATER );
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* 82541EI Gigabit Ethernet Controller
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* 82541ER Gigabit Ethernet Controller
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* 82541GI Gigabit Ethernet Controller
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* 82541PI Gigabit Ethernet Controller
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* 82547EI Gigabit Ethernet Controller
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* 82547GI Gigabit Ethernet Controller
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#include "e1000_api.h"
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static s32 e1000_init_phy_params_82541(struct e1000_hw *hw);
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static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw);
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static s32 e1000_init_mac_params_82541(struct e1000_hw *hw);
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static s32 e1000_reset_hw_82541(struct e1000_hw *hw);
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static s32 e1000_init_hw_82541(struct e1000_hw *hw);
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static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
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static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw);
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static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw);
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static s32 e1000_check_for_link_82541(struct e1000_hw *hw);
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static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw);
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static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw,
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static s32 e1000_setup_led_82541(struct e1000_hw *hw);
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static s32 e1000_cleanup_led_82541(struct e1000_hw *hw);
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static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw);
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static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
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static s32 e1000_phy_init_script_82541(struct e1000_hw *hw);
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static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw);
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static const u16 e1000_igp_cable_length_table[] =
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{ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
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25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
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40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
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60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
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90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
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100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
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110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
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#define IGP01E1000_AGC_LENGTH_TABLE_SIZE \
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(sizeof(e1000_igp_cable_length_table) / \
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sizeof(e1000_igp_cable_length_table[0]))
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* e1000_init_phy_params_82541 - Init PHY func ptrs.
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* @hw: pointer to the HW structure
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static s32 e1000_init_phy_params_82541(struct e1000_hw *hw)
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struct e1000_phy_info *phy = &hw->phy;
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s32 ret_val = E1000_SUCCESS;
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DEBUGFUNC("e1000_init_phy_params_82541");
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phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
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phy->reset_delay_us = 10000;
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phy->type = e1000_phy_igp;
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/* Function Pointers */
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phy->ops.check_polarity = e1000_check_polarity_igp;
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phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
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phy->ops.get_cable_length = e1000_get_cable_length_igp_82541;
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phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
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phy->ops.get_info = e1000_get_phy_info_igp;
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phy->ops.read_reg = e1000_read_phy_reg_igp;
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phy->ops.reset = e1000_phy_hw_reset_82541;
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phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541;
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phy->ops.write_reg = e1000_write_phy_reg_igp;
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phy->ops.power_up = e1000_power_up_phy_copper;
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phy->ops.power_down = e1000_power_down_phy_copper_82541;
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ret_val = e1000_get_phy_id(hw);
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if (phy->id != IGP01E1000_I_PHY_ID) {
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ret_val = -E1000_ERR_PHY;
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* e1000_init_nvm_params_82541 - Init NVM func ptrs.
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* @hw: pointer to the HW structure
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static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw)
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struct e1000_nvm_info *nvm = &hw->nvm;
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s32 ret_val = E1000_SUCCESS;
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u32 eecd = E1000_READ_REG(hw, E1000_EECD);
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DEBUGFUNC("e1000_init_nvm_params_82541");
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switch (nvm->override) {
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case e1000_nvm_override_spi_large:
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nvm->type = e1000_nvm_eeprom_spi;
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eecd |= E1000_EECD_ADDR_BITS;
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case e1000_nvm_override_spi_small:
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nvm->type = e1000_nvm_eeprom_spi;
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eecd &= ~E1000_EECD_ADDR_BITS;
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case e1000_nvm_override_microwire_large:
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nvm->type = e1000_nvm_eeprom_microwire;
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eecd |= E1000_EECD_SIZE;
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case e1000_nvm_override_microwire_small:
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nvm->type = e1000_nvm_eeprom_microwire;
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eecd &= ~E1000_EECD_SIZE;
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nvm->type = eecd & E1000_EECD_TYPE
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? e1000_nvm_eeprom_spi
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: e1000_nvm_eeprom_microwire;
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if (nvm->type == e1000_nvm_eeprom_spi) {
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nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS)
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nvm->opcode_bits = 8;
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nvm->page_size = (eecd & E1000_EECD_ADDR_BITS)
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/* Function Pointers */
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nvm->ops.acquire = e1000_acquire_nvm_generic;
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nvm->ops.read = e1000_read_nvm_spi;
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nvm->ops.release = e1000_release_nvm_generic;
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nvm->ops.update = e1000_update_nvm_checksum_generic;
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nvm->ops.valid_led_default = e1000_valid_led_default_generic;
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nvm->ops.validate = e1000_validate_nvm_checksum_generic;
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nvm->ops.write = e1000_write_nvm_spi;
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* nvm->word_size must be discovered after the pointers
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* are set so we can verify the size from the nvm image
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* itself. Temporarily set it to a dummy value so the
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ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size);
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size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT;
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* if size != 0, it can be added to a constant and become
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* the left-shift value to set the word_size. Otherwise,
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* word_size stays at 64.
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size += NVM_WORD_SIZE_BASE_SHIFT_82541;
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nvm->word_size = 1 << size;
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nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS)
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nvm->delay_usec = 50;
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nvm->opcode_bits = 3;
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nvm->word_size = (eecd & E1000_EECD_ADDR_BITS)
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/* Function Pointers */
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nvm->ops.acquire = e1000_acquire_nvm_generic;
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nvm->ops.read = e1000_read_nvm_microwire;
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nvm->ops.release = e1000_release_nvm_generic;
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nvm->ops.update = e1000_update_nvm_checksum_generic;
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nvm->ops.valid_led_default = e1000_valid_led_default_generic;
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nvm->ops.validate = e1000_validate_nvm_checksum_generic;
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nvm->ops.write = e1000_write_nvm_microwire;
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* e1000_init_mac_params_82541 - Init MAC func ptrs.
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* @hw: pointer to the HW structure
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static s32 e1000_init_mac_params_82541(struct e1000_hw *hw)
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struct e1000_mac_info *mac = &hw->mac;
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DEBUGFUNC("e1000_init_mac_params_82541");
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hw->phy.media_type = e1000_media_type_copper;
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/* Set mta register count */
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mac->mta_reg_count = 128;
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/* Set rar entry count */
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mac->rar_entry_count = E1000_RAR_ENTRIES;
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/* Set if part includes ASF firmware */
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mac->asf_firmware_present = true;
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/* Function Pointers */
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/* bus type/speed/width */
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mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
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mac->ops.set_lan_id = e1000_set_lan_id_single_port;
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mac->ops.reset_hw = e1000_reset_hw_82541;
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/* hw initialization */
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mac->ops.init_hw = e1000_init_hw_82541;
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mac->ops.setup_link = e1000_setup_link_generic;
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/* physical interface link setup */
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mac->ops.setup_physical_interface = e1000_setup_copper_link_82541;
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mac->ops.check_for_link = e1000_check_for_link_82541;
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mac->ops.get_link_up_info = e1000_get_link_up_info_82541;
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/* multicast address update */
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mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
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mac->ops.write_vfta = e1000_write_vfta_generic;
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mac->ops.clear_vfta = e1000_clear_vfta_generic;
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mac->ops.mta_set = e1000_mta_set_generic;
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mac->ops.id_led_init = e1000_id_led_init_generic;
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mac->ops.setup_led = e1000_setup_led_82541;
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mac->ops.cleanup_led = e1000_cleanup_led_82541;
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/* turn on/off LED */
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mac->ops.led_on = e1000_led_on_generic;
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mac->ops.led_off = e1000_led_off_generic;
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/* clear hardware counters */
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mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541;
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return E1000_SUCCESS;
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* e1000_init_function_pointers_82541 - Init func ptrs.
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* @hw: pointer to the HW structure
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* Called to initialize all function pointers and parameters.
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void e1000_init_function_pointers_82541(struct e1000_hw *hw)
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DEBUGFUNC("e1000_init_function_pointers_82541");
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hw->mac.ops.init_params = e1000_init_mac_params_82541;
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hw->nvm.ops.init_params = e1000_init_nvm_params_82541;
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hw->phy.ops.init_params = e1000_init_phy_params_82541;
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* e1000_reset_hw_82541 - Reset hardware
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* @hw: pointer to the HW structure
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* This resets the hardware into a known state.
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static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
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u32 ledctl, ctrl, manc;
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DEBUGFUNC("e1000_reset_hw_82541");
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DEBUGOUT("Masking off all interrupts\n");
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E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
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E1000_WRITE_REG(hw, E1000_RCTL, 0);
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E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
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E1000_WRITE_FLUSH(hw);
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* Delay to allow any outstanding PCI transactions to complete
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* before resetting the device.
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ctrl = E1000_READ_REG(hw, E1000_CTRL);
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/* Must reset the Phy before resetting the MAC */
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if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
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E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST));
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DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n");
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switch (hw->mac.type) {
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case e1000_82541_rev_2:
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* These controllers can't ack the 64-bit write when
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* issuing the reset, so we use IO-mapping as a
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* workaround to issue the reset.
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E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
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E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
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/* Wait for NVM reload */
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/* Disable HW ARPs on ASF enabled adapters */
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manc = E1000_READ_REG(hw, E1000_MANC);
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manc &= ~E1000_MANC_ARP_EN;
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E1000_WRITE_REG(hw, E1000_MANC, manc);
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if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
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e1000_phy_init_script_82541(hw);
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/* Configure activity LED after Phy reset */
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ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
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ledctl &= IGP_ACTIVITY_LED_MASK;
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ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
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E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
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/* Once again, mask the interrupts */
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DEBUGOUT("Masking off all interrupts\n");
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E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
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/* Clear any pending interrupt events. */
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E1000_READ_REG(hw, E1000_ICR);
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return E1000_SUCCESS;
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* e1000_init_hw_82541 - Initialize hardware
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* @hw: pointer to the HW structure
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* This inits the hardware readying it for operation.
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static s32 e1000_init_hw_82541(struct e1000_hw *hw)
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struct e1000_mac_info *mac = &hw->mac;
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struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
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DEBUGFUNC("e1000_init_hw_82541");
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/* Initialize identification LED */
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ret_val = mac->ops.id_led_init(hw);
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DEBUGOUT("Error initializing identification LED\n");
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/* This is not fatal and we should not stop init due to this */
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/* Storing the Speed Power Down value for later use */
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ret_val = hw->phy.ops.read_reg(hw,
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IGP01E1000_GMII_FIFO,
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&dev_spec->spd_default);
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/* Disabling VLAN filtering */
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DEBUGOUT("Initializing the IEEE VLAN\n");
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mac->ops.clear_vfta(hw);
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/* Setup the receive address. */
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e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
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/* Zero out the Multicast HASH table */
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DEBUGOUT("Zeroing the MTA\n");
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for (i = 0; i < mac->mta_reg_count; i++) {
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E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
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* Avoid back to back register writes by adding the register
418
* read (flush). This is to protect against some strange
419
* bridge configurations that may issue Memory Write Block
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* (MWB) to our register space.
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E1000_WRITE_FLUSH(hw);
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/* Setup link and flow control */
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ret_val = mac->ops.setup_link(hw);
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txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
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txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
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E1000_TXDCTL_FULL_TX_DESC_WB;
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E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
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* Clear all of the statistics registers (clear on read). It is
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* important that we do this after we have tried to establish link
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* because the symbol error count will increment wildly if there
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e1000_clear_hw_cntrs_82541(hw);
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* e1000_get_link_up_info_82541 - Report speed and duplex
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* @hw: pointer to the HW structure
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* @speed: pointer to speed buffer
449
* @duplex: pointer to duplex buffer
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* Retrieve the current speed and duplex configuration.
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static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
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struct e1000_phy_info *phy = &hw->phy;
460
DEBUGFUNC("e1000_get_link_up_info_82541");
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ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
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if (!phy->speed_downgraded)
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* IGP01 PHY may advertise full duplex operation after speed
471
* downgrade even if it is operating at half duplex.
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* Here we set the duplex settings to match the duplex in the
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* link partner's capabilities.
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ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data);
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if (!(data & NWAY_ER_LP_NWAY_CAPS)) {
480
*duplex = HALF_DUPLEX;
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ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data);
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if (*speed == SPEED_100) {
487
if (!(data & NWAY_LPAR_100TX_FD_CAPS))
488
*duplex = HALF_DUPLEX;
489
} else if (*speed == SPEED_10) {
490
if (!(data & NWAY_LPAR_10T_FD_CAPS))
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*duplex = HALF_DUPLEX;
500
* e1000_phy_hw_reset_82541 - PHY hardware reset
501
* @hw: pointer to the HW structure
503
* Verify the reset block is not blocking us from resetting. Acquire
504
* semaphore (if necessary) and read/set/write the device control reset
505
* bit in the PHY. Wait the appropriate delay time for the device to
506
* reset and release the semaphore (if necessary).
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static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw)
513
DEBUGFUNC("e1000_phy_hw_reset_82541");
515
ret_val = e1000_phy_hw_reset_generic(hw);
519
e1000_phy_init_script_82541(hw);
521
if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
522
/* Configure activity LED after PHY reset */
523
ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
524
ledctl &= IGP_ACTIVITY_LED_MASK;
525
ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
526
E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
534
* e1000_setup_copper_link_82541 - Configure copper link settings
535
* @hw: pointer to the HW structure
537
* Calls the appropriate function to configure the link for auto-neg or forced
538
* speed and duplex. Then we check for link, once link is established calls
539
* to configure collision distance and flow control are called. If link is
540
* not established, we return -E1000_ERR_PHY (-2).
542
static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw)
544
struct e1000_phy_info *phy = &hw->phy;
545
struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
549
DEBUGFUNC("e1000_setup_copper_link_82541");
551
ctrl = E1000_READ_REG(hw, E1000_CTRL);
552
ctrl |= E1000_CTRL_SLU;
553
ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
554
E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
556
hw->phy.reset_disable = false;
558
/* Earlier revs of the IGP phy require us to force MDI. */
559
if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) {
560
dev_spec->dsp_config = e1000_dsp_config_disabled;
563
dev_spec->dsp_config = e1000_dsp_config_enabled;
566
ret_val = e1000_copper_link_setup_igp(hw);
570
if (hw->mac.autoneg) {
571
if (dev_spec->ffe_config == e1000_ffe_config_active)
572
dev_spec->ffe_config = e1000_ffe_config_enabled;
575
/* Configure activity LED after Phy reset */
576
ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
577
ledctl &= IGP_ACTIVITY_LED_MASK;
578
ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
579
E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
581
ret_val = e1000_setup_copper_link_generic(hw);
588
* e1000_check_for_link_82541 - Check/Store link connection
589
* @hw: pointer to the HW structure
591
* This checks the link condition of the adapter and stores the
592
* results in the hw->mac structure.
594
static s32 e1000_check_for_link_82541(struct e1000_hw *hw)
596
struct e1000_mac_info *mac = &hw->mac;
600
DEBUGFUNC("e1000_check_for_link_82541");
603
* We only want to go out to the PHY registers to see if Auto-Neg
604
* has completed and/or if our link status has changed. The
605
* get_link_status flag is set upon receiving a Link Status
606
* Change or Rx Sequence Error interrupt.
608
if (!mac->get_link_status) {
609
ret_val = E1000_SUCCESS;
614
* First we want to see if the MII Status Register reports
615
* link. If so, then we want to get the current speed/duplex
618
ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
623
ret_val = -E1000_ERR_CONFIG;
625
ret_val = e1000_config_dsp_after_link_change_82541(hw, false);
627
goto out; /* No link detected */
630
mac->get_link_status = false;
633
* Check if there was DownShift, must be checked
634
* immediately after link-up
636
e1000_check_downshift_generic(hw);
639
* If we are forcing speed/duplex, then we simply return since
640
* we have already determined whether we have link or not.
643
ret_val = -E1000_ERR_CONFIG;
648
ret_val = e1000_config_dsp_after_link_change_82541(hw, true);
652
* Auto-Neg is enabled. Auto Speed Detection takes care
653
* of MAC speed/duplex configuration. So we only need to
654
* configure Collision Distance in the MAC.
656
e1000_config_collision_dist_generic(hw);
659
* Configure Flow Control now that Auto-Neg has completed.
660
* First, we need to restore the desired flow control
661
* settings because we may have had to re-autoneg with a
662
* different link partner.
664
ret_val = e1000_config_fc_after_link_up_generic(hw);
666
DEBUGOUT("Error configuring flow control\n");
675
* e1000_config_dsp_after_link_change_82541 - Config DSP after link
676
* @hw: pointer to the HW structure
677
* @link_up: boolean flag for link up status
679
* Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS
682
* 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
683
* gigabit link is achieved to improve link quality.
685
static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
688
struct e1000_phy_info *phy = &hw->phy;
689
struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
692
u16 phy_data, phy_saved_data, speed, duplex, i;
693
u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
694
u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
695
{IGP01E1000_PHY_AGC_PARAM_A,
696
IGP01E1000_PHY_AGC_PARAM_B,
697
IGP01E1000_PHY_AGC_PARAM_C,
698
IGP01E1000_PHY_AGC_PARAM_D};
700
DEBUGFUNC("e1000_config_dsp_after_link_change_82541");
703
ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
705
DEBUGOUT("Error getting link speed and duplex\n");
709
if (speed != SPEED_1000) {
710
ret_val = E1000_SUCCESS;
715
ret_val = phy->ops.get_cable_length(hw);
717
ret_val = -E1000_ERR_CONFIG;
721
if ((dev_spec->dsp_config == e1000_dsp_config_enabled) &&
722
phy->min_cable_length >= 50) {
724
for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
725
ret_val = phy->ops.read_reg(hw,
731
phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
733
ret_val = phy->ops.write_reg(hw,
739
dev_spec->dsp_config = e1000_dsp_config_activated;
742
if ((dev_spec->ffe_config != e1000_ffe_config_enabled) ||
743
(phy->min_cable_length >= 50)) {
744
ret_val = E1000_SUCCESS;
748
/* clear previous idle error counts */
749
ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
753
for (i = 0; i < ffe_idle_err_timeout; i++) {
755
ret_val = phy->ops.read_reg(hw,
761
idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
762
if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
763
dev_spec->ffe_config = e1000_ffe_config_active;
765
ret_val = phy->ops.write_reg(hw,
766
IGP01E1000_PHY_DSP_FFE,
767
IGP01E1000_PHY_DSP_FFE_CM_CP);
774
ffe_idle_err_timeout =
775
FFE_IDLE_ERR_COUNT_TIMEOUT_100;
778
if (dev_spec->dsp_config == e1000_dsp_config_activated) {
780
* Save off the current value of register 0x2F5B
781
* to be restored at the end of the routines.
783
ret_val = phy->ops.read_reg(hw,
789
/* Disable the PHY transmitter */
790
ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
796
ret_val = phy->ops.write_reg(hw,
798
IGP01E1000_IEEE_FORCE_GIG);
801
for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
802
ret_val = phy->ops.read_reg(hw,
808
phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
809
phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
811
ret_val = phy->ops.write_reg(hw,
818
ret_val = phy->ops.write_reg(hw,
820
IGP01E1000_IEEE_RESTART_AUTONEG);
826
/* Now enable the transmitter */
827
ret_val = phy->ops.write_reg(hw,
833
dev_spec->dsp_config = e1000_dsp_config_enabled;
836
if (dev_spec->ffe_config != e1000_ffe_config_active) {
837
ret_val = E1000_SUCCESS;
842
* Save off the current value of register 0x2F5B
843
* to be restored at the end of the routines.
845
ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data);
849
/* Disable the PHY transmitter */
850
ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
856
ret_val = phy->ops.write_reg(hw,
858
IGP01E1000_IEEE_FORCE_GIG);
862
ret_val = phy->ops.write_reg(hw,
863
IGP01E1000_PHY_DSP_FFE,
864
IGP01E1000_PHY_DSP_FFE_DEFAULT);
868
ret_val = phy->ops.write_reg(hw,
870
IGP01E1000_IEEE_RESTART_AUTONEG);
876
/* Now enable the transmitter */
877
ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data);
882
dev_spec->ffe_config = e1000_ffe_config_enabled;
892
* e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY
893
* @hw: pointer to the HW structure
895
* The automatic gain control (agc) normalizes the amplitude of the
896
* received signal, adjusting for the attenuation produced by the
897
* cable. By reading the AGC registers, which represent the
898
* combination of coarse and fine gain value, the value can be put
899
* into a lookup table to obtain the approximate cable length
902
static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw)
904
struct e1000_phy_info *phy = &hw->phy;
905
s32 ret_val = E1000_SUCCESS;
907
u16 cur_agc_value, agc_value = 0;
908
u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
909
u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
910
{IGP01E1000_PHY_AGC_A,
911
IGP01E1000_PHY_AGC_B,
912
IGP01E1000_PHY_AGC_C,
913
IGP01E1000_PHY_AGC_D};
915
DEBUGFUNC("e1000_get_cable_length_igp_82541");
917
/* Read the AGC registers for all channels */
918
for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
919
ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data);
923
cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT;
925
/* Bounds checking */
926
if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
927
(cur_agc_value == 0)) {
928
ret_val = -E1000_ERR_PHY;
932
agc_value += cur_agc_value;
934
if (min_agc_value > cur_agc_value)
935
min_agc_value = cur_agc_value;
938
/* Remove the minimal AGC result for length < 50m */
939
if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) {
940
agc_value -= min_agc_value;
941
/* Average the three remaining channels for the length. */
942
agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
944
/* Average the channels for the length. */
945
agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
948
phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] >
949
IGP01E1000_AGC_RANGE)
950
? (e1000_igp_cable_length_table[agc_value] -
951
IGP01E1000_AGC_RANGE)
953
phy->max_cable_length = e1000_igp_cable_length_table[agc_value] +
954
IGP01E1000_AGC_RANGE;
956
phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
964
* e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3
965
* @hw: pointer to the HW structure
966
* @active: boolean used to enable/disable lplu
968
* Success returns 0, Failure returns 1
970
* The low power link up (lplu) state is set to the power management level D3
971
* and SmartSpeed is disabled when active is true, else clear lplu for D3
972
* and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
973
* is used during Dx states where the power conservation is most important.
974
* During driver activity, SmartSpeed should be enabled so performance is
977
static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active)
979
struct e1000_phy_info *phy = &hw->phy;
983
DEBUGFUNC("e1000_set_d3_lplu_state_82541");
985
switch (hw->mac.type) {
986
case e1000_82541_rev_2:
987
case e1000_82547_rev_2:
990
ret_val = e1000_set_d3_lplu_state_generic(hw, active);
995
ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data);
1000
data &= ~IGP01E1000_GMII_FLEX_SPD;
1001
ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
1006
* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1007
* during Dx states where the power conservation is most
1008
* important. During driver activity we should enable
1009
* SmartSpeed, so performance is maintained.
1011
if (phy->smart_speed == e1000_smart_speed_on) {
1012
ret_val = phy->ops.read_reg(hw,
1013
IGP01E1000_PHY_PORT_CONFIG,
1018
data |= IGP01E1000_PSCFR_SMART_SPEED;
1019
ret_val = phy->ops.write_reg(hw,
1020
IGP01E1000_PHY_PORT_CONFIG,
1024
} else if (phy->smart_speed == e1000_smart_speed_off) {
1025
ret_val = phy->ops.read_reg(hw,
1026
IGP01E1000_PHY_PORT_CONFIG,
1031
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1032
ret_val = phy->ops.write_reg(hw,
1033
IGP01E1000_PHY_PORT_CONFIG,
1038
} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1039
(phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1040
(phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1041
data |= IGP01E1000_GMII_FLEX_SPD;
1042
ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
1046
/* When LPLU is enabled, we should disable SmartSpeed */
1047
ret_val = phy->ops.read_reg(hw,
1048
IGP01E1000_PHY_PORT_CONFIG,
1053
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1054
ret_val = phy->ops.write_reg(hw,
1055
IGP01E1000_PHY_PORT_CONFIG,
1064
* e1000_setup_led_82541 - Configures SW controllable LED
1065
* @hw: pointer to the HW structure
1067
* This prepares the SW controllable LED for use and saves the current state
1068
* of the LED so it can be later restored.
1070
static s32 e1000_setup_led_82541(struct e1000_hw *hw __unused)
1073
struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1076
DEBUGFUNC("e1000_setup_led_82541");
1078
ret_val = hw->phy.ops.read_reg(hw,
1079
IGP01E1000_GMII_FIFO,
1080
&dev_spec->spd_default);
1084
ret_val = hw->phy.ops.write_reg(hw,
1085
IGP01E1000_GMII_FIFO,
1086
(u16)(dev_spec->spd_default &
1087
~IGP01E1000_GMII_SPD));
1091
E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1100
* e1000_cleanup_led_82541 - Set LED config to default operation
1101
* @hw: pointer to the HW structure
1103
* Remove the current LED configuration and set the LED configuration
1104
* to the default value, saved from the EEPROM.
1106
static s32 e1000_cleanup_led_82541(struct e1000_hw *hw __unused)
1109
struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1112
DEBUGFUNC("e1000_cleanup_led_82541");
1114
ret_val = hw->phy.ops.write_reg(hw,
1115
IGP01E1000_GMII_FIFO,
1116
dev_spec->spd_default);
1120
E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1129
* e1000_phy_init_script_82541 - Initialize GbE PHY
1130
* @hw: pointer to the HW structure
1132
* Initializes the IGP PHY.
1134
static s32 e1000_phy_init_script_82541(struct e1000_hw *hw)
1136
struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1140
DEBUGFUNC("e1000_phy_init_script_82541");
1142
if (!dev_spec->phy_init_script) {
1143
ret_val = E1000_SUCCESS;
1147
/* Delay after phy reset to enable NVM configuration to load */
1151
* Save off the current value of register 0x2F5B to be restored at
1152
* the end of this routine.
1154
ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data);
1156
/* Disabled the PHY transmitter */
1157
hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003);
1161
hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
1165
switch (hw->mac.type) {
1168
hw->phy.ops.write_reg(hw, 0x1F95, 0x0001);
1170
hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21);
1172
hw->phy.ops.write_reg(hw, 0x1F79, 0x0018);
1174
hw->phy.ops.write_reg(hw, 0x1F30, 0x1600);
1176
hw->phy.ops.write_reg(hw, 0x1F31, 0x0014);
1178
hw->phy.ops.write_reg(hw, 0x1F32, 0x161C);
1180
hw->phy.ops.write_reg(hw, 0x1F94, 0x0003);
1182
hw->phy.ops.write_reg(hw, 0x1F96, 0x003F);
1184
hw->phy.ops.write_reg(hw, 0x2010, 0x0008);
1186
case e1000_82541_rev_2:
1187
case e1000_82547_rev_2:
1188
hw->phy.ops.write_reg(hw, 0x1F73, 0x0099);
1194
hw->phy.ops.write_reg(hw, 0x0000, 0x3300);
1198
/* Now enable the transmitter */
1199
hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data);
1201
if (hw->mac.type == e1000_82547) {
1202
u16 fused, fine, coarse;
1204
/* Move to analog registers page */
1205
hw->phy.ops.read_reg(hw,
1206
IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
1209
if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
1210
hw->phy.ops.read_reg(hw,
1211
IGP01E1000_ANALOG_FUSE_STATUS,
1214
fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
1215
coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
1217
if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
1218
coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
1219
fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
1220
} else if (coarse ==
1221
IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
1222
fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
1224
fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
1225
(fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
1226
(coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
1228
hw->phy.ops.write_reg(hw,
1229
IGP01E1000_ANALOG_FUSE_CONTROL,
1231
hw->phy.ops.write_reg(hw,
1232
IGP01E1000_ANALOG_FUSE_BYPASS,
1233
IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
1242
* e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down
1243
* @hw: pointer to the HW structure
1245
* In the case of a PHY power down to save power, or to turn off link during a
1246
* driver unload, or wake on lan is not enabled, remove the link.
1248
static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw)
1250
/* If the management interface is not enabled, then power down */
1251
if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
1252
e1000_power_down_phy_copper(hw);
1258
* e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters
1259
* @hw: pointer to the HW structure
1261
* Clears the hardware counters by reading the counter registers.
1263
static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw)
1265
DEBUGFUNC("e1000_clear_hw_cntrs_82541");
1267
e1000_clear_hw_cntrs_base_generic(hw);
1270
E1000_READ_REG(hw, E1000_PRC64);
1271
E1000_READ_REG(hw, E1000_PRC127);
1272
E1000_READ_REG(hw, E1000_PRC255);
1273
E1000_READ_REG(hw, E1000_PRC511);
1274
E1000_READ_REG(hw, E1000_PRC1023);
1275
E1000_READ_REG(hw, E1000_PRC1522);
1276
E1000_READ_REG(hw, E1000_PTC64);
1277
E1000_READ_REG(hw, E1000_PTC127);
1278
E1000_READ_REG(hw, E1000_PTC255);
1279
E1000_READ_REG(hw, E1000_PTC511);
1280
E1000_READ_REG(hw, E1000_PTC1023);
1281
E1000_READ_REG(hw, E1000_PTC1522);
1283
E1000_READ_REG(hw, E1000_ALGNERRC);
1284
E1000_READ_REG(hw, E1000_RXERRC);
1285
E1000_READ_REG(hw, E1000_TNCRS);
1286
E1000_READ_REG(hw, E1000_CEXTERR);
1287
E1000_READ_REG(hw, E1000_TSCTC);
1288
E1000_READ_REG(hw, E1000_TSCTFC);
1290
E1000_READ_REG(hw, E1000_MGTPRC);
1291
E1000_READ_REG(hw, E1000_MGTPDC);
1292
E1000_READ_REG(hw, E1000_MGTPTC);
1296
static struct pci_device_id e1000_82541_nics[] = {
1297
PCI_ROM(0x8086, 0x1013, "E1000_DEV_ID_82541EI", "E1000_DEV_ID_82541EI", e1000_82541),
1298
PCI_ROM(0x8086, 0x1014, "E1000_DEV_ID_82541ER_LOM", "E1000_DEV_ID_82541ER_LOM", e1000_82541),
1299
PCI_ROM(0x8086, 0x1018, "E1000_DEV_ID_82541EI_MOBILE", "E1000_DEV_ID_82541EI_MOBILE", e1000_82541),
1300
PCI_ROM(0x8086, 0x1019, "E1000_DEV_ID_82547EI", "E1000_DEV_ID_82547EI", e1000_82547),
1301
PCI_ROM(0x8086, 0x101A, "E1000_DEV_ID_82547EI_MOBILE", "E1000_DEV_ID_82547EI_MOBILE", e1000_82547),
1302
PCI_ROM(0x8086, 0x1075, "E1000_DEV_ID_82547GI", "E1000_DEV_ID_82547GI", e1000_82547_rev_2),
1303
PCI_ROM(0x8086, 0x1076, "E1000_DEV_ID_82541GI", "E1000_DEV_ID_82541GI", e1000_82541_rev_2),
1304
PCI_ROM(0x8086, 0x1077, "E1000_DEV_ID_82541GI_MOBILE", "E1000_DEV_ID_82541GI_MOBILE", e1000_82541_rev_2),
1305
PCI_ROM(0x8086, 0x1078, "E1000_DEV_ID_82541ER", "E1000_DEV_ID_82541ER", e1000_82541_rev_2),
1306
PCI_ROM(0x8086, 0x107C, "E1000_DEV_ID_82541GI_LF", "E1000_DEV_ID_82541GI_LF", e1000_82541_rev_2),
1309
struct pci_driver e1000_82541_driver __pci_driver = {
1310
.ids = e1000_82541_nics,
1311
.id_count = (sizeof (e1000_82541_nics) / sizeof (e1000_82541_nics[0])),
1312
.probe = e1000_probe,
1313
.remove = e1000_remove,
added
removed
src/drivers/net/e1000/e1000_82541.c
