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/*******************************************************************************
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Intel(R) Gigabit Ethernet Linux driver
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Copyright(c) 2007-2009 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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FILE_LICENCE ( GPL2_ONLY );
32
static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
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/* Cable length tables */
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static const u16 e1000_m88_cable_length_table[] =
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{ 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
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#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
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(sizeof(e1000_m88_cable_length_table) / \
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sizeof(e1000_m88_cable_length_table[0]))
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static const u16 e1000_igp_2_cable_length_table[] =
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{ 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
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0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
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6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
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21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
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40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
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60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
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83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
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104, 109, 114, 118, 121, 124};
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#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
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(sizeof(e1000_igp_2_cable_length_table) / \
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sizeof(e1000_igp_2_cable_length_table[0]))
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* igb_check_reset_block_generic - Check if PHY reset is blocked
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* @hw: pointer to the HW structure
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* Read the PHY management control register and check whether a PHY reset
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* is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
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* return E1000_BLK_PHY_RESET (12).
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s32 igb_check_reset_block_generic(struct e1000_hw *hw)
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DEBUGFUNC("igb_check_reset_block");
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manc = E1000_READ_REG(hw, E1000_MANC);
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return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
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E1000_BLK_PHY_RESET : E1000_SUCCESS;
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* igb_get_phy_id - Retrieve the PHY ID and revision
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* @hw: pointer to the HW structure
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* Reads the PHY registers and stores the PHY ID and possibly the PHY
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* revision in the hardware structure.
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s32 igb_get_phy_id(struct e1000_hw *hw)
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struct e1000_phy_info *phy = &hw->phy;
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s32 ret_val = E1000_SUCCESS;
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DEBUGFUNC("igb_get_phy_id");
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if (!(phy->ops.read_reg))
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ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
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phy->id = (u32)(phy_id << 16);
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ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
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phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
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phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
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* igb_phy_reset_dsp_generic - Reset PHY DSP
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* @hw: pointer to the HW structure
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* Reset the digital signal processor.
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s32 igb_phy_reset_dsp_generic(struct e1000_hw *hw)
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s32 ret_val = E1000_SUCCESS;
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DEBUGFUNC("igb_phy_reset_dsp_generic");
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if (!(hw->phy.ops.write_reg))
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ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
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ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
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* igb_read_phy_reg_mdic - Read MDI control register
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* @hw: pointer to the HW structure
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* @offset: register offset to be read
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* @data: pointer to the read data
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* Reads the MDI control register in the PHY at offset and stores the
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* information read to data.
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s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
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struct e1000_phy_info *phy = &hw->phy;
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s32 ret_val = E1000_SUCCESS;
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DEBUGFUNC("igb_read_phy_reg_mdic");
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* Set up Op-code, Phy Address, and register offset in the MDI
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* Control register. The MAC will take care of interfacing with the
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* PHY to retrieve the desired data.
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mdic = ((offset << E1000_MDIC_REG_SHIFT) |
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(phy->addr << E1000_MDIC_PHY_SHIFT) |
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(E1000_MDIC_OP_READ));
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E1000_WRITE_REG(hw, E1000_MDIC, mdic);
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* Poll the ready bit to see if the MDI read completed
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* Increasing the time out as testing showed failures with
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for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
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mdic = E1000_READ_REG(hw, E1000_MDIC);
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if (mdic & E1000_MDIC_READY)
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if (!(mdic & E1000_MDIC_READY)) {
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DEBUGOUT("MDI Read did not complete\n");
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ret_val = -E1000_ERR_PHY;
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if (mdic & E1000_MDIC_ERROR) {
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DEBUGOUT("MDI Error\n");
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ret_val = -E1000_ERR_PHY;
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* igb_write_phy_reg_mdic - Write MDI control register
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* @hw: pointer to the HW structure
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* @offset: register offset to write to
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* @data: data to write to register at offset
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* Writes data to MDI control register in the PHY at offset.
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s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
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struct e1000_phy_info *phy = &hw->phy;
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s32 ret_val = E1000_SUCCESS;
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DEBUGFUNC("igb_write_phy_reg_mdic");
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* Set up Op-code, Phy Address, and register offset in the MDI
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* Control register. The MAC will take care of interfacing with the
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* PHY to retrieve the desired data.
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mdic = (((u32)data) |
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(offset << E1000_MDIC_REG_SHIFT) |
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(phy->addr << E1000_MDIC_PHY_SHIFT) |
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(E1000_MDIC_OP_WRITE));
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E1000_WRITE_REG(hw, E1000_MDIC, mdic);
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* Poll the ready bit to see if the MDI read completed
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* Increasing the time out as testing showed failures with
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for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
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mdic = E1000_READ_REG(hw, E1000_MDIC);
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if (mdic & E1000_MDIC_READY)
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if (!(mdic & E1000_MDIC_READY)) {
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DEBUGOUT("MDI Write did not complete\n");
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ret_val = -E1000_ERR_PHY;
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if (mdic & E1000_MDIC_ERROR) {
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DEBUGOUT("MDI Error\n");
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ret_val = -E1000_ERR_PHY;
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* igb_read_phy_reg_i2c - Read PHY register using i2c
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* @hw: pointer to the HW structure
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* @offset: register offset to be read
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* @data: pointer to the read data
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* Reads the PHY register at offset using the i2c interface and stores the
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* retrieved information in data.
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s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
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struct e1000_phy_info *phy = &hw->phy;
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DEBUGFUNC("igb_read_phy_reg_i2c");
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* Set up Op-code, Phy Address, and register address in the I2CCMD
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* register. The MAC will take care of interfacing with the
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* PHY to retrieve the desired data.
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i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
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(phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
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(E1000_I2CCMD_OPCODE_READ));
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E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
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/* Poll the ready bit to see if the I2C read completed */
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for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
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i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
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if (i2ccmd & E1000_I2CCMD_READY)
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if (!(i2ccmd & E1000_I2CCMD_READY)) {
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DEBUGOUT("I2CCMD Read did not complete\n");
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return -E1000_ERR_PHY;
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if (i2ccmd & E1000_I2CCMD_ERROR) {
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DEBUGOUT("I2CCMD Error bit set\n");
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return -E1000_ERR_PHY;
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/* Need to byte-swap the 16-bit value. */
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*data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
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return E1000_SUCCESS;
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* igb_write_phy_reg_i2c - Write PHY register using i2c
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* @hw: pointer to the HW structure
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* @offset: register offset to write to
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* @data: data to write at register offset
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* Writes the data to PHY register at the offset using the i2c interface.
302
s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
304
struct e1000_phy_info *phy = &hw->phy;
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u16 phy_data_swapped;
308
DEBUGFUNC("igb_write_phy_reg_i2c");
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/* Swap the data bytes for the I2C interface */
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phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
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* Set up Op-code, Phy Address, and register address in the I2CCMD
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* register. The MAC will take care of interfacing with the
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* PHY to retrieve the desired data.
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i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
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(phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
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E1000_I2CCMD_OPCODE_WRITE |
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E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
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/* Poll the ready bit to see if the I2C read completed */
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for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
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i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
329
if (i2ccmd & E1000_I2CCMD_READY)
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if (!(i2ccmd & E1000_I2CCMD_READY)) {
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DEBUGOUT("I2CCMD Write did not complete\n");
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return -E1000_ERR_PHY;
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if (i2ccmd & E1000_I2CCMD_ERROR) {
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DEBUGOUT("I2CCMD Error bit set\n");
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return -E1000_ERR_PHY;
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return E1000_SUCCESS;
345
* igb_read_phy_reg_m88 - Read m88 PHY register
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* @hw: pointer to the HW structure
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* @offset: register offset to be read
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* @data: pointer to the read data
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* Acquires semaphore, if necessary, then reads the PHY register at offset
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* and storing the retrieved information in data. Release any acquired
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* semaphores before exiting.
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s32 igb_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
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s32 ret_val = E1000_SUCCESS;
358
DEBUGFUNC("igb_read_phy_reg_m88");
360
if (!(hw->phy.ops.acquire))
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ret_val = hw->phy.ops.acquire(hw);
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ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
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hw->phy.ops.release(hw);
377
* igb_write_phy_reg_m88 - Write m88 PHY register
378
* @hw: pointer to the HW structure
379
* @offset: register offset to write to
380
* @data: data to write at register offset
382
* Acquires semaphore, if necessary, then writes the data to PHY register
383
* at the offset. Release any acquired semaphores before exiting.
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s32 igb_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
387
s32 ret_val = E1000_SUCCESS;
389
DEBUGFUNC("igb_write_phy_reg_m88");
391
if (!(hw->phy.ops.acquire))
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ret_val = hw->phy.ops.acquire(hw);
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ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
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hw->phy.ops.release(hw);
408
* __igb_read_phy_reg_igp - Read igp PHY register
409
* @hw: pointer to the HW structure
410
* @offset: register offset to be read
411
* @data: pointer to the read data
412
* @locked: semaphore has already been acquired or not
414
* Acquires semaphore, if necessary, then reads the PHY register at offset
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* and stores the retrieved information in data. Release any acquired
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* semaphores before exiting.
418
static s32 __igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
421
s32 ret_val = E1000_SUCCESS;
423
DEBUGFUNC("__igb_read_phy_reg_igp");
426
if (!(hw->phy.ops.acquire))
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ret_val = hw->phy.ops.acquire(hw);
434
if (offset > MAX_PHY_MULTI_PAGE_REG) {
435
ret_val = igb_write_phy_reg_mdic(hw,
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IGP01E1000_PHY_PAGE_SELECT,
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ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
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hw->phy.ops.release(hw);
452
* igb_read_phy_reg_igp - Read igp PHY register
453
* @hw: pointer to the HW structure
454
* @offset: register offset to be read
455
* @data: pointer to the read data
457
* Acquires semaphore then reads the PHY register at offset and stores the
458
* retrieved information in data.
459
* Release the acquired semaphore before exiting.
461
s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
463
return __igb_read_phy_reg_igp(hw, offset, data, false);
467
* igb_read_phy_reg_igp_locked - Read igp PHY register
468
* @hw: pointer to the HW structure
469
* @offset: register offset to be read
470
* @data: pointer to the read data
472
* Reads the PHY register at offset and stores the retrieved information
473
* in data. Assumes semaphore already acquired.
475
s32 igb_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
477
return __igb_read_phy_reg_igp(hw, offset, data, true);
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* igb_write_phy_reg_igp - Write igp PHY register
482
* @hw: pointer to the HW structure
483
* @offset: register offset to write to
484
* @data: data to write at register offset
485
* @locked: semaphore has already been acquired or not
487
* Acquires semaphore, if necessary, then writes the data to PHY register
488
* at the offset. Release any acquired semaphores before exiting.
490
static s32 __igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
493
s32 ret_val = E1000_SUCCESS;
495
DEBUGFUNC("igb_write_phy_reg_igp");
498
if (!(hw->phy.ops.acquire))
501
ret_val = hw->phy.ops.acquire(hw);
506
if (offset > MAX_PHY_MULTI_PAGE_REG) {
507
ret_val = igb_write_phy_reg_mdic(hw,
508
IGP01E1000_PHY_PAGE_SELECT,
514
ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
519
hw->phy.ops.release(hw);
526
* igb_write_phy_reg_igp - Write igp PHY register
527
* @hw: pointer to the HW structure
528
* @offset: register offset to write to
529
* @data: data to write at register offset
531
* Acquires semaphore then writes the data to PHY register
532
* at the offset. Release any acquired semaphores before exiting.
534
s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
536
return __igb_write_phy_reg_igp(hw, offset, data, false);
540
* igb_write_phy_reg_igp_locked - Write igp PHY register
541
* @hw: pointer to the HW structure
542
* @offset: register offset to write to
543
* @data: data to write at register offset
545
* Writes the data to PHY register at the offset.
546
* Assumes semaphore already acquired.
548
s32 igb_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
550
return __igb_write_phy_reg_igp(hw, offset, data, true);
554
* __igb_read_kmrn_reg - Read kumeran register
555
* @hw: pointer to the HW structure
556
* @offset: register offset to be read
557
* @data: pointer to the read data
558
* @locked: semaphore has already been acquired or not
560
* Acquires semaphore, if necessary. Then reads the PHY register at offset
561
* using the kumeran interface. The information retrieved is stored in data.
562
* Release any acquired semaphores before exiting.
564
static s32 __igb_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
568
s32 ret_val = E1000_SUCCESS;
570
DEBUGFUNC("__igb_read_kmrn_reg");
573
if (!(hw->phy.ops.acquire))
576
ret_val = hw->phy.ops.acquire(hw);
581
kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
582
E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
583
E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
587
kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
588
*data = (u16)kmrnctrlsta;
591
hw->phy.ops.release(hw);
598
* igb_read_kmrn_reg_generic - Read kumeran register
599
* @hw: pointer to the HW structure
600
* @offset: register offset to be read
601
* @data: pointer to the read data
603
* Acquires semaphore then reads the PHY register at offset using the
604
* kumeran interface. The information retrieved is stored in data.
605
* Release the acquired semaphore before exiting.
607
s32 igb_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
609
return __igb_read_kmrn_reg(hw, offset, data, false);
613
* igb_read_kmrn_reg_locked - Read kumeran register
614
* @hw: pointer to the HW structure
615
* @offset: register offset to be read
616
* @data: pointer to the read data
618
* Reads the PHY register at offset using the kumeran interface. The
619
* information retrieved is stored in data.
620
* Assumes semaphore already acquired.
622
s32 igb_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
624
return __igb_read_kmrn_reg(hw, offset, data, true);
628
* __igb_write_kmrn_reg - Write kumeran register
629
* @hw: pointer to the HW structure
630
* @offset: register offset to write to
631
* @data: data to write at register offset
632
* @locked: semaphore has already been acquired or not
634
* Acquires semaphore, if necessary. Then write the data to PHY register
635
* at the offset using the kumeran interface. Release any acquired semaphores
638
static s32 __igb_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
642
s32 ret_val = E1000_SUCCESS;
644
DEBUGFUNC("igb_write_kmrn_reg_generic");
647
if (!(hw->phy.ops.acquire))
650
ret_val = hw->phy.ops.acquire(hw);
655
kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
656
E1000_KMRNCTRLSTA_OFFSET) | data;
657
E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
662
hw->phy.ops.release(hw);
669
* igb_write_kmrn_reg_generic - Write kumeran register
670
* @hw: pointer to the HW structure
671
* @offset: register offset to write to
672
* @data: data to write at register offset
674
* Acquires semaphore then writes the data to the PHY register at the offset
675
* using the kumeran interface. Release the acquired semaphore before exiting.
677
s32 igb_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
679
return __igb_write_kmrn_reg(hw, offset, data, false);
683
* igb_write_kmrn_reg_locked - Write kumeran register
684
* @hw: pointer to the HW structure
685
* @offset: register offset to write to
686
* @data: data to write at register offset
688
* Write the data to PHY register at the offset using the kumeran interface.
689
* Assumes semaphore already acquired.
691
s32 igb_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
693
return __igb_write_kmrn_reg(hw, offset, data, true);
697
* igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
698
* @hw: pointer to the HW structure
700
* Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
701
* and downshift values are set also.
703
s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
705
struct e1000_phy_info *phy = &hw->phy;
709
DEBUGFUNC("igb_copper_link_setup_m88");
711
if (phy->reset_disable) {
712
ret_val = E1000_SUCCESS;
716
/* Enable CRS on TX. This must be set for half-duplex operation. */
717
ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
721
phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
725
* MDI/MDI-X = 0 (default)
726
* 0 - Auto for all speeds
729
* 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
731
phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
735
phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
738
phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
741
phy_data |= M88E1000_PSCR_AUTO_X_1000T;
745
phy_data |= M88E1000_PSCR_AUTO_X_MODE;
751
* disable_polarity_correction = 0 (default)
752
* Automatic Correction for Reversed Cable Polarity
756
phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
757
if (phy->disable_polarity_correction == 1)
758
phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
760
ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
764
if (phy->revision < E1000_REVISION_4) {
766
* Force TX_CLK in the Extended PHY Specific Control Register
769
ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
774
phy_data |= M88E1000_EPSCR_TX_CLK_25;
776
if ((phy->revision == E1000_REVISION_2) &&
777
(phy->id == M88E1111_I_PHY_ID)) {
778
/* 82573L PHY - set the downshift counter to 5x. */
779
phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
780
phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
782
/* Configure Master and Slave downshift values */
783
phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
784
M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
785
phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
786
M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
788
ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
794
/* Commit the changes. */
795
ret_val = phy->ops.commit(hw);
797
DEBUGOUT("Error committing the PHY changes\n");
806
* igb_copper_link_setup_igp - Setup igp PHY's for copper link
807
* @hw: pointer to the HW structure
809
* Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
812
s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
814
struct e1000_phy_info *phy = &hw->phy;
818
DEBUGFUNC("igb_copper_link_setup_igp");
820
if (phy->reset_disable) {
821
ret_val = E1000_SUCCESS;
825
ret_val = hw->phy.ops.reset(hw);
827
DEBUGOUT("Error resetting the PHY.\n");
832
* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
833
* timeout issues when LFS is enabled.
838
* The NVM settings will configure LPLU in D3 for
841
if (phy->type == e1000_phy_igp) {
842
/* disable lplu d3 during driver init */
843
ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
845
DEBUGOUT("Error Disabling LPLU D3\n");
850
/* disable lplu d0 during driver init */
851
if (hw->phy.ops.set_d0_lplu_state) {
852
ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
854
DEBUGOUT("Error Disabling LPLU D0\n");
858
/* Configure mdi-mdix settings */
859
ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
863
data &= ~IGP01E1000_PSCR_AUTO_MDIX;
867
data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
870
data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
874
data |= IGP01E1000_PSCR_AUTO_MDIX;
877
ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
881
/* set auto-master slave resolution settings */
882
if (hw->mac.autoneg) {
884
* when autonegotiation advertisement is only 1000Mbps then we
885
* should disable SmartSpeed and enable Auto MasterSlave
886
* resolution as hardware default.
888
if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
889
/* Disable SmartSpeed */
890
ret_val = phy->ops.read_reg(hw,
891
IGP01E1000_PHY_PORT_CONFIG,
896
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
897
ret_val = phy->ops.write_reg(hw,
898
IGP01E1000_PHY_PORT_CONFIG,
903
/* Set auto Master/Slave resolution process */
904
ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
908
data &= ~CR_1000T_MS_ENABLE;
909
ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
914
ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
918
/* load defaults for future use */
919
phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
920
((data & CR_1000T_MS_VALUE) ?
921
e1000_ms_force_master :
922
e1000_ms_force_slave) :
925
switch (phy->ms_type) {
926
case e1000_ms_force_master:
927
data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
929
case e1000_ms_force_slave:
930
data |= CR_1000T_MS_ENABLE;
931
data &= ~(CR_1000T_MS_VALUE);
934
data &= ~CR_1000T_MS_ENABLE;
938
ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
948
* igb_copper_link_autoneg - Setup/Enable autoneg for copper link
949
* @hw: pointer to the HW structure
951
* Performs initial bounds checking on autoneg advertisement parameter, then
952
* configure to advertise the full capability. Setup the PHY to autoneg
953
* and restart the negotiation process between the link partner. If
954
* autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
956
s32 igb_copper_link_autoneg(struct e1000_hw *hw)
958
struct e1000_phy_info *phy = &hw->phy;
962
DEBUGFUNC("igb_copper_link_autoneg");
965
* Perform some bounds checking on the autoneg advertisement
968
phy->autoneg_advertised &= phy->autoneg_mask;
971
* If autoneg_advertised is zero, we assume it was not defaulted
972
* by the calling code so we set to advertise full capability.
974
if (phy->autoneg_advertised == 0)
975
phy->autoneg_advertised = phy->autoneg_mask;
977
DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
978
ret_val = igb_phy_setup_autoneg(hw);
980
DEBUGOUT("Error Setting up Auto-Negotiation\n");
983
DEBUGOUT("Restarting Auto-Neg\n");
986
* Restart auto-negotiation by setting the Auto Neg Enable bit and
987
* the Auto Neg Restart bit in the PHY control register.
989
ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
993
phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
994
ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
999
* Does the user want to wait for Auto-Neg to complete here, or
1000
* check at a later time (for example, callback routine).
1002
if (phy->autoneg_wait_to_complete) {
1003
ret_val = hw->mac.ops.wait_autoneg(hw);
1005
DEBUGOUT("Error while waiting for "
1006
"autoneg to complete\n");
1011
hw->mac.get_link_status = true;
1018
* igb_phy_setup_autoneg - Configure PHY for auto-negotiation
1019
* @hw: pointer to the HW structure
1021
* Reads the MII auto-neg advertisement register and/or the 1000T control
1022
* register and if the PHY is already setup for auto-negotiation, then
1023
* return successful. Otherwise, setup advertisement and flow control to
1024
* the appropriate values for the wanted auto-negotiation.
1026
static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
1028
struct e1000_phy_info *phy = &hw->phy;
1030
u16 mii_autoneg_adv_reg;
1031
u16 mii_1000t_ctrl_reg = 0;
1033
DEBUGFUNC("igb_phy_setup_autoneg");
1035
phy->autoneg_advertised &= phy->autoneg_mask;
1037
/* Read the MII Auto-Neg Advertisement Register (Address 4). */
1038
ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1042
if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1043
/* Read the MII 1000Base-T Control Register (Address 9). */
1044
ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1045
&mii_1000t_ctrl_reg);
1051
* Need to parse both autoneg_advertised and fc and set up
1052
* the appropriate PHY registers. First we will parse for
1053
* autoneg_advertised software override. Since we can advertise
1054
* a plethora of combinations, we need to check each bit
1059
* First we clear all the 10/100 mb speed bits in the Auto-Neg
1060
* Advertisement Register (Address 4) and the 1000 mb speed bits in
1061
* the 1000Base-T Control Register (Address 9).
1063
mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1064
NWAY_AR_100TX_HD_CAPS |
1065
NWAY_AR_10T_FD_CAPS |
1066
NWAY_AR_10T_HD_CAPS);
1067
mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1069
DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1071
/* Do we want to advertise 10 Mb Half Duplex? */
1072
if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1073
DEBUGOUT("Advertise 10mb Half duplex\n");
1074
mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1077
/* Do we want to advertise 10 Mb Full Duplex? */
1078
if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1079
DEBUGOUT("Advertise 10mb Full duplex\n");
1080
mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1083
/* Do we want to advertise 100 Mb Half Duplex? */
1084
if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1085
DEBUGOUT("Advertise 100mb Half duplex\n");
1086
mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1089
/* Do we want to advertise 100 Mb Full Duplex? */
1090
if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1091
DEBUGOUT("Advertise 100mb Full duplex\n");
1092
mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1095
/* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1096
if (phy->autoneg_advertised & ADVERTISE_1000_HALF) {
1097
DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1099
/* Do we want to advertise 1000 Mb Full Duplex? */
1100
if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1101
DEBUGOUT("Advertise 1000mb Full duplex\n");
1102
mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1106
* Check for a software override of the flow control settings, and
1107
* setup the PHY advertisement registers accordingly. If
1108
* auto-negotiation is enabled, then software will have to set the
1109
* "PAUSE" bits to the correct value in the Auto-Negotiation
1110
* Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1113
* The possible values of the "fc" parameter are:
1114
* 0: Flow control is completely disabled
1115
* 1: Rx flow control is enabled (we can receive pause frames
1116
* but not send pause frames).
1117
* 2: Tx flow control is enabled (we can send pause frames
1118
* but we do not support receiving pause frames).
1119
* 3: Both Rx and Tx flow control (symmetric) are enabled.
1120
* other: No software override. The flow control configuration
1121
* in the EEPROM is used.
1123
switch (hw->fc.current_mode) {
1126
* Flow control (Rx & Tx) is completely disabled by a
1127
* software over-ride.
1129
mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1131
case e1000_fc_rx_pause:
1133
* Rx Flow control is enabled, and Tx Flow control is
1134
* disabled, by a software over-ride.
1136
* Since there really isn't a way to advertise that we are
1137
* capable of Rx Pause ONLY, we will advertise that we
1138
* support both symmetric and asymmetric Rx PAUSE. Later
1139
* (in e1000_config_fc_after_link_up) we will disable the
1140
* hw's ability to send PAUSE frames.
1142
mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1144
case e1000_fc_tx_pause:
1146
* Tx Flow control is enabled, and Rx Flow control is
1147
* disabled, by a software over-ride.
1149
mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1150
mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1154
* Flow control (both Rx and Tx) is enabled by a software
1157
mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1160
DEBUGOUT("Flow control param set incorrectly\n");
1161
ret_val = -E1000_ERR_CONFIG;
1165
ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1169
DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1171
if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1172
ret_val = phy->ops.write_reg(hw,
1174
mii_1000t_ctrl_reg);
1184
* igb_setup_copper_link_generic - Configure copper link settings
1185
* @hw: pointer to the HW structure
1187
* Calls the appropriate function to configure the link for auto-neg or forced
1188
* speed and duplex. Then we check for link, once link is established calls
1189
* to configure collision distance and flow control are called. If link is
1190
* not established, we return -E1000_ERR_PHY (-2).
1192
s32 igb_setup_copper_link_generic(struct e1000_hw *hw)
1197
DEBUGFUNC("igb_setup_copper_link_generic");
1199
if (hw->mac.autoneg) {
1201
* Setup autoneg and flow control advertisement and perform
1204
ret_val = igb_copper_link_autoneg(hw);
1210
* PHY will be set to 10H, 10F, 100H or 100F
1211
* depending on user settings.
1213
DEBUGOUT("Forcing Speed and Duplex\n");
1214
ret_val = hw->phy.ops.force_speed_duplex(hw);
1216
DEBUGOUT("Error Forcing Speed and Duplex\n");
1223
* Check link status. Wait up to 100 microseconds for link to become
1226
ret_val = igb_phy_has_link_generic(hw,
1227
COPPER_LINK_UP_LIMIT,
1234
DEBUGOUT("Valid link established!!!\n");
1235
igb_config_collision_dist_generic(hw);
1236
ret_val = igb_config_fc_after_link_up_generic(hw);
1238
DEBUGOUT("Unable to establish link!!!\n");
1247
* igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1248
* @hw: pointer to the HW structure
1250
* Calls the PHY setup function to force speed and duplex. Clears the
1251
* auto-crossover to force MDI manually. Waits for link and returns
1252
* successful if link up is successful, else -E1000_ERR_PHY (-2).
1254
s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1256
struct e1000_phy_info *phy = &hw->phy;
1261
DEBUGFUNC("igb_phy_force_speed_duplex_igp");
1263
ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1267
igb_phy_force_speed_duplex_setup(hw, &phy_data);
1269
ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1274
* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1275
* forced whenever speed and duplex are forced.
1277
ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1281
phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1282
phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1284
ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1288
DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1292
if (phy->autoneg_wait_to_complete) {
1293
DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1295
ret_val = igb_phy_has_link_generic(hw,
1303
DEBUGOUT("Link taking longer than expected.\n");
1306
ret_val = igb_phy_has_link_generic(hw,
1321
* igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1322
* @hw: pointer to the HW structure
1324
* Calls the PHY setup function to force speed and duplex. Clears the
1325
* auto-crossover to force MDI manually. Resets the PHY to commit the
1326
* changes. If time expires while waiting for link up, we reset the DSP.
1327
* After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1328
* successful completion, else return corresponding error code.
1330
s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1332
struct e1000_phy_info *phy = &hw->phy;
1337
DEBUGFUNC("igb_phy_force_speed_duplex_m88");
1340
* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1341
* forced whenever speed and duplex are forced.
1343
ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1347
phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1348
ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1352
DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1354
ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1358
igb_phy_force_speed_duplex_setup(hw, &phy_data);
1360
ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1364
/* Reset the phy to commit changes. */
1365
ret_val = hw->phy.ops.commit(hw);
1369
if (phy->autoneg_wait_to_complete) {
1370
DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1372
ret_val = igb_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1379
* We didn't get link.
1380
* Reset the DSP and cross our fingers.
1382
ret_val = phy->ops.write_reg(hw,
1383
M88E1000_PHY_PAGE_SELECT,
1387
ret_val = igb_phy_reset_dsp_generic(hw);
1393
ret_val = igb_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1399
ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1404
* Resetting the phy means we need to re-force TX_CLK in the
1405
* Extended PHY Specific Control Register to 25MHz clock from
1406
* the reset value of 2.5MHz.
1408
phy_data |= M88E1000_EPSCR_TX_CLK_25;
1409
ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1414
* In addition, we must re-enable CRS on Tx for both half and full
1417
ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1421
phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1422
ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1431
* igb_phy_force_speed_duplex_ife - Force PHY speed & duplex
1432
* @hw: pointer to the HW structure
1434
* Forces the speed and duplex settings of the PHY.
1435
* This is a function pointer entry point only called by
1436
* PHY setup routines.
1438
s32 igb_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1440
struct e1000_phy_info *phy = &hw->phy;
1445
DEBUGFUNC("igb_phy_force_speed_duplex_ife");
1447
if (phy->type != e1000_phy_ife) {
1448
ret_val = igb_phy_force_speed_duplex_igp(hw);
1452
ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1456
igb_phy_force_speed_duplex_setup(hw, &data);
1458
ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1462
/* Disable MDI-X support for 10/100 */
1463
ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1467
data &= ~IFE_PMC_AUTO_MDIX;
1468
data &= ~IFE_PMC_FORCE_MDIX;
1470
ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1474
DEBUGOUT1("IFE PMC: %X\n", data);
1478
if (phy->autoneg_wait_to_complete) {
1479
DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1481
ret_val = igb_phy_has_link_generic(hw,
1489
DEBUGOUT("Link taking longer than expected.\n");
1492
ret_val = igb_phy_has_link_generic(hw,
1507
* igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1508
* @hw: pointer to the HW structure
1509
* @phy_ctrl: pointer to current value of PHY_CONTROL
1511
* Forces speed and duplex on the PHY by doing the following: disable flow
1512
* control, force speed/duplex on the MAC, disable auto speed detection,
1513
* disable auto-negotiation, configure duplex, configure speed, configure
1514
* the collision distance, write configuration to CTRL register. The
1515
* caller must write to the PHY_CONTROL register for these settings to
1518
void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1520
struct e1000_mac_info *mac = &hw->mac;
1523
DEBUGFUNC("igb_phy_force_speed_duplex_setup");
1525
/* Turn off flow control when forcing speed/duplex */
1526
hw->fc.current_mode = e1000_fc_none;
1528
/* Force speed/duplex on the mac */
1529
ctrl = E1000_READ_REG(hw, E1000_CTRL);
1530
ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1531
ctrl &= ~E1000_CTRL_SPD_SEL;
1533
/* Disable Auto Speed Detection */
1534
ctrl &= ~E1000_CTRL_ASDE;
1536
/* Disable autoneg on the phy */
1537
*phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1539
/* Forcing Full or Half Duplex? */
1540
if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1541
ctrl &= ~E1000_CTRL_FD;
1542
*phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1543
DEBUGOUT("Half Duplex\n");
1545
ctrl |= E1000_CTRL_FD;
1546
*phy_ctrl |= MII_CR_FULL_DUPLEX;
1547
DEBUGOUT("Full Duplex\n");
1550
/* Forcing 10mb or 100mb? */
1551
if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1552
ctrl |= E1000_CTRL_SPD_100;
1553
*phy_ctrl |= MII_CR_SPEED_100;
1554
*phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1555
DEBUGOUT("Forcing 100mb\n");
1557
ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1558
*phy_ctrl |= MII_CR_SPEED_10;
1559
*phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1560
DEBUGOUT("Forcing 10mb\n");
1563
igb_config_collision_dist_generic(hw);
1565
E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1570
* igb_set_d3_lplu_state_generic - Sets low power link up state for D3
1571
* @hw: pointer to the HW structure
1572
* @active: boolean used to enable/disable lplu
1574
* Success returns 0, Failure returns 1
1576
* The low power link up (lplu) state is set to the power management level D3
1577
* and SmartSpeed is disabled when active is true, else clear lplu for D3
1578
* and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1579
* is used during Dx states where the power conservation is most important.
1580
* During driver activity, SmartSpeed should be enabled so performance is
1583
s32 igb_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
1585
struct e1000_phy_info *phy = &hw->phy;
1586
s32 ret_val = E1000_SUCCESS;
1589
DEBUGFUNC("igb_set_d3_lplu_state_generic");
1591
if (!(hw->phy.ops.read_reg))
1594
ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1599
data &= ~IGP02E1000_PM_D3_LPLU;
1600
ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1605
* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1606
* during Dx states where the power conservation is most
1607
* important. During driver activity we should enable
1608
* SmartSpeed, so performance is maintained.
1610
if (phy->smart_speed == e1000_smart_speed_on) {
1611
ret_val = phy->ops.read_reg(hw,
1612
IGP01E1000_PHY_PORT_CONFIG,
1617
data |= IGP01E1000_PSCFR_SMART_SPEED;
1618
ret_val = phy->ops.write_reg(hw,
1619
IGP01E1000_PHY_PORT_CONFIG,
1623
} else if (phy->smart_speed == e1000_smart_speed_off) {
1624
ret_val = phy->ops.read_reg(hw,
1625
IGP01E1000_PHY_PORT_CONFIG,
1630
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1631
ret_val = phy->ops.write_reg(hw,
1632
IGP01E1000_PHY_PORT_CONFIG,
1637
} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1638
(phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1639
(phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1640
data |= IGP02E1000_PM_D3_LPLU;
1641
ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1646
/* When LPLU is enabled, we should disable SmartSpeed */
1647
ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1652
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1653
ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1662
* igb_check_downshift_generic - Checks whether a downshift in speed occurred
1663
* @hw: pointer to the HW structure
1665
* Success returns 0, Failure returns 1
1667
* A downshift is detected by querying the PHY link health.
1669
s32 igb_check_downshift_generic(struct e1000_hw *hw)
1671
struct e1000_phy_info *phy = &hw->phy;
1673
u16 phy_data, offset, mask;
1675
DEBUGFUNC("igb_check_downshift_generic");
1677
switch (phy->type) {
1679
case e1000_phy_gg82563:
1680
offset = M88E1000_PHY_SPEC_STATUS;
1681
mask = M88E1000_PSSR_DOWNSHIFT;
1683
case e1000_phy_igp_2:
1685
case e1000_phy_igp_3:
1686
offset = IGP01E1000_PHY_LINK_HEALTH;
1687
mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1690
/* speed downshift not supported */
1691
phy->speed_downgraded = false;
1692
ret_val = E1000_SUCCESS;
1696
ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1699
phy->speed_downgraded = (phy_data & mask) ? true : false;
1706
* igb_check_polarity_m88 - Checks the polarity.
1707
* @hw: pointer to the HW structure
1709
* Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1711
* Polarity is determined based on the PHY specific status register.
1713
s32 igb_check_polarity_m88(struct e1000_hw *hw)
1715
struct e1000_phy_info *phy = &hw->phy;
1719
DEBUGFUNC("igb_check_polarity_m88");
1721
ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1724
phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1725
? e1000_rev_polarity_reversed
1726
: e1000_rev_polarity_normal;
1732
* igb_check_polarity_igp - Checks the polarity.
1733
* @hw: pointer to the HW structure
1735
* Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1737
* Polarity is determined based on the PHY port status register, and the
1738
* current speed (since there is no polarity at 100Mbps).
1740
s32 igb_check_polarity_igp(struct e1000_hw *hw)
1742
struct e1000_phy_info *phy = &hw->phy;
1744
u16 data, offset, mask;
1746
DEBUGFUNC("igb_check_polarity_igp");
1749
* Polarity is determined based on the speed of
1752
ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1756
if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1757
IGP01E1000_PSSR_SPEED_1000MBPS) {
1758
offset = IGP01E1000_PHY_PCS_INIT_REG;
1759
mask = IGP01E1000_PHY_POLARITY_MASK;
1762
* This really only applies to 10Mbps since
1763
* there is no polarity for 100Mbps (always 0).
1765
offset = IGP01E1000_PHY_PORT_STATUS;
1766
mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1769
ret_val = phy->ops.read_reg(hw, offset, &data);
1772
phy->cable_polarity = (data & mask)
1773
? e1000_rev_polarity_reversed
1774
: e1000_rev_polarity_normal;
1781
* igb_check_polarity_ife - Check cable polarity for IFE PHY
1782
* @hw: pointer to the HW structure
1784
* Polarity is determined on the polarity reversal feature being enabled.
1786
s32 igb_check_polarity_ife(struct e1000_hw *hw)
1788
struct e1000_phy_info *phy = &hw->phy;
1790
u16 phy_data, offset, mask;
1792
DEBUGFUNC("igb_check_polarity_ife");
1795
* Polarity is determined based on the reversal feature being enabled.
1797
if (phy->polarity_correction) {
1798
offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1799
mask = IFE_PESC_POLARITY_REVERSED;
1801
offset = IFE_PHY_SPECIAL_CONTROL;
1802
mask = IFE_PSC_FORCE_POLARITY;
1805
ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1808
phy->cable_polarity = (phy_data & mask)
1809
? e1000_rev_polarity_reversed
1810
: e1000_rev_polarity_normal;
1816
* igb_wait_autoneg_generic - Wait for auto-neg completion
1817
* @hw: pointer to the HW structure
1819
* Waits for auto-negotiation to complete or for the auto-negotiation time
1820
* limit to expire, which ever happens first.
1822
s32 igb_wait_autoneg_generic(struct e1000_hw *hw)
1824
s32 ret_val = E1000_SUCCESS;
1827
DEBUGFUNC("igb_wait_autoneg_generic");
1829
if (!(hw->phy.ops.read_reg))
1830
return E1000_SUCCESS;
1832
/* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1833
for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1834
ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1837
ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1840
if (phy_status & MII_SR_AUTONEG_COMPLETE)
1846
* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1853
* igb_phy_has_link_generic - Polls PHY for link
1854
* @hw: pointer to the HW structure
1855
* @iterations: number of times to poll for link
1856
* @usec_interval: delay between polling attempts
1857
* @success: pointer to whether polling was successful or not
1859
* Polls the PHY status register for link, 'iterations' number of times.
1861
s32 igb_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1862
u32 usec_interval, bool *success)
1864
s32 ret_val = E1000_SUCCESS;
1867
DEBUGFUNC("igb_phy_has_link_generic");
1869
if (!(hw->phy.ops.read_reg))
1870
return E1000_SUCCESS;
1872
for (i = 0; i < iterations; i++) {
1874
* Some PHYs require the PHY_STATUS register to be read
1875
* twice due to the link bit being sticky. No harm doing
1876
* it across the board.
1878
ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1881
* If the first read fails, another entity may have
1882
* ownership of the resources, wait and try again to
1883
* see if they have relinquished the resources yet.
1885
usec_delay(usec_interval);
1887
ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1890
if (phy_status & MII_SR_LINK_STATUS)
1892
if (usec_interval >= 1000)
1893
msec_delay_irq(usec_interval/1000);
1895
usec_delay(usec_interval);
1898
*success = (i < iterations) ? true : false;
1905
* igb_get_cable_length_m88 - Determine cable length for m88 PHY
1906
* @hw: pointer to the HW structure
1908
* Reads the PHY specific status register to retrieve the cable length
1909
* information. The cable length is determined by averaging the minimum and
1910
* maximum values to get the "average" cable length. The m88 PHY has four
1911
* possible cable length values, which are:
1912
* Register Value Cable Length
1916
* 3 110 - 140 meters
1919
s32 igb_get_cable_length_m88(struct e1000_hw *hw)
1921
struct e1000_phy_info *phy = &hw->phy;
1923
u16 phy_data, index;
1925
DEBUGFUNC("igb_get_cable_length_m88");
1927
ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1931
index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1932
M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1933
if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
1934
ret_val = -E1000_ERR_PHY;
1938
phy->min_cable_length = e1000_m88_cable_length_table[index];
1939
phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1941
phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1948
* igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1949
* @hw: pointer to the HW structure
1951
* The automatic gain control (agc) normalizes the amplitude of the
1952
* received signal, adjusting for the attenuation produced by the
1953
* cable. By reading the AGC registers, which represent the
1954
* combination of coarse and fine gain value, the value can be put
1955
* into a lookup table to obtain the approximate cable length
1958
s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
1960
struct e1000_phy_info *phy = &hw->phy;
1961
s32 ret_val = E1000_SUCCESS;
1962
u16 phy_data, i, agc_value = 0;
1963
u16 cur_agc_index, max_agc_index = 0;
1964
u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1965
u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
1966
{IGP02E1000_PHY_AGC_A,
1967
IGP02E1000_PHY_AGC_B,
1968
IGP02E1000_PHY_AGC_C,
1969
IGP02E1000_PHY_AGC_D};
1971
DEBUGFUNC("igb_get_cable_length_igp_2");
1973
/* Read the AGC registers for all channels */
1974
for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1975
ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
1980
* Getting bits 15:9, which represent the combination of
1981
* coarse and fine gain values. The result is a number
1982
* that can be put into the lookup table to obtain the
1983
* approximate cable length.
1985
cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1986
IGP02E1000_AGC_LENGTH_MASK;
1988
/* Array index bound check. */
1989
if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1990
(cur_agc_index == 0)) {
1991
ret_val = -E1000_ERR_PHY;
1995
/* Remove min & max AGC values from calculation. */
1996
if (e1000_igp_2_cable_length_table[min_agc_index] >
1997
e1000_igp_2_cable_length_table[cur_agc_index])
1998
min_agc_index = cur_agc_index;
1999
if (e1000_igp_2_cable_length_table[max_agc_index] <
2000
e1000_igp_2_cable_length_table[cur_agc_index])
2001
max_agc_index = cur_agc_index;
2003
agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2006
agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2007
e1000_igp_2_cable_length_table[max_agc_index]);
2008
agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2010
/* Calculate cable length with the error range of +/- 10 meters. */
2011
phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2012
(agc_value - IGP02E1000_AGC_RANGE) : 0;
2013
phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2015
phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2023
* igb_get_phy_info_m88 - Retrieve PHY information
2024
* @hw: pointer to the HW structure
2026
* Valid for only copper links. Read the PHY status register (sticky read)
2027
* to verify that link is up. Read the PHY special control register to
2028
* determine the polarity and 10base-T extended distance. Read the PHY
2029
* special status register to determine MDI/MDIx and current speed. If
2030
* speed is 1000, then determine cable length, local and remote receiver.
2032
s32 igb_get_phy_info_m88(struct e1000_hw *hw)
2034
struct e1000_phy_info *phy = &hw->phy;
2039
DEBUGFUNC("igb_get_phy_info_m88");
2041
if (phy->media_type != e1000_media_type_copper) {
2042
DEBUGOUT("Phy info is only valid for copper media\n");
2043
ret_val = -E1000_ERR_CONFIG;
2047
ret_val = igb_phy_has_link_generic(hw, 1, 0, &link);
2052
DEBUGOUT("Phy info is only valid if link is up\n");
2053
ret_val = -E1000_ERR_CONFIG;
2057
ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2061
phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
2064
ret_val = igb_check_polarity_m88(hw);
2068
ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2072
phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
2074
if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2076
ret_val = hw->phy.ops.get_cable_length(hw);
2078
ret_val = -E1000_ERR_CONFIG;
2082
ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2086
phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2087
? e1000_1000t_rx_status_ok
2088
: e1000_1000t_rx_status_not_ok;
2090
phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2091
? e1000_1000t_rx_status_ok
2092
: e1000_1000t_rx_status_not_ok;
2095
/* Set values to "undefined" */
2096
phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2097
phy->local_rx = e1000_1000t_rx_status_undefined;
2098
phy->remote_rx = e1000_1000t_rx_status_undefined;
2106
* igb_get_phy_info_igp - Retrieve igp PHY information
2107
* @hw: pointer to the HW structure
2109
* Read PHY status to determine if link is up. If link is up, then
2110
* set/determine 10base-T extended distance and polarity correction. Read
2111
* PHY port status to determine MDI/MDIx and speed. Based on the speed,
2112
* determine on the cable length, local and remote receiver.
2114
s32 igb_get_phy_info_igp(struct e1000_hw *hw)
2116
struct e1000_phy_info *phy = &hw->phy;
2121
DEBUGFUNC("igb_get_phy_info_igp");
2123
ret_val = igb_phy_has_link_generic(hw, 1, 0, &link);
2128
DEBUGOUT("Phy info is only valid if link is up\n");
2129
ret_val = -E1000_ERR_CONFIG;
2133
phy->polarity_correction = true;
2135
ret_val = igb_check_polarity_igp(hw);
2139
ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2143
phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
2145
if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2146
IGP01E1000_PSSR_SPEED_1000MBPS) {
2148
ret_val = phy->ops.get_cable_length(hw);
2150
ret_val = -E1000_ERR_CONFIG;
2154
ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2158
phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2159
? e1000_1000t_rx_status_ok
2160
: e1000_1000t_rx_status_not_ok;
2162
phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2163
? e1000_1000t_rx_status_ok
2164
: e1000_1000t_rx_status_not_ok;
2167
phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2168
phy->local_rx = e1000_1000t_rx_status_undefined;
2169
phy->remote_rx = e1000_1000t_rx_status_undefined;
2177
* igb_phy_sw_reset_generic - PHY software reset
2178
* @hw: pointer to the HW structure
2180
* Does a software reset of the PHY by reading the PHY control register and
2181
* setting/write the control register reset bit to the PHY.
2183
s32 igb_phy_sw_reset_generic(struct e1000_hw *hw)
2185
s32 ret_val = E1000_SUCCESS;
2188
DEBUGFUNC("igb_phy_sw_reset_generic");
2190
if (!(hw->phy.ops.read_reg))
2193
ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2197
phy_ctrl |= MII_CR_RESET;
2198
ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2209
* igb_phy_hw_reset_generic - PHY hardware reset
2210
* @hw: pointer to the HW structure
2212
* Verify the reset block is not blocking us from resetting. Acquire
2213
* semaphore (if necessary) and read/set/write the device control reset
2214
* bit in the PHY. Wait the appropriate delay time for the device to
2215
* reset and release the semaphore (if necessary).
2217
s32 igb_phy_hw_reset_generic(struct e1000_hw *hw)
2219
struct e1000_phy_info *phy = &hw->phy;
2220
s32 ret_val = E1000_SUCCESS;
2223
DEBUGFUNC("igb_phy_hw_reset_generic");
2225
ret_val = phy->ops.check_reset_block(hw);
2227
ret_val = E1000_SUCCESS;
2231
ret_val = phy->ops.acquire(hw);
2235
ctrl = E1000_READ_REG(hw, E1000_CTRL);
2236
E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2237
E1000_WRITE_FLUSH(hw);
2239
usec_delay(phy->reset_delay_us);
2241
E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2242
E1000_WRITE_FLUSH(hw);
2246
phy->ops.release(hw);
2248
ret_val = phy->ops.get_cfg_done(hw);
2255
* igb_get_cfg_done_generic - Generic configuration done
2256
* @hw: pointer to the HW structure
2258
* Generic function to wait 10 milli-seconds for configuration to complete
2259
* and return success.
2261
s32 igb_get_cfg_done_generic(struct e1000_hw *hw __unused)
2263
DEBUGFUNC("igb_get_cfg_done_generic");
2267
return E1000_SUCCESS;
2271
* igb_phy_init_script_igp3 - Inits the IGP3 PHY
2272
* @hw: pointer to the HW structure
2274
* Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2276
s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
2278
DEBUGOUT("Running IGP 3 PHY init script\n");
2280
/* PHY init IGP 3 */
2281
/* Enable rise/fall, 10-mode work in class-A */
2282
hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2283
/* Remove all caps from Replica path filter */
2284
hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2285
/* Bias trimming for ADC, AFE and Driver (Default) */
2286
hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2287
/* Increase Hybrid poly bias */
2288
hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2289
/* Add 4% to Tx amplitude in Gig mode */
2290
hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2291
/* Disable trimming (TTT) */
2292
hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2293
/* Poly DC correction to 94.6% + 2% for all channels */
2294
hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2295
/* ABS DC correction to 95.9% */
2296
hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2297
/* BG temp curve trim */
2298
hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2299
/* Increasing ADC OPAMP stage 1 currents to max */
2300
hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2301
/* Force 1000 ( required for enabling PHY regs configuration) */
2302
hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2303
/* Set upd_freq to 6 */
2304
hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2306
hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2307
/* Disable adaptive fixed FFE (Default) */
2308
hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2309
/* Enable FFE hysteresis */
2310
hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2311
/* Fixed FFE for short cable lengths */
2312
hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2313
/* Fixed FFE for medium cable lengths */
2314
hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2315
/* Fixed FFE for long cable lengths */
2316
hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2317
/* Enable Adaptive Clip Threshold */
2318
hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2319
/* AHT reset limit to 1 */
2320
hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2321
/* Set AHT master delay to 127 msec */
2322
hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2323
/* Set scan bits for AHT */
2324
hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2325
/* Set AHT Preset bits */
2326
hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2327
/* Change integ_factor of channel A to 3 */
2328
hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2329
/* Change prop_factor of channels BCD to 8 */
2330
hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2331
/* Change cg_icount + enable integbp for channels BCD */
2332
hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2334
* Change cg_icount + enable integbp + change prop_factor_master
2335
* to 8 for channel A
2337
hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2338
/* Disable AHT in Slave mode on channel A */
2339
hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2341
* Enable LPLU and disable AN to 1000 in non-D0a states,
2344
hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2345
/* Enable restart AN on an1000_dis change */
2346
hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2347
/* Enable wh_fifo read clock in 10/100 modes */
2348
hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2349
/* Restart AN, Speed selection is 1000 */
2350
hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2352
return E1000_SUCCESS;
2356
* igb_get_phy_type_from_id - Get PHY type from id
2357
* @phy_id: phy_id read from the phy
2359
* Returns the phy type from the id.
2361
enum e1000_phy_type igb_get_phy_type_from_id(u32 phy_id)
2363
enum e1000_phy_type phy_type = e1000_phy_unknown;
2366
case M88E1000_I_PHY_ID:
2367
case M88E1000_E_PHY_ID:
2368
case M88E1111_I_PHY_ID:
2369
case M88E1011_I_PHY_ID:
2370
phy_type = e1000_phy_m88;
2372
case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2373
phy_type = e1000_phy_igp_2;
2375
case GG82563_E_PHY_ID:
2376
phy_type = e1000_phy_gg82563;
2378
case IGP03E1000_E_PHY_ID:
2379
phy_type = e1000_phy_igp_3;
2382
case IFE_PLUS_E_PHY_ID:
2383
case IFE_C_E_PHY_ID:
2384
phy_type = e1000_phy_ife;
2387
phy_type = e1000_phy_unknown;
2394
* igb_determine_phy_address - Determines PHY address.
2395
* @hw: pointer to the HW structure
2397
* This uses a trial and error method to loop through possible PHY
2398
* addresses. It tests each by reading the PHY ID registers and
2399
* checking for a match.
2401
s32 igb_determine_phy_address(struct e1000_hw *hw)
2403
s32 ret_val = -E1000_ERR_PHY_TYPE;
2406
enum e1000_phy_type phy_type = e1000_phy_unknown;
2408
hw->phy.id = phy_type;
2410
for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2411
hw->phy.addr = phy_addr;
2416
phy_type = igb_get_phy_type_from_id(hw->phy.id);
2419
* If phy_type is valid, break - we found our
2422
if (phy_type != e1000_phy_unknown) {
2423
ret_val = E1000_SUCCESS;
2436
* igb_power_up_phy_copper - Restore copper link in case of PHY power down
2437
* @hw: pointer to the HW structure
2439
* In the case of a PHY power down to save power, or to turn off link during a
2440
* driver unload, or wake on lan is not enabled, restore the link to previous
2443
void igb_power_up_phy_copper(struct e1000_hw *hw)
2447
/* The PHY will retain its settings across a power down/up cycle */
2448
hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2449
mii_reg &= ~MII_CR_POWER_DOWN;
2450
hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2454
* igb_power_down_phy_copper - Restore copper link in case of PHY power down
2455
* @hw: pointer to the HW structure
2457
* In the case of a PHY power down to save power, or to turn off link during a
2458
* driver unload, or wake on lan is not enabled, restore the link to previous
2461
void igb_power_down_phy_copper(struct e1000_hw *hw)
2465
/* The PHY will retain its settings across a power down/up cycle */
2466
hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2467
mii_reg |= MII_CR_POWER_DOWN;
2468
hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
added
removed
src/drivers/net/igb/igb_phy.c
