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/*******************************************************************************
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Intel(R) Gigabit Ethernet Linux driver
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Copyright(c) 2007-2009 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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FILE_LICENCE ( GPL2_ONLY );
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static s32 igb_set_default_fc_generic(struct e1000_hw *hw);
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static s32 igb_commit_fc_settings_generic(struct e1000_hw *hw);
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static s32 igb_poll_fiber_serdes_link_generic(struct e1000_hw *hw);
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static s32 igb_validate_mdi_setting_generic(struct e1000_hw *hw);
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static void igb_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
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* igb_init_mac_ops_generic - Initialize MAC function pointers
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* @hw: pointer to the HW structure
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* Setups up the function pointers to no-op functions
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void igb_init_mac_ops_generic(struct e1000_hw *hw)
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struct e1000_mac_info *mac = &hw->mac;
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DEBUGFUNC("igb_init_mac_ops_generic");
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mac->ops.set_lan_id = igb_set_lan_id_multi_port_pcie;
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mac->ops.read_mac_addr = igb_read_mac_addr_generic;
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mac->ops.config_collision_dist = igb_config_collision_dist_generic;
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mac->ops.wait_autoneg = igb_wait_autoneg_generic;
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mac->ops.mng_host_if_write = igb_mng_host_if_write_generic;
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mac->ops.mng_write_cmd_header = igb_mng_write_cmd_header_generic;
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mac->ops.mng_enable_host_if = igb_mng_enable_host_if_generic;
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mac->ops.rar_set = igb_rar_set_generic;
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mac->ops.validate_mdi_setting = igb_validate_mdi_setting_generic;
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* igb_get_bus_info_pcie_generic - Get PCIe bus information
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* @hw: pointer to the HW structure
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* Determines and stores the system bus information for a particular
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* network interface. The following bus information is determined and stored:
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* bus speed, bus width, type (PCIe), and PCIe function.
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s32 igb_get_bus_info_pcie_generic(struct e1000_hw *hw)
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struct e1000_mac_info *mac = &hw->mac;
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struct e1000_bus_info *bus = &hw->bus;
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DEBUGFUNC("igb_get_bus_info_pcie_generic");
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bus->type = e1000_bus_type_pci_express;
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bus->speed = e1000_bus_speed_2500;
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ret_val = igb_read_pcie_cap_reg(hw,
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bus->width = e1000_bus_width_unknown;
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bus->width = (enum e1000_bus_width)((pcie_link_status &
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PCIE_LINK_WIDTH_MASK) >>
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PCIE_LINK_WIDTH_SHIFT);
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mac->ops.set_lan_id(hw);
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* igb_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
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* @hw: pointer to the HW structure
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* Determines the LAN function id by reading memory-mapped registers
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* and swaps the port value if requested.
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static void igb_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
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struct e1000_bus_info *bus = &hw->bus;
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* The status register reports the correct function number
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* for the device regardless of function swap state.
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reg = E1000_READ_REG(hw, E1000_STATUS);
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bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
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* igb_set_lan_id_single_port - Set LAN id for a single port device
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* @hw: pointer to the HW structure
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* Sets the LAN function id to zero for a single port device.
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void igb_set_lan_id_single_port(struct e1000_hw *hw)
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struct e1000_bus_info *bus = &hw->bus;
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* igb_clear_vfta_generic - Clear VLAN filter table
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* @hw: pointer to the HW structure
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* Clears the register array which contains the VLAN filter table by
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* setting all the values to 0.
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void igb_clear_vfta_generic(struct e1000_hw *hw)
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DEBUGFUNC("igb_clear_vfta_generic");
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for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
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E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
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E1000_WRITE_FLUSH(hw);
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* igb_write_vfta_generic - Write value to VLAN filter table
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* @hw: pointer to the HW structure
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* @offset: register offset in VLAN filter table
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* @value: register value written to VLAN filter table
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* Writes value at the given offset in the register array which stores
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* the VLAN filter table.
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void igb_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
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DEBUGFUNC("igb_write_vfta_generic");
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E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
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E1000_WRITE_FLUSH(hw);
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* igb_init_rx_addrs_generic - Initialize receive address's
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* @hw: pointer to the HW structure
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* @rar_count: receive address registers
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* Setups the receive address registers by setting the base receive address
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* register to the devices MAC address and clearing all the other receive
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* address registers to 0.
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void igb_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
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u8 mac_addr[ETH_ADDR_LEN] = {0};
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DEBUGFUNC("igb_init_rx_addrs_generic");
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/* Setup the receive address */
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DEBUGOUT("Programming MAC Address into RAR[0]\n");
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hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
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/* Zero out the other (rar_entry_count - 1) receive addresses */
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DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
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for (i = 1; i < rar_count; i++)
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hw->mac.ops.rar_set(hw, mac_addr, i);
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* igb_check_alt_mac_addr_generic - Check for alternate MAC addr
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* @hw: pointer to the HW structure
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* Checks the nvm for an alternate MAC address. An alternate MAC address
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* can be setup by pre-boot software and must be treated like a permanent
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* address and must override the actual permanent MAC address. If an
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* alternate MAC address is found it is programmed into RAR0, replacing
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* the permanent address that was installed into RAR0 by the Si on reset.
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* This function will return SUCCESS unless it encounters an error while
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* reading the EEPROM.
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s32 igb_check_alt_mac_addr_generic(struct e1000_hw *hw)
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s32 ret_val = E1000_SUCCESS;
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u16 offset, nvm_alt_mac_addr_offset, nvm_data;
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u8 alt_mac_addr[ETH_ADDR_LEN];
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DEBUGFUNC("igb_check_alt_mac_addr_generic");
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ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
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&nvm_alt_mac_addr_offset);
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DEBUGOUT("NVM Read Error\n");
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if (nvm_alt_mac_addr_offset == 0xFFFF) {
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/* There is no Alternate MAC Address */
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if (hw->bus.func == E1000_FUNC_1)
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nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
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for (i = 0; i < ETH_ADDR_LEN; i += 2) {
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offset = nvm_alt_mac_addr_offset + (i >> 1);
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ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
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DEBUGOUT("NVM Read Error\n");
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alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
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alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
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/* if multicast bit is set, the alternate address will not be used */
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if (alt_mac_addr[0] & 0x01) {
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DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
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* We have a valid alternate MAC address, and we want to treat it the
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* same as the normal permanent MAC address stored by the HW into the
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* RAR. Do this by mapping this address into RAR0.
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hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
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* igb_rar_set_generic - Set receive address register
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* @hw: pointer to the HW structure
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* @addr: pointer to the receive address
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* @index: receive address array register
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* Sets the receive address array register at index to the address passed
272
void igb_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
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u32 rar_low, rar_high;
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DEBUGFUNC("igb_rar_set_generic");
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* HW expects these in little endian so we reverse the byte order
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* from network order (big endian) to little endian
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rar_low = ((u32) addr[0] |
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((u32) addr[1] << 8) |
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((u32) addr[2] << 16) | ((u32) addr[3] << 24));
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rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
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/* If MAC address zero, no need to set the AV bit */
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if (rar_low || rar_high)
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rar_high |= E1000_RAH_AV;
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* Some bridges will combine consecutive 32-bit writes into
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* a single burst write, which will malfunction on some parts.
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* The flushes avoid this.
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E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
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E1000_WRITE_FLUSH(hw);
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E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
300
E1000_WRITE_FLUSH(hw);
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* igb_mta_set_generic - Set multicast filter table address
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* @hw: pointer to the HW structure
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* @hash_value: determines the MTA register and bit to set
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* The multicast table address is a register array of 32-bit registers.
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* The hash_value is used to determine what register the bit is in, the
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* current value is read, the new bit is OR'd in and the new value is
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* written back into the register.
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void igb_mta_set_generic(struct e1000_hw *hw, u32 hash_value)
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u32 hash_bit, hash_reg, mta;
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DEBUGFUNC("igb_mta_set_generic");
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* The MTA is a register array of 32-bit registers. It is
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* treated like an array of (32*mta_reg_count) bits. We want to
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* set bit BitArray[hash_value]. So we figure out what register
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* the bit is in, read it, OR in the new bit, then write
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* back the new value. The (hw->mac.mta_reg_count - 1) serves as a
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* mask to bits 31:5 of the hash value which gives us the
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* register we're modifying. The hash bit within that register
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* is determined by the lower 5 bits of the hash value.
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hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
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hash_bit = hash_value & 0x1F;
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mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg);
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mta |= (1 << hash_bit);
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E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta);
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E1000_WRITE_FLUSH(hw);
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* igb_update_mc_addr_list_generic - Update Multicast addresses
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* @hw: pointer to the HW structure
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* @mc_addr_list: array of multicast addresses to program
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* @mc_addr_count: number of multicast addresses to program
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* Updates entire Multicast Table Array.
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* The caller must have a packed mc_addr_list of multicast addresses.
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void igb_update_mc_addr_list_generic(struct e1000_hw *hw,
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u8 *mc_addr_list, u32 mc_addr_count)
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u32 hash_value, hash_bit, hash_reg;
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DEBUGFUNC("igb_update_mc_addr_list_generic");
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/* clear mta_shadow */
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memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
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/* update mta_shadow from mc_addr_list */
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for (i = 0; (u32) i < mc_addr_count; i++) {
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hash_value = igb_hash_mc_addr_generic(hw, mc_addr_list);
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hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
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hash_bit = hash_value & 0x1F;
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hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
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mc_addr_list += (ETH_ADDR_LEN);
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/* replace the entire MTA table */
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for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
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E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
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E1000_WRITE_FLUSH(hw);
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* igb_hash_mc_addr_generic - Generate a multicast hash value
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* @hw: pointer to the HW structure
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* @mc_addr: pointer to a multicast address
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* Generates a multicast address hash value which is used to determine
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* the multicast filter table array address and new table value. See
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* igb_mta_set_generic()
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u32 igb_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
387
u32 hash_value, hash_mask;
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DEBUGFUNC("igb_hash_mc_addr_generic");
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/* Register count multiplied by bits per register */
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hash_mask = (hw->mac.mta_reg_count * 32) - 1;
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* For a mc_filter_type of 0, bit_shift is the number of left-shifts
397
* where 0xFF would still fall within the hash mask.
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while (hash_mask >> bit_shift != 0xFF)
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* The portion of the address that is used for the hash table
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* is determined by the mc_filter_type setting.
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* The algorithm is such that there is a total of 8 bits of shifting.
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* The bit_shift for a mc_filter_type of 0 represents the number of
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* left-shifts where the MSB of mc_addr[5] would still fall within
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* the hash_mask. Case 0 does this exactly. Since there are a total
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* of 8 bits of shifting, then mc_addr[4] will shift right the
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* remaining number of bits. Thus 8 - bit_shift. The rest of the
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* cases are a variation of this algorithm...essentially raising the
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* number of bits to shift mc_addr[5] left, while still keeping the
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* 8-bit shifting total.
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* For example, given the following Destination MAC Address and an
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* mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
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* we can see that the bit_shift for case 0 is 4. These are the hash
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* values resulting from each mc_filter_type...
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* [0] [1] [2] [3] [4] [5]
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* case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
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* case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
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* case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
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* case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
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switch (hw->mac.mc_filter_type) {
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hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
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(((u16) mc_addr[5]) << bit_shift)));
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* igb_clear_hw_cntrs_base_generic - Clear base hardware counters
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* @hw: pointer to the HW structure
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* Clears the base hardware counters by reading the counter registers.
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void igb_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
457
DEBUGFUNC("igb_clear_hw_cntrs_base_generic");
459
E1000_READ_REG(hw, E1000_CRCERRS);
460
E1000_READ_REG(hw, E1000_SYMERRS);
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E1000_READ_REG(hw, E1000_MPC);
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E1000_READ_REG(hw, E1000_SCC);
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E1000_READ_REG(hw, E1000_ECOL);
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E1000_READ_REG(hw, E1000_MCC);
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E1000_READ_REG(hw, E1000_LATECOL);
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E1000_READ_REG(hw, E1000_COLC);
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E1000_READ_REG(hw, E1000_DC);
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E1000_READ_REG(hw, E1000_SEC);
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E1000_READ_REG(hw, E1000_RLEC);
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E1000_READ_REG(hw, E1000_XONRXC);
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E1000_READ_REG(hw, E1000_XONTXC);
472
E1000_READ_REG(hw, E1000_XOFFRXC);
473
E1000_READ_REG(hw, E1000_XOFFTXC);
474
E1000_READ_REG(hw, E1000_FCRUC);
475
E1000_READ_REG(hw, E1000_GPRC);
476
E1000_READ_REG(hw, E1000_BPRC);
477
E1000_READ_REG(hw, E1000_MPRC);
478
E1000_READ_REG(hw, E1000_GPTC);
479
E1000_READ_REG(hw, E1000_GORCL);
480
E1000_READ_REG(hw, E1000_GORCH);
481
E1000_READ_REG(hw, E1000_GOTCL);
482
E1000_READ_REG(hw, E1000_GOTCH);
483
E1000_READ_REG(hw, E1000_RNBC);
484
E1000_READ_REG(hw, E1000_RUC);
485
E1000_READ_REG(hw, E1000_RFC);
486
E1000_READ_REG(hw, E1000_ROC);
487
E1000_READ_REG(hw, E1000_RJC);
488
E1000_READ_REG(hw, E1000_TORL);
489
E1000_READ_REG(hw, E1000_TORH);
490
E1000_READ_REG(hw, E1000_TOTL);
491
E1000_READ_REG(hw, E1000_TOTH);
492
E1000_READ_REG(hw, E1000_TPR);
493
E1000_READ_REG(hw, E1000_TPT);
494
E1000_READ_REG(hw, E1000_MPTC);
495
E1000_READ_REG(hw, E1000_BPTC);
499
* igb_check_for_copper_link_generic - Check for link (Copper)
500
* @hw: pointer to the HW structure
502
* Checks to see of the link status of the hardware has changed. If a
503
* change in link status has been detected, then we read the PHY registers
504
* to get the current speed/duplex if link exists.
506
s32 igb_check_for_copper_link_generic(struct e1000_hw *hw)
508
struct e1000_mac_info *mac = &hw->mac;
512
DEBUGFUNC("igb_check_for_copper_link");
515
* We only want to go out to the PHY registers to see if Auto-Neg
516
* has completed and/or if our link status has changed. The
517
* get_link_status flag is set upon receiving a Link Status
518
* Change or Rx Sequence Error interrupt.
520
if (!mac->get_link_status) {
521
ret_val = E1000_SUCCESS;
526
* First we want to see if the MII Status Register reports
527
* link. If so, then we want to get the current speed/duplex
530
ret_val = igb_phy_has_link_generic(hw, 1, 0, &link);
535
goto out; /* No link detected */
537
mac->get_link_status = false;
540
* Check if there was DownShift, must be checked
541
* immediately after link-up
543
igb_check_downshift_generic(hw);
546
* If we are forcing speed/duplex, then we simply return since
547
* we have already determined whether we have link or not.
550
ret_val = -E1000_ERR_CONFIG;
555
* Auto-Neg is enabled. Auto Speed Detection takes care
556
* of MAC speed/duplex configuration. So we only need to
557
* configure Collision Distance in the MAC.
559
igb_config_collision_dist_generic(hw);
562
* Configure Flow Control now that Auto-Neg has completed.
563
* First, we need to restore the desired flow control
564
* settings because we may have had to re-autoneg with a
565
* different link partner.
567
ret_val = igb_config_fc_after_link_up_generic(hw);
569
DEBUGOUT("Error configuring flow control\n");
576
* igb_check_for_fiber_link_generic - Check for link (Fiber)
577
* @hw: pointer to the HW structure
579
* Checks for link up on the hardware. If link is not up and we have
580
* a signal, then we need to force link up.
582
s32 igb_check_for_fiber_link_generic(struct e1000_hw *hw)
584
struct e1000_mac_info *mac = &hw->mac;
588
s32 ret_val = E1000_SUCCESS;
590
DEBUGFUNC("igb_check_for_fiber_link_generic");
592
ctrl = E1000_READ_REG(hw, E1000_CTRL);
593
status = E1000_READ_REG(hw, E1000_STATUS);
594
rxcw = E1000_READ_REG(hw, E1000_RXCW);
597
* If we don't have link (auto-negotiation failed or link partner
598
* cannot auto-negotiate), the cable is plugged in (we have signal),
599
* and our link partner is not trying to auto-negotiate with us (we
600
* are receiving idles or data), we need to force link up. We also
601
* need to give auto-negotiation time to complete, in case the cable
602
* was just plugged in. The autoneg_failed flag does this.
604
/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
605
if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
606
(!(rxcw & E1000_RXCW_C))) {
607
if (mac->autoneg_failed == 0) {
608
mac->autoneg_failed = 1;
611
DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
613
/* Disable auto-negotiation in the TXCW register */
614
E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
616
/* Force link-up and also force full-duplex. */
617
ctrl = E1000_READ_REG(hw, E1000_CTRL);
618
ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
619
E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
621
/* Configure Flow Control after forcing link up. */
622
ret_val = igb_config_fc_after_link_up_generic(hw);
624
DEBUGOUT("Error configuring flow control\n");
627
} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
629
* If we are forcing link and we are receiving /C/ ordered
630
* sets, re-enable auto-negotiation in the TXCW register
631
* and disable forced link in the Device Control register
632
* in an attempt to auto-negotiate with our link partner.
634
DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
635
E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
636
E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
638
mac->serdes_has_link = true;
646
* igb_check_for_serdes_link_generic - Check for link (Serdes)
647
* @hw: pointer to the HW structure
649
* Checks for link up on the hardware. If link is not up and we have
650
* a signal, then we need to force link up.
652
s32 igb_check_for_serdes_link_generic(struct e1000_hw *hw)
654
struct e1000_mac_info *mac = &hw->mac;
658
s32 ret_val = E1000_SUCCESS;
660
DEBUGFUNC("igb_check_for_serdes_link_generic");
662
ctrl = E1000_READ_REG(hw, E1000_CTRL);
663
status = E1000_READ_REG(hw, E1000_STATUS);
664
rxcw = E1000_READ_REG(hw, E1000_RXCW);
667
* If we don't have link (auto-negotiation failed or link partner
668
* cannot auto-negotiate), and our link partner is not trying to
669
* auto-negotiate with us (we are receiving idles or data),
670
* we need to force link up. We also need to give auto-negotiation
673
/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
674
if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
675
if (mac->autoneg_failed == 0) {
676
mac->autoneg_failed = 1;
679
DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
681
/* Disable auto-negotiation in the TXCW register */
682
E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
684
/* Force link-up and also force full-duplex. */
685
ctrl = E1000_READ_REG(hw, E1000_CTRL);
686
ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
687
E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
689
/* Configure Flow Control after forcing link up. */
690
ret_val = igb_config_fc_after_link_up_generic(hw);
692
DEBUGOUT("Error configuring flow control\n");
695
} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
697
* If we are forcing link and we are receiving /C/ ordered
698
* sets, re-enable auto-negotiation in the TXCW register
699
* and disable forced link in the Device Control register
700
* in an attempt to auto-negotiate with our link partner.
702
DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
703
E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
704
E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
706
mac->serdes_has_link = true;
707
} else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
709
* If we force link for non-auto-negotiation switch, check
710
* link status based on MAC synchronization for internal
713
/* SYNCH bit and IV bit are sticky. */
715
rxcw = E1000_READ_REG(hw, E1000_RXCW);
716
if (rxcw & E1000_RXCW_SYNCH) {
717
if (!(rxcw & E1000_RXCW_IV)) {
718
mac->serdes_has_link = true;
719
DEBUGOUT("SERDES: Link up - forced.\n");
722
mac->serdes_has_link = false;
723
DEBUGOUT("SERDES: Link down - force failed.\n");
727
if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
728
status = E1000_READ_REG(hw, E1000_STATUS);
729
if (status & E1000_STATUS_LU) {
730
/* SYNCH bit and IV bit are sticky, so reread rxcw. */
732
rxcw = E1000_READ_REG(hw, E1000_RXCW);
733
if (rxcw & E1000_RXCW_SYNCH) {
734
if (!(rxcw & E1000_RXCW_IV)) {
735
mac->serdes_has_link = true;
736
DEBUGOUT("SERDES: Link up - autoneg "
737
"completed sucessfully.\n");
739
mac->serdes_has_link = false;
740
DEBUGOUT("SERDES: Link down - invalid"
741
"codewords detected in autoneg.\n");
744
mac->serdes_has_link = false;
745
DEBUGOUT("SERDES: Link down - no sync.\n");
748
mac->serdes_has_link = false;
749
DEBUGOUT("SERDES: Link down - autoneg failed\n");
758
* igb_setup_link_generic - Setup flow control and link settings
759
* @hw: pointer to the HW structure
761
* Determines which flow control settings to use, then configures flow
762
* control. Calls the appropriate media-specific link configuration
763
* function. Assuming the adapter has a valid link partner, a valid link
764
* should be established. Assumes the hardware has previously been reset
765
* and the transmitter and receiver are not enabled.
767
s32 igb_setup_link_generic(struct e1000_hw *hw)
769
s32 ret_val = E1000_SUCCESS;
771
DEBUGFUNC("igb_setup_link_generic");
774
* In the case of the phy reset being blocked, we already have a link.
775
* We do not need to set it up again.
777
if (hw->phy.ops.check_reset_block)
778
if (hw->phy.ops.check_reset_block(hw))
782
* If requested flow control is set to default, set flow control
783
* based on the EEPROM flow control settings.
785
if (hw->fc.requested_mode == e1000_fc_default) {
786
ret_val = igb_set_default_fc_generic(hw);
792
* Save off the requested flow control mode for use later. Depending
793
* on the link partner's capabilities, we may or may not use this mode.
795
hw->fc.current_mode = hw->fc.requested_mode;
797
DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
798
hw->fc.current_mode);
800
/* Call the necessary media_type subroutine to configure the link. */
801
ret_val = hw->mac.ops.setup_physical_interface(hw);
806
* Initialize the flow control address, type, and PAUSE timer
807
* registers to their default values. This is done even if flow
808
* control is disabled, because it does not hurt anything to
809
* initialize these registers.
811
DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
812
E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
813
E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
814
E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
816
E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
818
ret_val = igb_set_fc_watermarks_generic(hw);
825
* igb_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
826
* @hw: pointer to the HW structure
828
* Configures collision distance and flow control for fiber and serdes
829
* links. Upon successful setup, poll for link.
831
s32 igb_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
834
s32 ret_val = E1000_SUCCESS;
836
DEBUGFUNC("igb_setup_fiber_serdes_link_generic");
838
ctrl = E1000_READ_REG(hw, E1000_CTRL);
840
/* Take the link out of reset */
841
ctrl &= ~E1000_CTRL_LRST;
843
igb_config_collision_dist_generic(hw);
845
ret_val = igb_commit_fc_settings_generic(hw);
850
* Since auto-negotiation is enabled, take the link out of reset (the
851
* link will be in reset, because we previously reset the chip). This
852
* will restart auto-negotiation. If auto-negotiation is successful
853
* then the link-up status bit will be set and the flow control enable
854
* bits (RFCE and TFCE) will be set according to their negotiated value.
856
DEBUGOUT("Auto-negotiation enabled\n");
858
E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
859
E1000_WRITE_FLUSH(hw);
863
* For these adapters, the SW definable pin 1 is set when the optics
864
* detect a signal. If we have a signal, then poll for a "Link-Up"
867
if (hw->phy.media_type == e1000_media_type_internal_serdes ||
868
(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
869
ret_val = igb_poll_fiber_serdes_link_generic(hw);
871
DEBUGOUT("No signal detected\n");
879
* igb_config_collision_dist_generic - Configure collision distance
880
* @hw: pointer to the HW structure
882
* Configures the collision distance to the default value and is used
883
* during link setup. Currently no func pointer exists and all
884
* implementations are handled in the generic version of this function.
886
void igb_config_collision_dist_generic(struct e1000_hw *hw)
890
DEBUGFUNC("igb_config_collision_dist_generic");
892
tctl = E1000_READ_REG(hw, E1000_TCTL);
894
tctl &= ~E1000_TCTL_COLD;
895
tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
897
E1000_WRITE_REG(hw, E1000_TCTL, tctl);
898
E1000_WRITE_FLUSH(hw);
902
* igb_poll_fiber_serdes_link_generic - Poll for link up
903
* @hw: pointer to the HW structure
905
* Polls for link up by reading the status register, if link fails to come
906
* up with auto-negotiation, then the link is forced if a signal is detected.
908
static s32 igb_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
910
struct e1000_mac_info *mac = &hw->mac;
912
s32 ret_val = E1000_SUCCESS;
914
DEBUGFUNC("igb_poll_fiber_serdes_link_generic");
917
* If we have a signal (the cable is plugged in, or assumed true for
918
* serdes media) then poll for a "Link-Up" indication in the Device
919
* Status Register. Time-out if a link isn't seen in 500 milliseconds
920
* seconds (Auto-negotiation should complete in less than 500
921
* milliseconds even if the other end is doing it in SW).
923
for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
925
status = E1000_READ_REG(hw, E1000_STATUS);
926
if (status & E1000_STATUS_LU)
929
if (i == FIBER_LINK_UP_LIMIT) {
930
DEBUGOUT("Never got a valid link from auto-neg!!!\n");
931
mac->autoneg_failed = 1;
933
* AutoNeg failed to achieve a link, so we'll call
934
* mac->check_for_link. This routine will force the
935
* link up if we detect a signal. This will allow us to
936
* communicate with non-autonegotiating link partners.
938
ret_val = hw->mac.ops.check_for_link(hw);
940
DEBUGOUT("Error while checking for link\n");
943
mac->autoneg_failed = 0;
945
mac->autoneg_failed = 0;
946
DEBUGOUT("Valid Link Found\n");
954
* igb_commit_fc_settings_generic - Configure flow control
955
* @hw: pointer to the HW structure
957
* Write the flow control settings to the Transmit Config Word Register (TXCW)
958
* base on the flow control settings in e1000_mac_info.
960
static s32 igb_commit_fc_settings_generic(struct e1000_hw *hw)
962
struct e1000_mac_info *mac = &hw->mac;
964
s32 ret_val = E1000_SUCCESS;
966
DEBUGFUNC("igb_commit_fc_settings_generic");
969
* Check for a software override of the flow control settings, and
970
* setup the device accordingly. If auto-negotiation is enabled, then
971
* software will have to set the "PAUSE" bits to the correct value in
972
* the Transmit Config Word Register (TXCW) and re-start auto-
973
* negotiation. However, if auto-negotiation is disabled, then
974
* software will have to manually configure the two flow control enable
975
* bits in the CTRL register.
977
* The possible values of the "fc" parameter are:
978
* 0: Flow control is completely disabled
979
* 1: Rx flow control is enabled (we can receive pause frames,
980
* but not send pause frames).
981
* 2: Tx flow control is enabled (we can send pause frames but we
982
* do not support receiving pause frames).
983
* 3: Both Rx and Tx flow control (symmetric) are enabled.
985
switch (hw->fc.current_mode) {
987
/* Flow control completely disabled by a software over-ride. */
988
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
990
case e1000_fc_rx_pause:
992
* Rx Flow control is enabled and Tx Flow control is disabled
993
* by a software over-ride. Since there really isn't a way to
994
* advertise that we are capable of Rx Pause ONLY, we will
995
* advertise that we support both symmetric and asymmetric RX
996
* PAUSE. Later, we will disable the adapter's ability to send
999
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1001
case e1000_fc_tx_pause:
1003
* Tx Flow control is enabled, and Rx Flow control is disabled,
1004
* by a software over-ride.
1006
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1010
* Flow control (both Rx and Tx) is enabled by a software
1013
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1016
DEBUGOUT("Flow control param set incorrectly\n");
1017
ret_val = -E1000_ERR_CONFIG;
1022
E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1030
* igb_set_fc_watermarks_generic - Set flow control high/low watermarks
1031
* @hw: pointer to the HW structure
1033
* Sets the flow control high/low threshold (watermark) registers. If
1034
* flow control XON frame transmission is enabled, then set XON frame
1035
* transmission as well.
1037
s32 igb_set_fc_watermarks_generic(struct e1000_hw *hw)
1039
s32 ret_val = E1000_SUCCESS;
1040
u32 fcrtl = 0, fcrth = 0;
1042
DEBUGFUNC("igb_set_fc_watermarks_generic");
1045
* Set the flow control receive threshold registers. Normally,
1046
* these registers will be set to a default threshold that may be
1047
* adjusted later by the driver's runtime code. However, if the
1048
* ability to transmit pause frames is not enabled, then these
1049
* registers will be set to 0.
1051
if (hw->fc.current_mode & e1000_fc_tx_pause) {
1053
* We need to set up the Receive Threshold high and low water
1054
* marks as well as (optionally) enabling the transmission of
1057
fcrtl = hw->fc.low_water;
1058
if (hw->fc.send_xon)
1059
fcrtl |= E1000_FCRTL_XONE;
1061
fcrth = hw->fc.high_water;
1063
E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1064
E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1070
* igb_set_default_fc_generic - Set flow control default values
1071
* @hw: pointer to the HW structure
1073
* Read the EEPROM for the default values for flow control and store the
1076
static s32 igb_set_default_fc_generic(struct e1000_hw *hw)
1078
s32 ret_val = E1000_SUCCESS;
1081
DEBUGFUNC("igb_set_default_fc_generic");
1084
* Read and store word 0x0F of the EEPROM. This word contains bits
1085
* that determine the hardware's default PAUSE (flow control) mode,
1086
* a bit that determines whether the HW defaults to enabling or
1087
* disabling auto-negotiation, and the direction of the
1088
* SW defined pins. If there is no SW over-ride of the flow
1089
* control setting, then the variable hw->fc will
1090
* be initialized based on a value in the EEPROM.
1092
ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
1095
DEBUGOUT("NVM Read Error\n");
1099
if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
1100
hw->fc.requested_mode = e1000_fc_none;
1101
else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
1103
hw->fc.requested_mode = e1000_fc_tx_pause;
1105
hw->fc.requested_mode = e1000_fc_full;
1112
* igb_force_mac_fc_generic - Force the MAC's flow control settings
1113
* @hw: pointer to the HW structure
1115
* Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1116
* device control register to reflect the adapter settings. TFCE and RFCE
1117
* need to be explicitly set by software when a copper PHY is used because
1118
* autonegotiation is managed by the PHY rather than the MAC. Software must
1119
* also configure these bits when link is forced on a fiber connection.
1121
s32 igb_force_mac_fc_generic(struct e1000_hw *hw)
1124
s32 ret_val = E1000_SUCCESS;
1126
DEBUGFUNC("igb_force_mac_fc_generic");
1128
ctrl = E1000_READ_REG(hw, E1000_CTRL);
1131
* Because we didn't get link via the internal auto-negotiation
1132
* mechanism (we either forced link or we got link via PHY
1133
* auto-neg), we have to manually enable/disable transmit an
1134
* receive flow control.
1136
* The "Case" statement below enables/disable flow control
1137
* according to the "hw->fc.current_mode" parameter.
1139
* The possible values of the "fc" parameter are:
1140
* 0: Flow control is completely disabled
1141
* 1: Rx flow control is enabled (we can receive pause
1142
* frames but not send pause frames).
1143
* 2: Tx flow control is enabled (we can send pause frames
1144
* frames but we do not receive pause frames).
1145
* 3: Both Rx and Tx flow control (symmetric) is enabled.
1146
* other: No other values should be possible at this point.
1148
DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1150
switch (hw->fc.current_mode) {
1152
ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1154
case e1000_fc_rx_pause:
1155
ctrl &= (~E1000_CTRL_TFCE);
1156
ctrl |= E1000_CTRL_RFCE;
1158
case e1000_fc_tx_pause:
1159
ctrl &= (~E1000_CTRL_RFCE);
1160
ctrl |= E1000_CTRL_TFCE;
1163
ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1166
DEBUGOUT("Flow control param set incorrectly\n");
1167
ret_val = -E1000_ERR_CONFIG;
1171
E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1178
* igb_config_fc_after_link_up_generic - Configures flow control after link
1179
* @hw: pointer to the HW structure
1181
* Checks the status of auto-negotiation after link up to ensure that the
1182
* speed and duplex were not forced. If the link needed to be forced, then
1183
* flow control needs to be forced also. If auto-negotiation is enabled
1184
* and did not fail, then we configure flow control based on our link
1187
s32 igb_config_fc_after_link_up_generic(struct e1000_hw *hw)
1189
struct e1000_mac_info *mac = &hw->mac;
1190
s32 ret_val = E1000_SUCCESS;
1191
u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1194
DEBUGFUNC("igb_config_fc_after_link_up_generic");
1197
* Check for the case where we have fiber media and auto-neg failed
1198
* so we had to force link. In this case, we need to force the
1199
* configuration of the MAC to match the "fc" parameter.
1201
if (mac->autoneg_failed) {
1202
if (hw->phy.media_type == e1000_media_type_fiber ||
1203
hw->phy.media_type == e1000_media_type_internal_serdes)
1204
ret_val = igb_force_mac_fc_generic(hw);
1206
if (hw->phy.media_type == e1000_media_type_copper)
1207
ret_val = igb_force_mac_fc_generic(hw);
1211
DEBUGOUT("Error forcing flow control settings\n");
1216
* Check for the case where we have copper media and auto-neg is
1217
* enabled. In this case, we need to check and see if Auto-Neg
1218
* has completed, and if so, how the PHY and link partner has
1219
* flow control configured.
1221
if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1223
* Read the MII Status Register and check to see if AutoNeg
1224
* has completed. We read this twice because this reg has
1225
* some "sticky" (latched) bits.
1227
ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1230
ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1234
if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1235
DEBUGOUT("Copper PHY and Auto Neg "
1236
"has not completed.\n");
1241
* The AutoNeg process has completed, so we now need to
1242
* read both the Auto Negotiation Advertisement
1243
* Register (Address 4) and the Auto_Negotiation Base
1244
* Page Ability Register (Address 5) to determine how
1245
* flow control was negotiated.
1247
ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1251
ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1252
&mii_nway_lp_ability_reg);
1257
* Two bits in the Auto Negotiation Advertisement Register
1258
* (Address 4) and two bits in the Auto Negotiation Base
1259
* Page Ability Register (Address 5) determine flow control
1260
* for both the PHY and the link partner. The following
1261
* table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1262
* 1999, describes these PAUSE resolution bits and how flow
1263
* control is determined based upon these settings.
1264
* NOTE: DC = Don't Care
1266
* LOCAL DEVICE | LINK PARTNER
1267
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1268
*-------|---------|-------|---------|--------------------
1269
* 0 | 0 | DC | DC | e1000_fc_none
1270
* 0 | 1 | 0 | DC | e1000_fc_none
1271
* 0 | 1 | 1 | 0 | e1000_fc_none
1272
* 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1273
* 1 | 0 | 0 | DC | e1000_fc_none
1274
* 1 | DC | 1 | DC | e1000_fc_full
1275
* 1 | 1 | 0 | 0 | e1000_fc_none
1276
* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1278
* Are both PAUSE bits set to 1? If so, this implies
1279
* Symmetric Flow Control is enabled at both ends. The
1280
* ASM_DIR bits are irrelevant per the spec.
1282
* For Symmetric Flow Control:
1284
* LOCAL DEVICE | LINK PARTNER
1285
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1286
*-------|---------|-------|---------|--------------------
1287
* 1 | DC | 1 | DC | E1000_fc_full
1290
if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1291
(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1293
* Now we need to check if the user selected Rx ONLY
1294
* of pause frames. In this case, we had to advertise
1295
* FULL flow control because we could not advertise RX
1296
* ONLY. Hence, we must now check to see if we need to
1297
* turn OFF the TRANSMISSION of PAUSE frames.
1299
if (hw->fc.requested_mode == e1000_fc_full) {
1300
hw->fc.current_mode = e1000_fc_full;
1301
DEBUGOUT("Flow Control = FULL.\r\n");
1303
hw->fc.current_mode = e1000_fc_rx_pause;
1304
DEBUGOUT("Flow Control = "
1305
"RX PAUSE frames only.\r\n");
1309
* For receiving PAUSE frames ONLY.
1311
* LOCAL DEVICE | LINK PARTNER
1312
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1313
*-------|---------|-------|---------|--------------------
1314
* 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1316
else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1317
(mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1318
(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1319
(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1320
hw->fc.current_mode = e1000_fc_tx_pause;
1321
DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
1324
* For transmitting PAUSE frames ONLY.
1326
* LOCAL DEVICE | LINK PARTNER
1327
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1328
*-------|---------|-------|---------|--------------------
1329
* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1331
else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1332
(mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1333
!(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1334
(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1335
hw->fc.current_mode = e1000_fc_rx_pause;
1336
DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1339
* Per the IEEE spec, at this point flow control
1340
* should be disabled.
1342
hw->fc.current_mode = e1000_fc_none;
1343
DEBUGOUT("Flow Control = NONE.\r\n");
1347
* Now we need to do one last check... If we auto-
1348
* negotiated to HALF DUPLEX, flow control should not be
1349
* enabled per IEEE 802.3 spec.
1351
ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1353
DEBUGOUT("Error getting link speed and duplex\n");
1357
if (duplex == HALF_DUPLEX)
1358
hw->fc.current_mode = e1000_fc_none;
1361
* Now we call a subroutine to actually force the MAC
1362
* controller to use the correct flow control settings.
1364
ret_val = igb_force_mac_fc_generic(hw);
1366
DEBUGOUT("Error forcing flow control settings\n");
1376
* igb_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1377
* @hw: pointer to the HW structure
1378
* @speed: stores the current speed
1379
* @duplex: stores the current duplex
1381
* Read the status register for the current speed/duplex and store the current
1382
* speed and duplex for copper connections.
1384
s32 igb_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1389
DEBUGFUNC("igb_get_speed_and_duplex_copper_generic");
1391
status = E1000_READ_REG(hw, E1000_STATUS);
1392
if (status & E1000_STATUS_SPEED_1000) {
1393
*speed = SPEED_1000;
1394
DEBUGOUT("1000 Mbs, ");
1395
} else if (status & E1000_STATUS_SPEED_100) {
1397
DEBUGOUT("100 Mbs, ");
1400
DEBUGOUT("10 Mbs, ");
1403
if (status & E1000_STATUS_FD) {
1404
*duplex = FULL_DUPLEX;
1405
DEBUGOUT("Full Duplex\n");
1407
*duplex = HALF_DUPLEX;
1408
DEBUGOUT("Half Duplex\n");
1411
return E1000_SUCCESS;
1415
* igb_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1416
* @hw: pointer to the HW structure
1417
* @speed: stores the current speed
1418
* @duplex: stores the current duplex
1420
* Sets the speed and duplex to gigabit full duplex (the only possible option)
1421
* for fiber/serdes links.
1423
s32 igb_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw __unused,
1424
u16 *speed, u16 *duplex)
1426
DEBUGFUNC("igb_get_speed_and_duplex_fiber_serdes_generic");
1428
*speed = SPEED_1000;
1429
*duplex = FULL_DUPLEX;
1431
return E1000_SUCCESS;
1435
* igb_get_hw_semaphore_generic - Acquire hardware semaphore
1436
* @hw: pointer to the HW structure
1438
* Acquire the HW semaphore to access the PHY or NVM
1440
s32 igb_get_hw_semaphore_generic(struct e1000_hw *hw)
1443
s32 ret_val = E1000_SUCCESS;
1444
s32 timeout = hw->nvm.word_size + 1;
1447
DEBUGFUNC("igb_get_hw_semaphore_generic");
1449
/* Get the SW semaphore */
1450
while (i < timeout) {
1451
swsm = E1000_READ_REG(hw, E1000_SWSM);
1452
if (!(swsm & E1000_SWSM_SMBI))
1460
DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1461
ret_val = -E1000_ERR_NVM;
1465
/* Get the FW semaphore. */
1466
for (i = 0; i < timeout; i++) {
1467
swsm = E1000_READ_REG(hw, E1000_SWSM);
1468
E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1470
/* Semaphore acquired if bit latched */
1471
if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1478
/* Release semaphores */
1479
igb_put_hw_semaphore_generic(hw);
1480
DEBUGOUT("Driver can't access the NVM\n");
1481
ret_val = -E1000_ERR_NVM;
1490
* igb_put_hw_semaphore_generic - Release hardware semaphore
1491
* @hw: pointer to the HW structure
1493
* Release hardware semaphore used to access the PHY or NVM
1495
void igb_put_hw_semaphore_generic(struct e1000_hw *hw)
1499
DEBUGFUNC("igb_put_hw_semaphore_generic");
1501
swsm = E1000_READ_REG(hw, E1000_SWSM);
1503
swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1505
E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1509
* igb_get_auto_rd_done_generic - Check for auto read completion
1510
* @hw: pointer to the HW structure
1512
* Check EEPROM for Auto Read done bit.
1514
s32 igb_get_auto_rd_done_generic(struct e1000_hw *hw)
1517
s32 ret_val = E1000_SUCCESS;
1519
DEBUGFUNC("igb_get_auto_rd_done_generic");
1521
while (i < AUTO_READ_DONE_TIMEOUT) {
1522
if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1528
if (i == AUTO_READ_DONE_TIMEOUT) {
1529
DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1530
ret_val = -E1000_ERR_RESET;
1539
* igb_valid_led_default_generic - Verify a valid default LED config
1540
* @hw: pointer to the HW structure
1541
* @data: pointer to the NVM (EEPROM)
1543
* Read the EEPROM for the current default LED configuration. If the
1544
* LED configuration is not valid, set to a valid LED configuration.
1546
s32 igb_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1550
DEBUGFUNC("igb_valid_led_default_generic");
1552
ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1554
DEBUGOUT("NVM Read Error\n");
1558
if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1559
*data = ID_LED_DEFAULT;
1566
* e1000_id_led_init_generic -
1567
* @hw: pointer to the HW structure
1570
s32 igb_id_led_init_generic(struct e1000_hw *hw)
1572
struct e1000_mac_info *mac = &hw->mac;
1574
const u32 ledctl_mask = 0x000000FF;
1575
const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1576
const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1578
const u16 led_mask = 0x0F;
1580
DEBUGFUNC("igb_id_led_init_generic");
1582
ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1586
mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1587
mac->ledctl_mode1 = mac->ledctl_default;
1588
mac->ledctl_mode2 = mac->ledctl_default;
1590
for (i = 0; i < 4; i++) {
1591
temp = (data >> (i << 2)) & led_mask;
1593
case ID_LED_ON1_DEF2:
1594
case ID_LED_ON1_ON2:
1595
case ID_LED_ON1_OFF2:
1596
mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1597
mac->ledctl_mode1 |= ledctl_on << (i << 3);
1599
case ID_LED_OFF1_DEF2:
1600
case ID_LED_OFF1_ON2:
1601
case ID_LED_OFF1_OFF2:
1602
mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1603
mac->ledctl_mode1 |= ledctl_off << (i << 3);
1610
case ID_LED_DEF1_ON2:
1611
case ID_LED_ON1_ON2:
1612
case ID_LED_OFF1_ON2:
1613
mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1614
mac->ledctl_mode2 |= ledctl_on << (i << 3);
1616
case ID_LED_DEF1_OFF2:
1617
case ID_LED_ON1_OFF2:
1618
case ID_LED_OFF1_OFF2:
1619
mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1620
mac->ledctl_mode2 |= ledctl_off << (i << 3);
1634
* igb_setup_led_generic - Configures SW controllable LED
1635
* @hw: pointer to the HW structure
1637
* This prepares the SW controllable LED for use and saves the current state
1638
* of the LED so it can be later restored.
1640
s32 igb_setup_led_generic(struct e1000_hw *hw)
1643
s32 ret_val = E1000_SUCCESS;
1645
DEBUGFUNC("igb_setup_led_generic");
1647
if (hw->mac.ops.setup_led != e1000_setup_led_generic) {
1648
ret_val = -E1000_ERR_CONFIG;
1652
if (hw->phy.media_type == e1000_media_type_fiber) {
1653
ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1654
hw->mac.ledctl_default = ledctl;
1656
ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1657
E1000_LEDCTL_LED0_BLINK |
1658
E1000_LEDCTL_LED0_MODE_MASK);
1659
ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1660
E1000_LEDCTL_LED0_MODE_SHIFT);
1661
E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1662
} else if (hw->phy.media_type == e1000_media_type_copper) {
1663
E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1671
* igb_cleanup_led_generic - Set LED config to default operation
1672
* @hw: pointer to the HW structure
1674
* Remove the current LED configuration and set the LED configuration
1675
* to the default value, saved from the EEPROM.
1677
s32 igb_cleanup_led_generic(struct e1000_hw *hw)
1679
s32 ret_val = E1000_SUCCESS;
1681
DEBUGFUNC("igb_cleanup_led_generic");
1683
if (hw->mac.ops.cleanup_led != e1000_cleanup_led_generic) {
1684
ret_val = -E1000_ERR_CONFIG;
1688
E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1695
* igb_blink_led_generic - Blink LED
1696
* @hw: pointer to the HW structure
1698
* Blink the LEDs which are set to be on.
1700
s32 igb_blink_led_generic(struct e1000_hw *hw)
1702
u32 ledctl_blink = 0;
1705
DEBUGFUNC("igb_blink_led_generic");
1707
if (hw->phy.media_type == e1000_media_type_fiber) {
1708
/* always blink LED0 for PCI-E fiber */
1709
ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1710
(E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1713
* set the blink bit for each LED that's "on" (0x0E)
1716
ledctl_blink = hw->mac.ledctl_mode2;
1717
for (i = 0; i < 4; i++)
1718
if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1719
E1000_LEDCTL_MODE_LED_ON)
1720
ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1724
E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1726
return E1000_SUCCESS;
1730
* igb_led_on_generic - Turn LED on
1731
* @hw: pointer to the HW structure
1735
s32 igb_led_on_generic(struct e1000_hw *hw)
1739
DEBUGFUNC("igb_led_on_generic");
1741
switch (hw->phy.media_type) {
1742
case e1000_media_type_fiber:
1743
ctrl = E1000_READ_REG(hw, E1000_CTRL);
1744
ctrl &= ~E1000_CTRL_SWDPIN0;
1745
ctrl |= E1000_CTRL_SWDPIO0;
1746
E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1748
case e1000_media_type_copper:
1749
E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
1755
return E1000_SUCCESS;
1759
* igb_led_off_generic - Turn LED off
1760
* @hw: pointer to the HW structure
1764
s32 igb_led_off_generic(struct e1000_hw *hw)
1768
DEBUGFUNC("igb_led_off_generic");
1770
switch (hw->phy.media_type) {
1771
case e1000_media_type_fiber:
1772
ctrl = E1000_READ_REG(hw, E1000_CTRL);
1773
ctrl |= E1000_CTRL_SWDPIN0;
1774
ctrl |= E1000_CTRL_SWDPIO0;
1775
E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1777
case e1000_media_type_copper:
1778
E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1784
return E1000_SUCCESS;
1789
* igb_set_pcie_no_snoop_generic - Set PCI-express capabilities
1790
* @hw: pointer to the HW structure
1791
* @no_snoop: bitmap of snoop events
1793
* Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1795
void igb_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
1799
DEBUGFUNC("igb_set_pcie_no_snoop_generic");
1801
if (hw->bus.type != e1000_bus_type_pci_express)
1805
gcr = E1000_READ_REG(hw, E1000_GCR);
1806
gcr &= ~(PCIE_NO_SNOOP_ALL);
1808
E1000_WRITE_REG(hw, E1000_GCR, gcr);
1815
* igb_disable_pcie_master_generic - Disables PCI-express master access
1816
* @hw: pointer to the HW structure
1818
* Returns 0 (E1000_SUCCESS) if successful, else returns -10
1819
* (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1820
* the master requests to be disabled.
1822
* Disables PCI-Express master access and verifies there are no pending
1825
s32 igb_disable_pcie_master_generic(struct e1000_hw *hw)
1828
s32 timeout = MASTER_DISABLE_TIMEOUT;
1829
s32 ret_val = E1000_SUCCESS;
1831
DEBUGFUNC("igb_disable_pcie_master_generic");
1833
if (hw->bus.type != e1000_bus_type_pci_express)
1836
ctrl = E1000_READ_REG(hw, E1000_CTRL);
1837
ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1838
E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1841
if (!(E1000_READ_REG(hw, E1000_STATUS) &
1842
E1000_STATUS_GIO_MASTER_ENABLE))
1849
DEBUGOUT("Master requests are pending.\n");
1850
ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
1859
* igb_reset_adaptive_generic - Reset Adaptive Interframe Spacing
1860
* @hw: pointer to the HW structure
1862
* Reset the Adaptive Interframe Spacing throttle to default values.
1864
void igb_reset_adaptive_generic(struct e1000_hw *hw)
1866
struct e1000_mac_info *mac = &hw->mac;
1868
DEBUGFUNC("igb_reset_adaptive_generic");
1870
if (!mac->adaptive_ifs) {
1871
DEBUGOUT("Not in Adaptive IFS mode!\n");
1875
mac->current_ifs_val = 0;
1876
mac->ifs_min_val = IFS_MIN;
1877
mac->ifs_max_val = IFS_MAX;
1878
mac->ifs_step_size = IFS_STEP;
1879
mac->ifs_ratio = IFS_RATIO;
1881
mac->in_ifs_mode = false;
1882
E1000_WRITE_REG(hw, E1000_AIT, 0);
1888
* igb_update_adaptive_generic - Update Adaptive Interframe Spacing
1889
* @hw: pointer to the HW structure
1891
* Update the Adaptive Interframe Spacing Throttle value based on the
1892
* time between transmitted packets and time between collisions.
1894
void igb_update_adaptive_generic(struct e1000_hw *hw)
1896
struct e1000_mac_info *mac = &hw->mac;
1898
DEBUGFUNC("igb_update_adaptive_generic");
1900
if (!mac->adaptive_ifs) {
1901
DEBUGOUT("Not in Adaptive IFS mode!\n");
1905
if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
1906
if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1907
mac->in_ifs_mode = true;
1908
if (mac->current_ifs_val < mac->ifs_max_val) {
1909
if (!mac->current_ifs_val)
1910
mac->current_ifs_val = mac->ifs_min_val;
1912
mac->current_ifs_val +=
1914
E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val);
1918
if (mac->in_ifs_mode &&
1919
(mac->tx_packet_delta <= MIN_NUM_XMITS)) {
1920
mac->current_ifs_val = 0;
1921
mac->in_ifs_mode = false;
1922
E1000_WRITE_REG(hw, E1000_AIT, 0);
1930
* igb_validate_mdi_setting_generic - Verify MDI/MDIx settings
1931
* @hw: pointer to the HW structure
1933
* Verify that when not using auto-negotiation that MDI/MDIx is correctly
1934
* set, which is forced to MDI mode only.
1936
static s32 igb_validate_mdi_setting_generic(struct e1000_hw *hw)
1938
s32 ret_val = E1000_SUCCESS;
1940
DEBUGFUNC("igb_validate_mdi_setting_generic");
1942
if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
1943
DEBUGOUT("Invalid MDI setting detected\n");
1945
ret_val = -E1000_ERR_CONFIG;
1954
* igb_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
1955
* @hw: pointer to the HW structure
1956
* @reg: 32bit register offset such as E1000_SCTL
1957
* @offset: register offset to write to
1958
* @data: data to write at register offset
1960
* Writes an address/data control type register. There are several of these
1961
* and they all have the format address << 8 | data and bit 31 is polled for
1964
s32 igb_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
1965
u32 offset, u8 data)
1967
u32 i, regvalue = 0;
1968
s32 ret_val = E1000_SUCCESS;
1970
DEBUGFUNC("igb_write_8bit_ctrl_reg_generic");
1972
/* Set up the address and data */
1973
regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
1974
E1000_WRITE_REG(hw, reg, regvalue);
1976
/* Poll the ready bit to see if the MDI read completed */
1977
for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
1979
regvalue = E1000_READ_REG(hw, reg);
1980
if (regvalue & E1000_GEN_CTL_READY)
1983
if (!(regvalue & E1000_GEN_CTL_READY)) {
1984
DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
1985
ret_val = -E1000_ERR_PHY;
added
removed
src/drivers/net/igb/igb_mac.c
