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/*******************************************************************************
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Intel PRO/1000 Linux driver
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Copyright(c) 1999 - 2009 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Linux NICS <linux.nics@intel.com>
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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FILE_LICENCE ( GPL2_OR_LATER );
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static void e1000e_stop_nvm(struct e1000_hw *hw);
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static void e1000e_reload_nvm(struct e1000_hw *hw);
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* e1000e_init_nvm_ops_generic - Initialize NVM function pointers
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* @hw: pointer to the HW structure
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* Setups up the function pointers to no-op functions
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void e1000e_init_nvm_ops_generic(struct e1000_hw *hw)
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struct e1000_nvm_info *nvm = &hw->nvm;
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/* Initialize function pointers */
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nvm->ops.reload = e1000e_reload_nvm;
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* e1000e_raise_eec_clk - Raise EEPROM clock
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* @hw: pointer to the HW structure
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* @eecd: pointer to the EEPROM
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* Enable/Raise the EEPROM clock bit.
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static void e1000e_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
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*eecd = *eecd | E1000_EECD_SK;
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udelay(hw->nvm.delay_usec);
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* e1000e_lower_eec_clk - Lower EEPROM clock
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* @hw: pointer to the HW structure
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* @eecd: pointer to the EEPROM
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* Clear/Lower the EEPROM clock bit.
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static void e1000e_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
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*eecd = *eecd & ~E1000_EECD_SK;
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udelay(hw->nvm.delay_usec);
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* e1000e_shift_out_eec_bits - Shift data bits our to the EEPROM
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* @hw: pointer to the HW structure
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* @data: data to send to the EEPROM
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* @count: number of bits to shift out
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* We need to shift 'count' bits out to the EEPROM. So, the value in the
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* "data" parameter will be shifted out to the EEPROM one bit at a time.
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* In order to do this, "data" must be broken down into bits.
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static void e1000e_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
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struct e1000_nvm_info *nvm = &hw->nvm;
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u32 eecd = er32(EECD);
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mask = 0x01 << (count - 1);
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if (nvm->type == e1000_nvm_eeprom_spi)
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eecd |= E1000_EECD_DO;
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eecd &= ~E1000_EECD_DI;
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eecd |= E1000_EECD_DI;
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udelay(nvm->delay_usec);
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e1000e_raise_eec_clk(hw, &eecd);
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e1000e_lower_eec_clk(hw, &eecd);
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eecd &= ~E1000_EECD_DI;
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* e1000e_shift_in_eec_bits - Shift data bits in from the EEPROM
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* @hw: pointer to the HW structure
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* @count: number of bits to shift in
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* In order to read a register from the EEPROM, we need to shift 'count' bits
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* in from the EEPROM. Bits are "shifted in" by raising the clock input to
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* the EEPROM (setting the SK bit), and then reading the value of the data out
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* "DO" bit. During this "shifting in" process the data in "DI" bit should
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static u16 e1000e_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
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eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
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for (i = 0; i < count; i++) {
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e1000e_raise_eec_clk(hw, &eecd);
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eecd &= ~E1000_EECD_DI;
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if (eecd & E1000_EECD_DO)
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e1000e_lower_eec_clk(hw, &eecd);
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* e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
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* @hw: pointer to the HW structure
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* @ee_reg: EEPROM flag for polling
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* Polls the EEPROM status bit for either read or write completion based
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* upon the value of 'ee_reg'.
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s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
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u32 attempts = 100000;
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s32 ret_val = -E1000_ERR_NVM;
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for (i = 0; i < attempts; i++) {
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if (ee_reg == E1000_NVM_POLL_READ)
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if (reg & E1000_NVM_RW_REG_DONE) {
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ret_val = E1000_SUCCESS;
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* e1000e_acquire_nvm - Generic request for access to EEPROM
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* @hw: pointer to the HW structure
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* Set the EEPROM access request bit and wait for EEPROM access grant bit.
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* Return successful if access grant bit set, else clear the request for
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* EEPROM access and return -E1000_ERR_NVM (-1).
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s32 e1000e_acquire_nvm(struct e1000_hw *hw)
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u32 eecd = er32(EECD);
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s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
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s32 ret_val = E1000_SUCCESS;
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ew32(EECD, eecd | E1000_EECD_REQ);
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if (eecd & E1000_EECD_GNT)
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eecd &= ~E1000_EECD_REQ;
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e_dbg("Could not acquire NVM grant\n");
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ret_val = -E1000_ERR_NVM;
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* e1000e_standby_nvm - Return EEPROM to standby state
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* @hw: pointer to the HW structure
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* Return the EEPROM to a standby state.
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static void e1000e_standby_nvm(struct e1000_hw *hw)
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struct e1000_nvm_info *nvm = &hw->nvm;
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u32 eecd = er32(EECD);
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if (nvm->type == e1000_nvm_eeprom_spi) {
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/* Toggle CS to flush commands */
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eecd |= E1000_EECD_CS;
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udelay(nvm->delay_usec);
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eecd &= ~E1000_EECD_CS;
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udelay(nvm->delay_usec);
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* e1000e_stop_nvm - Terminate EEPROM command
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* @hw: pointer to the HW structure
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* Terminates the current command by inverting the EEPROM's chip select pin.
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static void e1000e_stop_nvm(struct e1000_hw *hw)
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if (hw->nvm.type == e1000_nvm_eeprom_spi) {
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eecd |= E1000_EECD_CS;
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e1000e_lower_eec_clk(hw, &eecd);
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* e1000e_release_nvm - Release exclusive access to EEPROM
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* @hw: pointer to the HW structure
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* Stop any current commands to the EEPROM and clear the EEPROM request bit.
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void e1000e_release_nvm(struct e1000_hw *hw)
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eecd &= ~E1000_EECD_REQ;
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* e1000e_ready_nvm_eeprom - Prepares EEPROM for read/write
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* @hw: pointer to the HW structure
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* Setups the EEPROM for reading and writing.
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static s32 e1000e_ready_nvm_eeprom(struct e1000_hw *hw)
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struct e1000_nvm_info *nvm = &hw->nvm;
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u32 eecd = er32(EECD);
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s32 ret_val = E1000_SUCCESS;
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if (nvm->type == e1000_nvm_eeprom_spi) {
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/* Clear SK and CS */
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eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
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timeout = NVM_MAX_RETRY_SPI;
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* Read "Status Register" repeatedly until the LSB is cleared.
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* The EEPROM will signal that the command has been completed
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* by clearing bit 0 of the internal status register. If it's
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* not cleared within 'timeout', then error out.
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e1000e_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
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hw->nvm.opcode_bits);
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spi_stat_reg = (u8)e1000e_shift_in_eec_bits(hw, 8);
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if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
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e1000e_standby_nvm(hw);
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e_dbg("SPI NVM Status error\n");
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ret_val = -E1000_ERR_NVM;
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* e1000e_read_nvm_eerd - Reads EEPROM using EERD register
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* @hw: pointer to the HW structure
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* @offset: offset of word in the EEPROM to read
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* @words: number of words to read
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* @data: word read from the EEPROM
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* Reads a 16 bit word from the EEPROM using the EERD register.
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s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
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struct e1000_nvm_info *nvm = &hw->nvm;
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s32 ret_val = E1000_SUCCESS;
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* A check for invalid values: offset too large, too many words,
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* too many words for the offset, and not enough words.
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if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
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e_dbg("nvm parameter(s) out of bounds\n");
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ret_val = -E1000_ERR_NVM;
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for (i = 0; i < words; i++) {
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eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
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E1000_NVM_RW_REG_START;
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ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
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data[i] = (er32(EERD) >>
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E1000_NVM_RW_REG_DATA);
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* e1000e_write_nvm_spi - Write to EEPROM using SPI
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* @hw: pointer to the HW structure
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* @offset: offset within the EEPROM to be written to
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* @words: number of words to write
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* @data: 16 bit word(s) to be written to the EEPROM
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* Writes data to EEPROM at offset using SPI interface.
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* If e1000e_update_nvm_checksum is not called after this function , the
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* EEPROM will most likely contain an invalid checksum.
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s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
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struct e1000_nvm_info *nvm = &hw->nvm;
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* A check for invalid values: offset too large, too many words,
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* and not enough words.
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if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
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e_dbg("nvm parameter(s) out of bounds\n");
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ret_val = -E1000_ERR_NVM;
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ret_val = nvm->ops.acquire(hw);
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while (widx < words) {
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u8 write_opcode = NVM_WRITE_OPCODE_SPI;
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ret_val = e1000e_ready_nvm_eeprom(hw);
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e1000e_standby_nvm(hw);
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/* Send the WRITE ENABLE command (8 bit opcode) */
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e1000e_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
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e1000e_standby_nvm(hw);
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* Some SPI eeproms use the 8th address bit embedded in the
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if ((nvm->address_bits == 8) && (offset >= 128))
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write_opcode |= NVM_A8_OPCODE_SPI;
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/* Send the Write command (8-bit opcode + addr) */
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e1000e_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
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e1000e_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
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/* Loop to allow for up to whole page write of eeprom */
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while (widx < words) {
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u16 word_out = data[widx];
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word_out = (word_out >> 8) | (word_out << 8);
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e1000e_shift_out_eec_bits(hw, word_out, 16);
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if ((((offset + widx) * 2) % nvm->page_size) == 0) {
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e1000e_standby_nvm(hw);
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nvm->ops.release(hw);
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* e1000e_read_pba_num - Read device part number
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* @hw: pointer to the HW structure
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* @pba_num: pointer to device part number
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* Reads the product board assembly (PBA) number from the EEPROM and stores
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* the value in pba_num.
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s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num)
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ret_val = e1000e_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
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e_dbg("NVM Read Error\n");
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*pba_num = (u32)(nvm_data << 16);
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ret_val = e1000e_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
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e_dbg("NVM Read Error\n");
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*pba_num |= nvm_data;
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* e1000e_read_mac_addr_generic - Read device MAC address
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* @hw: pointer to the HW structure
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* Reads the device MAC address from the EEPROM and stores the value.
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* Since devices with two ports use the same EEPROM, we increment the
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* last bit in the MAC address for the second port.
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s32 e1000e_read_mac_addr_generic(struct e1000_hw *hw)
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rar_high = er32(RAH(0));
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rar_low = er32(RAL(0));
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for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
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hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
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for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
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hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
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for (i = 0; i < ETH_ADDR_LEN; i++)
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hw->mac.addr[i] = hw->mac.perm_addr[i];
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return E1000_SUCCESS;
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* e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
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* @hw: pointer to the HW structure
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* Calculates the EEPROM checksum by reading/adding each word of the EEPROM
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* and then verifies that the sum of the EEPROM is equal to 0xBABA.
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s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
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s32 ret_val = E1000_SUCCESS;
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for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
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ret_val = e1000e_read_nvm(hw, i, 1, &nvm_data);
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e_dbg("NVM Read Error\n");
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checksum += nvm_data;
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if (checksum != (u16) NVM_SUM) {
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e_dbg("NVM Checksum Invalid\n");
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ret_val = -E1000_ERR_NVM;
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* e1000e_update_nvm_checksum_generic - Update EEPROM checksum
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* @hw: pointer to the HW structure
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* Updates the EEPROM checksum by reading/adding each word of the EEPROM
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* up to the checksum. Then calculates the EEPROM checksum and writes the
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* value to the EEPROM.
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s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
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for (i = 0; i < NVM_CHECKSUM_REG; i++) {
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ret_val = e1000e_read_nvm(hw, i, 1, &nvm_data);
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e_dbg("NVM Read Error while updating checksum.\n");
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checksum += nvm_data;
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checksum = (u16) NVM_SUM - checksum;
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ret_val = e1000e_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
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e_dbg("NVM Write Error while updating checksum.\n");
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* e1000e_reload_nvm - Reloads EEPROM
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* @hw: pointer to the HW structure
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* Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
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* extended control register.
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static void e1000e_reload_nvm(struct e1000_hw *hw)
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ctrl_ext = er32(CTRL_EXT);
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ctrl_ext |= E1000_CTRL_EXT_EE_RST;
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ew32(CTRL_EXT, ctrl_ext);
added
removed
src/drivers/net/e1000e/e1000e_nvm.c
