2
* Copyright © 2008,2010 Intel Corporation
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24
* Eric Anholt <eric@anholt.net>
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* Chris Wilson <chris@chris-wilson.co.uk>
33
#include "i915_trace.h"
34
#include "intel_drv.h"
35
#include <linux/dma_remapping.h>
39
struct hlist_head buckets[0];
42
static struct eb_objects *
45
struct eb_objects *eb;
46
int count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
47
BUILD_BUG_ON(!is_power_of_2(PAGE_SIZE / sizeof(struct hlist_head)));
50
eb = kzalloc(count*sizeof(struct hlist_head) +
51
sizeof(struct eb_objects),
61
eb_reset(struct eb_objects *eb)
63
memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
67
eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj)
69
hlist_add_head(&obj->exec_node,
70
&eb->buckets[obj->exec_handle & eb->and]);
73
static struct drm_i915_gem_object *
74
eb_get_object(struct eb_objects *eb, unsigned long handle)
76
struct hlist_head *head;
77
struct hlist_node *node;
78
struct drm_i915_gem_object *obj;
80
head = &eb->buckets[handle & eb->and];
81
hlist_for_each(node, head) {
82
obj = hlist_entry(node, struct drm_i915_gem_object, exec_node);
83
if (obj->exec_handle == handle)
91
eb_destroy(struct eb_objects *eb)
96
static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
98
return (obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
99
!obj->map_and_fenceable ||
100
obj->cache_level != I915_CACHE_NONE);
104
i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
105
struct eb_objects *eb,
106
struct drm_i915_gem_relocation_entry *reloc)
108
struct drm_device *dev = obj->base.dev;
109
struct drm_gem_object *target_obj;
110
struct drm_i915_gem_object *target_i915_obj;
111
uint32_t target_offset;
114
/* we've already hold a reference to all valid objects */
115
target_obj = &eb_get_object(eb, reloc->target_handle)->base;
116
if (unlikely(target_obj == NULL))
119
target_i915_obj = to_intel_bo(target_obj);
120
target_offset = target_i915_obj->gtt_offset;
122
/* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
123
* pipe_control writes because the gpu doesn't properly redirect them
124
* through the ppgtt for non_secure batchbuffers. */
125
if (unlikely(IS_GEN6(dev) &&
126
reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
127
!target_i915_obj->has_global_gtt_mapping)) {
128
i915_gem_gtt_bind_object(target_i915_obj,
129
target_i915_obj->cache_level);
132
/* Validate that the target is in a valid r/w GPU domain */
133
if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
134
DRM_DEBUG("reloc with multiple write domains: "
135
"obj %p target %d offset %d "
136
"read %08x write %08x",
137
obj, reloc->target_handle,
140
reloc->write_domain);
143
if (unlikely((reloc->write_domain | reloc->read_domains)
144
& ~I915_GEM_GPU_DOMAINS)) {
145
DRM_DEBUG("reloc with read/write non-GPU domains: "
146
"obj %p target %d offset %d "
147
"read %08x write %08x",
148
obj, reloc->target_handle,
151
reloc->write_domain);
154
if (unlikely(reloc->write_domain && target_obj->pending_write_domain &&
155
reloc->write_domain != target_obj->pending_write_domain)) {
156
DRM_DEBUG("Write domain conflict: "
157
"obj %p target %d offset %d "
158
"new %08x old %08x\n",
159
obj, reloc->target_handle,
162
target_obj->pending_write_domain);
166
target_obj->pending_read_domains |= reloc->read_domains;
167
target_obj->pending_write_domain |= reloc->write_domain;
169
/* If the relocation already has the right value in it, no
170
* more work needs to be done.
172
if (target_offset == reloc->presumed_offset)
175
/* Check that the relocation address is valid... */
176
if (unlikely(reloc->offset > obj->base.size - 4)) {
177
DRM_DEBUG("Relocation beyond object bounds: "
178
"obj %p target %d offset %d size %d.\n",
179
obj, reloc->target_handle,
181
(int) obj->base.size);
184
if (unlikely(reloc->offset & 3)) {
185
DRM_DEBUG("Relocation not 4-byte aligned: "
186
"obj %p target %d offset %d.\n",
187
obj, reloc->target_handle,
188
(int) reloc->offset);
192
/* We can't wait for rendering with pagefaults disabled */
193
if (obj->active && in_atomic())
196
reloc->delta += target_offset;
197
if (use_cpu_reloc(obj)) {
198
uint32_t page_offset = reloc->offset & ~PAGE_MASK;
201
ret = i915_gem_object_set_to_cpu_domain(obj, 1);
205
vaddr = kmap_atomic(i915_gem_object_get_page(obj,
206
reloc->offset >> PAGE_SHIFT));
207
*(uint32_t *)(vaddr + page_offset) = reloc->delta;
208
kunmap_atomic(vaddr);
210
struct drm_i915_private *dev_priv = dev->dev_private;
211
uint32_t __iomem *reloc_entry;
212
void __iomem *reloc_page;
214
ret = i915_gem_object_set_to_gtt_domain(obj, true);
218
ret = i915_gem_object_put_fence(obj);
222
/* Map the page containing the relocation we're going to perform. */
223
reloc->offset += obj->gtt_offset;
224
reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
225
reloc->offset & PAGE_MASK);
226
reloc_entry = (uint32_t __iomem *)
227
(reloc_page + (reloc->offset & ~PAGE_MASK));
228
iowrite32(reloc->delta, reloc_entry);
229
io_mapping_unmap_atomic(reloc_page);
232
/* and update the user's relocation entry */
233
reloc->presumed_offset = target_offset;
239
i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
240
struct eb_objects *eb)
242
#define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
243
struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
244
struct drm_i915_gem_relocation_entry __user *user_relocs;
245
struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
248
user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
250
remain = entry->relocation_count;
252
struct drm_i915_gem_relocation_entry *r = stack_reloc;
254
if (count > ARRAY_SIZE(stack_reloc))
255
count = ARRAY_SIZE(stack_reloc);
258
if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
262
u64 offset = r->presumed_offset;
264
ret = i915_gem_execbuffer_relocate_entry(obj, eb, r);
268
if (r->presumed_offset != offset &&
269
__copy_to_user_inatomic(&user_relocs->presumed_offset,
271
sizeof(r->presumed_offset))) {
285
i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj,
286
struct eb_objects *eb,
287
struct drm_i915_gem_relocation_entry *relocs)
289
const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
292
for (i = 0; i < entry->relocation_count; i++) {
293
ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]);
302
i915_gem_execbuffer_relocate(struct drm_device *dev,
303
struct eb_objects *eb,
304
struct list_head *objects)
306
struct drm_i915_gem_object *obj;
309
/* This is the fast path and we cannot handle a pagefault whilst
310
* holding the struct mutex lest the user pass in the relocations
311
* contained within a mmaped bo. For in such a case we, the page
312
* fault handler would call i915_gem_fault() and we would try to
313
* acquire the struct mutex again. Obviously this is bad and so
314
* lockdep complains vehemently.
317
list_for_each_entry(obj, objects, exec_list) {
318
ret = i915_gem_execbuffer_relocate_object(obj, eb);
327
#define __EXEC_OBJECT_HAS_PIN (1<<31)
328
#define __EXEC_OBJECT_HAS_FENCE (1<<30)
331
need_reloc_mappable(struct drm_i915_gem_object *obj)
333
struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
334
return entry->relocation_count && !use_cpu_reloc(obj);
338
i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object *obj,
339
struct intel_ring_buffer *ring)
341
struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
342
struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
343
bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
344
bool need_fence, need_mappable;
348
has_fenced_gpu_access &&
349
entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
350
obj->tiling_mode != I915_TILING_NONE;
351
need_mappable = need_fence || need_reloc_mappable(obj);
353
ret = i915_gem_object_pin(obj, entry->alignment, need_mappable, false);
357
entry->flags |= __EXEC_OBJECT_HAS_PIN;
359
if (has_fenced_gpu_access) {
360
if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
361
ret = i915_gem_object_get_fence(obj);
365
if (i915_gem_object_pin_fence(obj))
366
entry->flags |= __EXEC_OBJECT_HAS_FENCE;
368
obj->pending_fenced_gpu_access = true;
372
/* Ensure ppgtt mapping exists if needed */
373
if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) {
374
i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
375
obj, obj->cache_level);
377
obj->has_aliasing_ppgtt_mapping = 1;
380
entry->offset = obj->gtt_offset;
385
i915_gem_execbuffer_unreserve_object(struct drm_i915_gem_object *obj)
387
struct drm_i915_gem_exec_object2 *entry;
392
entry = obj->exec_entry;
394
if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
395
i915_gem_object_unpin_fence(obj);
397
if (entry->flags & __EXEC_OBJECT_HAS_PIN)
398
i915_gem_object_unpin(obj);
400
entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
404
i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
405
struct drm_file *file,
406
struct list_head *objects)
408
struct drm_i915_gem_object *obj;
409
struct list_head ordered_objects;
410
bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
413
INIT_LIST_HEAD(&ordered_objects);
414
while (!list_empty(objects)) {
415
struct drm_i915_gem_exec_object2 *entry;
416
bool need_fence, need_mappable;
418
obj = list_first_entry(objects,
419
struct drm_i915_gem_object,
421
entry = obj->exec_entry;
424
has_fenced_gpu_access &&
425
entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
426
obj->tiling_mode != I915_TILING_NONE;
427
need_mappable = need_fence || need_reloc_mappable(obj);
430
list_move(&obj->exec_list, &ordered_objects);
432
list_move_tail(&obj->exec_list, &ordered_objects);
434
obj->base.pending_read_domains = 0;
435
obj->base.pending_write_domain = 0;
436
obj->pending_fenced_gpu_access = false;
438
list_splice(&ordered_objects, objects);
440
/* Attempt to pin all of the buffers into the GTT.
441
* This is done in 3 phases:
443
* 1a. Unbind all objects that do not match the GTT constraints for
444
* the execbuffer (fenceable, mappable, alignment etc).
445
* 1b. Increment pin count for already bound objects.
446
* 2. Bind new objects.
447
* 3. Decrement pin count.
449
* This avoid unnecessary unbinding of later objects in order to make
450
* room for the earlier objects *unless* we need to defragment.
456
/* Unbind any ill-fitting objects or pin. */
457
list_for_each_entry(obj, objects, exec_list) {
458
struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
459
bool need_fence, need_mappable;
465
has_fenced_gpu_access &&
466
entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
467
obj->tiling_mode != I915_TILING_NONE;
468
need_mappable = need_fence || need_reloc_mappable(obj);
470
if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) ||
471
(need_mappable && !obj->map_and_fenceable))
472
ret = i915_gem_object_unbind(obj);
474
ret = i915_gem_execbuffer_reserve_object(obj, ring);
479
/* Bind fresh objects */
480
list_for_each_entry(obj, objects, exec_list) {
484
ret = i915_gem_execbuffer_reserve_object(obj, ring);
489
err: /* Decrement pin count for bound objects */
490
list_for_each_entry(obj, objects, exec_list)
491
i915_gem_execbuffer_unreserve_object(obj);
493
if (ret != -ENOSPC || retry++)
496
ret = i915_gem_evict_everything(ring->dev);
503
i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
504
struct drm_file *file,
505
struct intel_ring_buffer *ring,
506
struct list_head *objects,
507
struct eb_objects *eb,
508
struct drm_i915_gem_exec_object2 *exec,
511
struct drm_i915_gem_relocation_entry *reloc;
512
struct drm_i915_gem_object *obj;
516
/* We may process another execbuffer during the unlock... */
517
while (!list_empty(objects)) {
518
obj = list_first_entry(objects,
519
struct drm_i915_gem_object,
521
list_del_init(&obj->exec_list);
522
drm_gem_object_unreference(&obj->base);
525
mutex_unlock(&dev->struct_mutex);
528
for (i = 0; i < count; i++)
529
total += exec[i].relocation_count;
531
reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
532
reloc = drm_malloc_ab(total, sizeof(*reloc));
533
if (reloc == NULL || reloc_offset == NULL) {
534
drm_free_large(reloc);
535
drm_free_large(reloc_offset);
536
mutex_lock(&dev->struct_mutex);
541
for (i = 0; i < count; i++) {
542
struct drm_i915_gem_relocation_entry __user *user_relocs;
544
user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr;
546
if (copy_from_user(reloc+total, user_relocs,
547
exec[i].relocation_count * sizeof(*reloc))) {
549
mutex_lock(&dev->struct_mutex);
553
reloc_offset[i] = total;
554
total += exec[i].relocation_count;
557
ret = i915_mutex_lock_interruptible(dev);
559
mutex_lock(&dev->struct_mutex);
563
/* reacquire the objects */
565
for (i = 0; i < count; i++) {
566
obj = to_intel_bo(drm_gem_object_lookup(dev, file,
568
if (&obj->base == NULL) {
569
DRM_DEBUG("Invalid object handle %d at index %d\n",
575
list_add_tail(&obj->exec_list, objects);
576
obj->exec_handle = exec[i].handle;
577
obj->exec_entry = &exec[i];
578
eb_add_object(eb, obj);
581
ret = i915_gem_execbuffer_reserve(ring, file, objects);
585
list_for_each_entry(obj, objects, exec_list) {
586
int offset = obj->exec_entry - exec;
587
ret = i915_gem_execbuffer_relocate_object_slow(obj, eb,
588
reloc + reloc_offset[offset]);
593
/* Leave the user relocations as are, this is the painfully slow path,
594
* and we want to avoid the complication of dropping the lock whilst
595
* having buffers reserved in the aperture and so causing spurious
596
* ENOSPC for random operations.
600
drm_free_large(reloc);
601
drm_free_large(reloc_offset);
606
i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips)
608
u32 plane, flip_mask;
611
/* Check for any pending flips. As we only maintain a flip queue depth
612
* of 1, we can simply insert a WAIT for the next display flip prior
613
* to executing the batch and avoid stalling the CPU.
616
for (plane = 0; flips >> plane; plane++) {
617
if (((flips >> plane) & 1) == 0)
621
flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
623
flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
625
ret = intel_ring_begin(ring, 2);
629
intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
630
intel_ring_emit(ring, MI_NOOP);
631
intel_ring_advance(ring);
638
i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
639
struct list_head *objects)
641
struct drm_i915_gem_object *obj;
642
uint32_t flush_domains = 0;
646
list_for_each_entry(obj, objects, exec_list) {
647
ret = i915_gem_object_sync(obj, ring);
651
if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
652
i915_gem_clflush_object(obj);
654
if (obj->base.pending_write_domain)
655
flips |= atomic_read(&obj->pending_flip);
657
flush_domains |= obj->base.write_domain;
661
ret = i915_gem_execbuffer_wait_for_flips(ring, flips);
666
if (flush_domains & I915_GEM_DOMAIN_CPU)
667
i915_gem_chipset_flush(ring->dev);
669
if (flush_domains & I915_GEM_DOMAIN_GTT)
672
/* Unconditionally invalidate gpu caches and ensure that we do flush
673
* any residual writes from the previous batch.
675
return intel_ring_invalidate_all_caches(ring);
679
i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
681
return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
685
validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
690
for (i = 0; i < count; i++) {
691
char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
692
int length; /* limited by fault_in_pages_readable() */
694
/* First check for malicious input causing overflow */
695
if (exec[i].relocation_count >
696
INT_MAX / sizeof(struct drm_i915_gem_relocation_entry))
699
length = exec[i].relocation_count *
700
sizeof(struct drm_i915_gem_relocation_entry);
701
if (!access_ok(VERIFY_READ, ptr, length))
704
/* we may also need to update the presumed offsets */
705
if (!access_ok(VERIFY_WRITE, ptr, length))
708
if (fault_in_multipages_readable(ptr, length))
716
i915_gem_execbuffer_move_to_active(struct list_head *objects,
717
struct intel_ring_buffer *ring,
720
struct drm_i915_gem_object *obj;
722
list_for_each_entry(obj, objects, exec_list) {
723
u32 old_read = obj->base.read_domains;
724
u32 old_write = obj->base.write_domain;
726
obj->base.read_domains = obj->base.pending_read_domains;
727
obj->base.write_domain = obj->base.pending_write_domain;
728
obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
730
i915_gem_object_move_to_active(obj, ring, seqno);
731
if (obj->base.write_domain) {
733
obj->last_write_seqno = seqno;
734
if (obj->pin_count) /* check for potential scanout */
735
intel_mark_fb_busy(obj);
738
trace_i915_gem_object_change_domain(obj, old_read, old_write);
743
i915_gem_execbuffer_retire_commands(struct drm_device *dev,
744
struct drm_file *file,
745
struct intel_ring_buffer *ring)
747
/* Unconditionally force add_request to emit a full flush. */
748
ring->gpu_caches_dirty = true;
750
/* Add a breadcrumb for the completion of the batch buffer */
751
(void)i915_add_request(ring, file, NULL);
755
i915_reset_gen7_sol_offsets(struct drm_device *dev,
756
struct intel_ring_buffer *ring)
758
drm_i915_private_t *dev_priv = dev->dev_private;
761
if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS])
764
ret = intel_ring_begin(ring, 4 * 3);
768
for (i = 0; i < 4; i++) {
769
intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
770
intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
771
intel_ring_emit(ring, 0);
774
intel_ring_advance(ring);
780
i915_gem_do_execbuffer(struct drm_device *dev, void *data,
781
struct drm_file *file,
782
struct drm_i915_gem_execbuffer2 *args,
783
struct drm_i915_gem_exec_object2 *exec)
785
drm_i915_private_t *dev_priv = dev->dev_private;
786
struct list_head objects;
787
struct eb_objects *eb;
788
struct drm_i915_gem_object *batch_obj;
789
struct drm_clip_rect *cliprects = NULL;
790
struct intel_ring_buffer *ring;
791
u32 ctx_id = i915_execbuffer2_get_context_id(*args);
792
u32 exec_start, exec_len;
798
if (!i915_gem_check_execbuffer(args)) {
799
DRM_DEBUG("execbuf with invalid offset/length\n");
803
ret = validate_exec_list(exec, args->buffer_count);
808
if (args->flags & I915_EXEC_SECURE) {
809
if (!file->is_master || !capable(CAP_SYS_ADMIN))
812
flags |= I915_DISPATCH_SECURE;
815
switch (args->flags & I915_EXEC_RING_MASK) {
816
case I915_EXEC_DEFAULT:
817
case I915_EXEC_RENDER:
818
ring = &dev_priv->ring[RCS];
821
ring = &dev_priv->ring[VCS];
823
DRM_DEBUG("Ring %s doesn't support contexts\n",
829
ring = &dev_priv->ring[BCS];
831
DRM_DEBUG("Ring %s doesn't support contexts\n",
837
DRM_DEBUG("execbuf with unknown ring: %d\n",
838
(int)(args->flags & I915_EXEC_RING_MASK));
841
if (!intel_ring_initialized(ring)) {
842
DRM_DEBUG("execbuf with invalid ring: %d\n",
843
(int)(args->flags & I915_EXEC_RING_MASK));
847
mode = args->flags & I915_EXEC_CONSTANTS_MASK;
848
mask = I915_EXEC_CONSTANTS_MASK;
850
case I915_EXEC_CONSTANTS_REL_GENERAL:
851
case I915_EXEC_CONSTANTS_ABSOLUTE:
852
case I915_EXEC_CONSTANTS_REL_SURFACE:
853
if (ring == &dev_priv->ring[RCS] &&
854
mode != dev_priv->relative_constants_mode) {
855
if (INTEL_INFO(dev)->gen < 4)
858
if (INTEL_INFO(dev)->gen > 5 &&
859
mode == I915_EXEC_CONSTANTS_REL_SURFACE)
862
/* The HW changed the meaning on this bit on gen6 */
863
if (INTEL_INFO(dev)->gen >= 6)
864
mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
868
DRM_DEBUG("execbuf with unknown constants: %d\n", mode);
872
if (args->buffer_count < 1) {
873
DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
877
if (args->num_cliprects != 0) {
878
if (ring != &dev_priv->ring[RCS]) {
879
DRM_DEBUG("clip rectangles are only valid with the render ring\n");
883
if (INTEL_INFO(dev)->gen >= 5) {
884
DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
888
if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) {
889
DRM_DEBUG("execbuf with %u cliprects\n",
890
args->num_cliprects);
894
cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects),
896
if (cliprects == NULL) {
901
if (copy_from_user(cliprects,
902
(struct drm_clip_rect __user *)(uintptr_t)
904
sizeof(*cliprects)*args->num_cliprects)) {
910
ret = i915_mutex_lock_interruptible(dev);
914
if (dev_priv->mm.suspended) {
915
mutex_unlock(&dev->struct_mutex);
920
eb = eb_create(args->buffer_count);
922
mutex_unlock(&dev->struct_mutex);
927
/* Look up object handles */
928
INIT_LIST_HEAD(&objects);
929
for (i = 0; i < args->buffer_count; i++) {
930
struct drm_i915_gem_object *obj;
932
obj = to_intel_bo(drm_gem_object_lookup(dev, file,
934
if (&obj->base == NULL) {
935
DRM_DEBUG("Invalid object handle %d at index %d\n",
937
/* prevent error path from reading uninitialized data */
942
if (!list_empty(&obj->exec_list)) {
943
DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
944
obj, exec[i].handle, i);
949
list_add_tail(&obj->exec_list, &objects);
950
obj->exec_handle = exec[i].handle;
951
obj->exec_entry = &exec[i];
952
eb_add_object(eb, obj);
955
/* take note of the batch buffer before we might reorder the lists */
956
batch_obj = list_entry(objects.prev,
957
struct drm_i915_gem_object,
960
/* Move the objects en-masse into the GTT, evicting if necessary. */
961
ret = i915_gem_execbuffer_reserve(ring, file, &objects);
965
/* The objects are in their final locations, apply the relocations. */
966
ret = i915_gem_execbuffer_relocate(dev, eb, &objects);
968
if (ret == -EFAULT) {
969
ret = i915_gem_execbuffer_relocate_slow(dev, file, ring,
973
BUG_ON(!mutex_is_locked(&dev->struct_mutex));
979
/* Set the pending read domains for the batch buffer to COMMAND */
980
if (batch_obj->base.pending_write_domain) {
981
DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
985
batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
987
/* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
988
* batch" bit. Hence we need to pin secure batches into the global gtt.
989
* hsw should have this fixed, but let's be paranoid and do it
990
* unconditionally for now. */
991
if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping)
992
i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level);
994
ret = i915_gem_execbuffer_move_to_gpu(ring, &objects);
998
seqno = i915_gem_next_request_seqno(ring);
999
for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) {
1000
if (seqno < ring->sync_seqno[i]) {
1001
/* The GPU can not handle its semaphore value wrapping,
1002
* so every billion or so execbuffers, we need to stall
1003
* the GPU in order to reset the counters.
1005
ret = i915_gpu_idle(dev);
1008
i915_gem_retire_requests(dev);
1010
BUG_ON(ring->sync_seqno[i]);
1014
ret = i915_switch_context(ring, file, ctx_id);
1018
if (ring == &dev_priv->ring[RCS] &&
1019
mode != dev_priv->relative_constants_mode) {
1020
ret = intel_ring_begin(ring, 4);
1024
intel_ring_emit(ring, MI_NOOP);
1025
intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1026
intel_ring_emit(ring, INSTPM);
1027
intel_ring_emit(ring, mask << 16 | mode);
1028
intel_ring_advance(ring);
1030
dev_priv->relative_constants_mode = mode;
1033
if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1034
ret = i915_reset_gen7_sol_offsets(dev, ring);
1039
trace_i915_gem_ring_dispatch(ring, seqno, flags);
1041
exec_start = batch_obj->gtt_offset + args->batch_start_offset;
1042
exec_len = args->batch_len;
1044
for (i = 0; i < args->num_cliprects; i++) {
1045
ret = i915_emit_box(dev, &cliprects[i],
1046
args->DR1, args->DR4);
1050
ret = ring->dispatch_execbuffer(ring,
1051
exec_start, exec_len,
1057
ret = ring->dispatch_execbuffer(ring,
1058
exec_start, exec_len,
1064
i915_gem_execbuffer_move_to_active(&objects, ring, seqno);
1065
i915_gem_execbuffer_retire_commands(dev, file, ring);
1069
while (!list_empty(&objects)) {
1070
struct drm_i915_gem_object *obj;
1072
obj = list_first_entry(&objects,
1073
struct drm_i915_gem_object,
1075
list_del_init(&obj->exec_list);
1076
drm_gem_object_unreference(&obj->base);
1079
mutex_unlock(&dev->struct_mutex);
1087
* Legacy execbuffer just creates an exec2 list from the original exec object
1088
* list array and passes it to the real function.
1091
i915_gem_execbuffer(struct drm_device *dev, void *data,
1092
struct drm_file *file)
1094
struct drm_i915_gem_execbuffer *args = data;
1095
struct drm_i915_gem_execbuffer2 exec2;
1096
struct drm_i915_gem_exec_object *exec_list = NULL;
1097
struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1100
if (args->buffer_count < 1) {
1101
DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1105
/* Copy in the exec list from userland */
1106
exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1107
exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1108
if (exec_list == NULL || exec2_list == NULL) {
1109
DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1110
args->buffer_count);
1111
drm_free_large(exec_list);
1112
drm_free_large(exec2_list);
1115
ret = copy_from_user(exec_list,
1116
(void __user *)(uintptr_t)args->buffers_ptr,
1117
sizeof(*exec_list) * args->buffer_count);
1119
DRM_DEBUG("copy %d exec entries failed %d\n",
1120
args->buffer_count, ret);
1121
drm_free_large(exec_list);
1122
drm_free_large(exec2_list);
1126
for (i = 0; i < args->buffer_count; i++) {
1127
exec2_list[i].handle = exec_list[i].handle;
1128
exec2_list[i].relocation_count = exec_list[i].relocation_count;
1129
exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1130
exec2_list[i].alignment = exec_list[i].alignment;
1131
exec2_list[i].offset = exec_list[i].offset;
1132
if (INTEL_INFO(dev)->gen < 4)
1133
exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1135
exec2_list[i].flags = 0;
1138
exec2.buffers_ptr = args->buffers_ptr;
1139
exec2.buffer_count = args->buffer_count;
1140
exec2.batch_start_offset = args->batch_start_offset;
1141
exec2.batch_len = args->batch_len;
1142
exec2.DR1 = args->DR1;
1143
exec2.DR4 = args->DR4;
1144
exec2.num_cliprects = args->num_cliprects;
1145
exec2.cliprects_ptr = args->cliprects_ptr;
1146
exec2.flags = I915_EXEC_RENDER;
1147
i915_execbuffer2_set_context_id(exec2, 0);
1149
ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1151
/* Copy the new buffer offsets back to the user's exec list. */
1152
for (i = 0; i < args->buffer_count; i++)
1153
exec_list[i].offset = exec2_list[i].offset;
1154
/* ... and back out to userspace */
1155
ret = copy_to_user((void __user *)(uintptr_t)args->buffers_ptr,
1157
sizeof(*exec_list) * args->buffer_count);
1160
DRM_DEBUG("failed to copy %d exec entries "
1161
"back to user (%d)\n",
1162
args->buffer_count, ret);
1166
drm_free_large(exec_list);
1167
drm_free_large(exec2_list);
1172
i915_gem_execbuffer2(struct drm_device *dev, void *data,
1173
struct drm_file *file)
1175
struct drm_i915_gem_execbuffer2 *args = data;
1176
struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1179
if (args->buffer_count < 1 ||
1180
args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1181
DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1185
exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1186
GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY);
1187
if (exec2_list == NULL)
1188
exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1189
args->buffer_count);
1190
if (exec2_list == NULL) {
1191
DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1192
args->buffer_count);
1195
ret = copy_from_user(exec2_list,
1196
(struct drm_i915_relocation_entry __user *)
1197
(uintptr_t) args->buffers_ptr,
1198
sizeof(*exec2_list) * args->buffer_count);
1200
DRM_DEBUG("copy %d exec entries failed %d\n",
1201
args->buffer_count, ret);
1202
drm_free_large(exec2_list);
1206
ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1208
/* Copy the new buffer offsets back to the user's exec list. */
1209
ret = copy_to_user((void __user *)(uintptr_t)args->buffers_ptr,
1211
sizeof(*exec2_list) * args->buffer_count);
1214
DRM_DEBUG("failed to copy %d exec entries "
1215
"back to user (%d)\n",
1216
args->buffer_count, ret);
1220
drm_free_large(exec2_list);