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* Copyright © 2006-2007 Intel Corporation
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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* Eric Anholt <eric@anholt.net>
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#include <linux/dmi.h>
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#include <linux/module.h>
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#include <linux/input.h>
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#include <linux/i2c.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/vgaarb.h>
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#include <drm/drm_edid.h>
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#include "intel_drv.h"
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#include "i915_trace.h"
40
#include "drm_dp_helper.h"
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#include "drm_crtc_helper.h"
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#include <linux/dma_remapping.h>
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bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
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static void intel_increase_pllclock(struct drm_crtc *crtc);
46
static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
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#define INTEL_P2_NUM 2
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typedef struct intel_limit intel_limit_t;
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intel_range_t dot, vco, n, m, m1, m2, p, p1;
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bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
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int, int, intel_clock_t *, intel_clock_t *);
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#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
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intel_pch_rawclk(struct drm_device *dev)
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struct drm_i915_private *dev_priv = dev->dev_private;
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WARN_ON(!HAS_PCH_SPLIT(dev));
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return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
92
intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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int target, int refclk, intel_clock_t *match_clock,
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intel_clock_t *best_clock);
96
intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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int target, int refclk, intel_clock_t *match_clock,
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intel_clock_t *best_clock);
101
intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
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int target, int refclk, intel_clock_t *match_clock,
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intel_clock_t *best_clock);
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intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
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int target, int refclk, intel_clock_t *match_clock,
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intel_clock_t *best_clock);
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intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
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int target, int refclk, intel_clock_t *match_clock,
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intel_clock_t *best_clock);
114
static inline u32 /* units of 100MHz */
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intel_fdi_link_freq(struct drm_device *dev)
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struct drm_i915_private *dev_priv = dev->dev_private;
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return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
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static const intel_limit_t intel_limits_i8xx_dvo = {
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.dot = { .min = 25000, .max = 350000 },
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.vco = { .min = 930000, .max = 1400000 },
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.n = { .min = 3, .max = 16 },
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.m = { .min = 96, .max = 140 },
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.m1 = { .min = 18, .max = 26 },
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.m2 = { .min = 6, .max = 16 },
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.p = { .min = 4, .max = 128 },
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.p1 = { .min = 2, .max = 33 },
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.p2 = { .dot_limit = 165000,
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.p2_slow = 4, .p2_fast = 2 },
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.find_pll = intel_find_best_PLL,
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static const intel_limit_t intel_limits_i8xx_lvds = {
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.dot = { .min = 25000, .max = 350000 },
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.vco = { .min = 930000, .max = 1400000 },
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.n = { .min = 3, .max = 16 },
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.m = { .min = 96, .max = 140 },
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.m1 = { .min = 18, .max = 26 },
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.m2 = { .min = 6, .max = 16 },
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.p = { .min = 4, .max = 128 },
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.p1 = { .min = 1, .max = 6 },
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.p2 = { .dot_limit = 165000,
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.p2_slow = 14, .p2_fast = 7 },
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.find_pll = intel_find_best_PLL,
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static const intel_limit_t intel_limits_i9xx_sdvo = {
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.dot = { .min = 20000, .max = 400000 },
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.vco = { .min = 1400000, .max = 2800000 },
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.n = { .min = 1, .max = 6 },
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.m = { .min = 70, .max = 120 },
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.m1 = { .min = 10, .max = 22 },
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.m2 = { .min = 5, .max = 9 },
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.p = { .min = 5, .max = 80 },
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.p1 = { .min = 1, .max = 8 },
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.p2 = { .dot_limit = 200000,
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.p2_slow = 10, .p2_fast = 5 },
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.find_pll = intel_find_best_PLL,
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static const intel_limit_t intel_limits_i9xx_lvds = {
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.dot = { .min = 20000, .max = 400000 },
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.vco = { .min = 1400000, .max = 2800000 },
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.n = { .min = 1, .max = 6 },
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.m = { .min = 70, .max = 120 },
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.m1 = { .min = 10, .max = 22 },
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.m2 = { .min = 5, .max = 9 },
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.p = { .min = 7, .max = 98 },
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.p1 = { .min = 1, .max = 8 },
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.p2 = { .dot_limit = 112000,
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.p2_slow = 14, .p2_fast = 7 },
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.find_pll = intel_find_best_PLL,
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static const intel_limit_t intel_limits_g4x_sdvo = {
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.dot = { .min = 25000, .max = 270000 },
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.vco = { .min = 1750000, .max = 3500000},
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.n = { .min = 1, .max = 4 },
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.m = { .min = 104, .max = 138 },
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.m1 = { .min = 17, .max = 23 },
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.m2 = { .min = 5, .max = 11 },
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.p = { .min = 10, .max = 30 },
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.p1 = { .min = 1, .max = 3},
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.p2 = { .dot_limit = 270000,
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.find_pll = intel_g4x_find_best_PLL,
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static const intel_limit_t intel_limits_g4x_hdmi = {
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.dot = { .min = 22000, .max = 400000 },
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.vco = { .min = 1750000, .max = 3500000},
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.n = { .min = 1, .max = 4 },
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.m = { .min = 104, .max = 138 },
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.m1 = { .min = 16, .max = 23 },
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.m2 = { .min = 5, .max = 11 },
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.p = { .min = 5, .max = 80 },
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.p1 = { .min = 1, .max = 8},
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.p2 = { .dot_limit = 165000,
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.p2_slow = 10, .p2_fast = 5 },
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.find_pll = intel_g4x_find_best_PLL,
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static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
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.dot = { .min = 20000, .max = 115000 },
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.vco = { .min = 1750000, .max = 3500000 },
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.n = { .min = 1, .max = 3 },
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.m = { .min = 104, .max = 138 },
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.m1 = { .min = 17, .max = 23 },
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.m2 = { .min = 5, .max = 11 },
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.p = { .min = 28, .max = 112 },
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.p1 = { .min = 2, .max = 8 },
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.p2 = { .dot_limit = 0,
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.p2_slow = 14, .p2_fast = 14
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.find_pll = intel_g4x_find_best_PLL,
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static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
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.dot = { .min = 80000, .max = 224000 },
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.vco = { .min = 1750000, .max = 3500000 },
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.n = { .min = 1, .max = 3 },
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.m = { .min = 104, .max = 138 },
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.m1 = { .min = 17, .max = 23 },
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.m2 = { .min = 5, .max = 11 },
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.p = { .min = 14, .max = 42 },
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.p1 = { .min = 2, .max = 6 },
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.p2 = { .dot_limit = 0,
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.p2_slow = 7, .p2_fast = 7
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.find_pll = intel_g4x_find_best_PLL,
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static const intel_limit_t intel_limits_g4x_display_port = {
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.dot = { .min = 161670, .max = 227000 },
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.vco = { .min = 1750000, .max = 3500000},
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.n = { .min = 1, .max = 2 },
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.m = { .min = 97, .max = 108 },
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.m1 = { .min = 0x10, .max = 0x12 },
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.m2 = { .min = 0x05, .max = 0x06 },
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.p = { .min = 10, .max = 20 },
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.p1 = { .min = 1, .max = 2},
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.p2 = { .dot_limit = 0,
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.p2_slow = 10, .p2_fast = 10 },
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.find_pll = intel_find_pll_g4x_dp,
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static const intel_limit_t intel_limits_pineview_sdvo = {
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.dot = { .min = 20000, .max = 400000},
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.vco = { .min = 1700000, .max = 3500000 },
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/* Pineview's Ncounter is a ring counter */
259
.n = { .min = 3, .max = 6 },
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.m = { .min = 2, .max = 256 },
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/* Pineview only has one combined m divider, which we treat as m2. */
262
.m1 = { .min = 0, .max = 0 },
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.m2 = { .min = 0, .max = 254 },
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.p = { .min = 5, .max = 80 },
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.p1 = { .min = 1, .max = 8 },
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.p2 = { .dot_limit = 200000,
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.p2_slow = 10, .p2_fast = 5 },
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.find_pll = intel_find_best_PLL,
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static const intel_limit_t intel_limits_pineview_lvds = {
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.dot = { .min = 20000, .max = 400000 },
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.vco = { .min = 1700000, .max = 3500000 },
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.n = { .min = 3, .max = 6 },
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.m = { .min = 2, .max = 256 },
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.m1 = { .min = 0, .max = 0 },
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.m2 = { .min = 0, .max = 254 },
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.p = { .min = 7, .max = 112 },
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.p1 = { .min = 1, .max = 8 },
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.p2 = { .dot_limit = 112000,
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.p2_slow = 14, .p2_fast = 14 },
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.find_pll = intel_find_best_PLL,
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/* Ironlake / Sandybridge
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* We calculate clock using (register_value + 2) for N/M1/M2, so here
288
* the range value for them is (actual_value - 2).
290
static const intel_limit_t intel_limits_ironlake_dac = {
291
.dot = { .min = 25000, .max = 350000 },
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.vco = { .min = 1760000, .max = 3510000 },
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.n = { .min = 1, .max = 5 },
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.m = { .min = 79, .max = 127 },
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.m1 = { .min = 12, .max = 22 },
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.m2 = { .min = 5, .max = 9 },
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.p = { .min = 5, .max = 80 },
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.p1 = { .min = 1, .max = 8 },
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.p2 = { .dot_limit = 225000,
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.p2_slow = 10, .p2_fast = 5 },
301
.find_pll = intel_g4x_find_best_PLL,
304
static const intel_limit_t intel_limits_ironlake_single_lvds = {
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.dot = { .min = 25000, .max = 350000 },
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.vco = { .min = 1760000, .max = 3510000 },
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.n = { .min = 1, .max = 3 },
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.m = { .min = 79, .max = 118 },
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.m1 = { .min = 12, .max = 22 },
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.m2 = { .min = 5, .max = 9 },
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.p = { .min = 28, .max = 112 },
312
.p1 = { .min = 2, .max = 8 },
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.p2 = { .dot_limit = 225000,
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.p2_slow = 14, .p2_fast = 14 },
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.find_pll = intel_g4x_find_best_PLL,
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static const intel_limit_t intel_limits_ironlake_dual_lvds = {
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.dot = { .min = 25000, .max = 350000 },
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.vco = { .min = 1760000, .max = 3510000 },
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.n = { .min = 1, .max = 3 },
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.m = { .min = 79, .max = 127 },
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.m1 = { .min = 12, .max = 22 },
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.m2 = { .min = 5, .max = 9 },
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.p = { .min = 14, .max = 56 },
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.p1 = { .min = 2, .max = 8 },
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.p2 = { .dot_limit = 225000,
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.p2_slow = 7, .p2_fast = 7 },
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.find_pll = intel_g4x_find_best_PLL,
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/* LVDS 100mhz refclk limits. */
333
static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
334
.dot = { .min = 25000, .max = 350000 },
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.vco = { .min = 1760000, .max = 3510000 },
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.n = { .min = 1, .max = 2 },
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.m = { .min = 79, .max = 126 },
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.m1 = { .min = 12, .max = 22 },
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.m2 = { .min = 5, .max = 9 },
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.p = { .min = 28, .max = 112 },
341
.p1 = { .min = 2, .max = 8 },
342
.p2 = { .dot_limit = 225000,
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.p2_slow = 14, .p2_fast = 14 },
344
.find_pll = intel_g4x_find_best_PLL,
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static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
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.dot = { .min = 25000, .max = 350000 },
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.vco = { .min = 1760000, .max = 3510000 },
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.n = { .min = 1, .max = 3 },
351
.m = { .min = 79, .max = 126 },
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.m1 = { .min = 12, .max = 22 },
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.m2 = { .min = 5, .max = 9 },
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.p = { .min = 14, .max = 42 },
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.p1 = { .min = 2, .max = 6 },
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.p2 = { .dot_limit = 225000,
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.p2_slow = 7, .p2_fast = 7 },
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.find_pll = intel_g4x_find_best_PLL,
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static const intel_limit_t intel_limits_ironlake_display_port = {
362
.dot = { .min = 25000, .max = 350000 },
363
.vco = { .min = 1760000, .max = 3510000},
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.n = { .min = 1, .max = 2 },
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.m = { .min = 81, .max = 90 },
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.m1 = { .min = 12, .max = 22 },
367
.m2 = { .min = 5, .max = 9 },
368
.p = { .min = 10, .max = 20 },
369
.p1 = { .min = 1, .max = 2},
370
.p2 = { .dot_limit = 0,
371
.p2_slow = 10, .p2_fast = 10 },
372
.find_pll = intel_find_pll_ironlake_dp,
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static const intel_limit_t intel_limits_vlv_dac = {
376
.dot = { .min = 25000, .max = 270000 },
377
.vco = { .min = 4000000, .max = 6000000 },
378
.n = { .min = 1, .max = 7 },
379
.m = { .min = 22, .max = 450 }, /* guess */
380
.m1 = { .min = 2, .max = 3 },
381
.m2 = { .min = 11, .max = 156 },
382
.p = { .min = 10, .max = 30 },
383
.p1 = { .min = 2, .max = 3 },
384
.p2 = { .dot_limit = 270000,
385
.p2_slow = 2, .p2_fast = 20 },
386
.find_pll = intel_vlv_find_best_pll,
389
static const intel_limit_t intel_limits_vlv_hdmi = {
390
.dot = { .min = 20000, .max = 165000 },
391
.vco = { .min = 4000000, .max = 5994000},
392
.n = { .min = 1, .max = 7 },
393
.m = { .min = 60, .max = 300 }, /* guess */
394
.m1 = { .min = 2, .max = 3 },
395
.m2 = { .min = 11, .max = 156 },
396
.p = { .min = 10, .max = 30 },
397
.p1 = { .min = 2, .max = 3 },
398
.p2 = { .dot_limit = 270000,
399
.p2_slow = 2, .p2_fast = 20 },
400
.find_pll = intel_vlv_find_best_pll,
403
static const intel_limit_t intel_limits_vlv_dp = {
404
.dot = { .min = 25000, .max = 270000 },
405
.vco = { .min = 4000000, .max = 6000000 },
406
.n = { .min = 1, .max = 7 },
407
.m = { .min = 22, .max = 450 },
408
.m1 = { .min = 2, .max = 3 },
409
.m2 = { .min = 11, .max = 156 },
410
.p = { .min = 10, .max = 30 },
411
.p1 = { .min = 2, .max = 3 },
412
.p2 = { .dot_limit = 270000,
413
.p2_slow = 2, .p2_fast = 20 },
414
.find_pll = intel_vlv_find_best_pll,
417
u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
422
spin_lock_irqsave(&dev_priv->dpio_lock, flags);
423
if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424
DRM_ERROR("DPIO idle wait timed out\n");
428
I915_WRITE(DPIO_REG, reg);
429
I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
431
if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
432
DRM_ERROR("DPIO read wait timed out\n");
435
val = I915_READ(DPIO_DATA);
438
spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
442
static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
447
spin_lock_irqsave(&dev_priv->dpio_lock, flags);
448
if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
449
DRM_ERROR("DPIO idle wait timed out\n");
453
I915_WRITE(DPIO_DATA, val);
454
I915_WRITE(DPIO_REG, reg);
455
I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
457
if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
458
DRM_ERROR("DPIO write wait timed out\n");
461
spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
464
static void vlv_init_dpio(struct drm_device *dev)
466
struct drm_i915_private *dev_priv = dev->dev_private;
468
/* Reset the DPIO config */
469
I915_WRITE(DPIO_CTL, 0);
470
POSTING_READ(DPIO_CTL);
471
I915_WRITE(DPIO_CTL, 1);
472
POSTING_READ(DPIO_CTL);
475
static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
477
DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
481
static const struct dmi_system_id intel_dual_link_lvds[] = {
483
.callback = intel_dual_link_lvds_callback,
484
.ident = "Apple MacBook Pro (Core i5/i7 Series)",
486
DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
487
DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
490
{ } /* terminating entry */
493
static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
498
/* use the module option value if specified */
499
if (i915_lvds_channel_mode > 0)
500
return i915_lvds_channel_mode == 2;
502
if (dmi_check_system(intel_dual_link_lvds))
505
if (dev_priv->lvds_val)
506
val = dev_priv->lvds_val;
508
/* BIOS should set the proper LVDS register value at boot, but
509
* in reality, it doesn't set the value when the lid is closed;
510
* we need to check "the value to be set" in VBT when LVDS
511
* register is uninitialized.
513
val = I915_READ(reg);
514
if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
515
val = dev_priv->bios_lvds_val;
516
dev_priv->lvds_val = val;
518
return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
521
static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
524
struct drm_device *dev = crtc->dev;
525
struct drm_i915_private *dev_priv = dev->dev_private;
526
const intel_limit_t *limit;
528
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
529
if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
530
/* LVDS dual channel */
531
if (refclk == 100000)
532
limit = &intel_limits_ironlake_dual_lvds_100m;
534
limit = &intel_limits_ironlake_dual_lvds;
536
if (refclk == 100000)
537
limit = &intel_limits_ironlake_single_lvds_100m;
539
limit = &intel_limits_ironlake_single_lvds;
541
} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
542
intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
543
limit = &intel_limits_ironlake_display_port;
545
limit = &intel_limits_ironlake_dac;
550
static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
552
struct drm_device *dev = crtc->dev;
553
struct drm_i915_private *dev_priv = dev->dev_private;
554
const intel_limit_t *limit;
556
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
557
if (is_dual_link_lvds(dev_priv, LVDS))
558
/* LVDS with dual channel */
559
limit = &intel_limits_g4x_dual_channel_lvds;
561
/* LVDS with dual channel */
562
limit = &intel_limits_g4x_single_channel_lvds;
563
} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
564
intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
565
limit = &intel_limits_g4x_hdmi;
566
} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
567
limit = &intel_limits_g4x_sdvo;
568
} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
569
limit = &intel_limits_g4x_display_port;
570
} else /* The option is for other outputs */
571
limit = &intel_limits_i9xx_sdvo;
576
static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
578
struct drm_device *dev = crtc->dev;
579
const intel_limit_t *limit;
581
if (HAS_PCH_SPLIT(dev))
582
limit = intel_ironlake_limit(crtc, refclk);
583
else if (IS_G4X(dev)) {
584
limit = intel_g4x_limit(crtc);
585
} else if (IS_PINEVIEW(dev)) {
586
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
587
limit = &intel_limits_pineview_lvds;
589
limit = &intel_limits_pineview_sdvo;
590
} else if (IS_VALLEYVIEW(dev)) {
591
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
592
limit = &intel_limits_vlv_dac;
593
else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
594
limit = &intel_limits_vlv_hdmi;
596
limit = &intel_limits_vlv_dp;
597
} else if (!IS_GEN2(dev)) {
598
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
599
limit = &intel_limits_i9xx_lvds;
601
limit = &intel_limits_i9xx_sdvo;
603
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
604
limit = &intel_limits_i8xx_lvds;
606
limit = &intel_limits_i8xx_dvo;
611
/* m1 is reserved as 0 in Pineview, n is a ring counter */
612
static void pineview_clock(int refclk, intel_clock_t *clock)
614
clock->m = clock->m2 + 2;
615
clock->p = clock->p1 * clock->p2;
616
clock->vco = refclk * clock->m / clock->n;
617
clock->dot = clock->vco / clock->p;
620
static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
622
if (IS_PINEVIEW(dev)) {
623
pineview_clock(refclk, clock);
626
clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
627
clock->p = clock->p1 * clock->p2;
628
clock->vco = refclk * clock->m / (clock->n + 2);
629
clock->dot = clock->vco / clock->p;
633
* Returns whether any output on the specified pipe is of the specified type
635
bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
637
struct drm_device *dev = crtc->dev;
638
struct intel_encoder *encoder;
640
for_each_encoder_on_crtc(dev, crtc, encoder)
641
if (encoder->type == type)
647
#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
649
* Returns whether the given set of divisors are valid for a given refclk with
650
* the given connectors.
653
static bool intel_PLL_is_valid(struct drm_device *dev,
654
const intel_limit_t *limit,
655
const intel_clock_t *clock)
657
if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
658
INTELPllInvalid("p1 out of range\n");
659
if (clock->p < limit->p.min || limit->p.max < clock->p)
660
INTELPllInvalid("p out of range\n");
661
if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
662
INTELPllInvalid("m2 out of range\n");
663
if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
664
INTELPllInvalid("m1 out of range\n");
665
if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
666
INTELPllInvalid("m1 <= m2\n");
667
if (clock->m < limit->m.min || limit->m.max < clock->m)
668
INTELPllInvalid("m out of range\n");
669
if (clock->n < limit->n.min || limit->n.max < clock->n)
670
INTELPllInvalid("n out of range\n");
671
if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
672
INTELPllInvalid("vco out of range\n");
673
/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
674
* connector, etc., rather than just a single range.
676
if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
677
INTELPllInvalid("dot out of range\n");
683
intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
684
int target, int refclk, intel_clock_t *match_clock,
685
intel_clock_t *best_clock)
688
struct drm_device *dev = crtc->dev;
689
struct drm_i915_private *dev_priv = dev->dev_private;
693
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
694
(I915_READ(LVDS)) != 0) {
696
* For LVDS, if the panel is on, just rely on its current
697
* settings for dual-channel. We haven't figured out how to
698
* reliably set up different single/dual channel state, if we
701
if (is_dual_link_lvds(dev_priv, LVDS))
702
clock.p2 = limit->p2.p2_fast;
704
clock.p2 = limit->p2.p2_slow;
706
if (target < limit->p2.dot_limit)
707
clock.p2 = limit->p2.p2_slow;
709
clock.p2 = limit->p2.p2_fast;
712
memset(best_clock, 0, sizeof(*best_clock));
714
for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
716
for (clock.m2 = limit->m2.min;
717
clock.m2 <= limit->m2.max; clock.m2++) {
718
/* m1 is always 0 in Pineview */
719
if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
721
for (clock.n = limit->n.min;
722
clock.n <= limit->n.max; clock.n++) {
723
for (clock.p1 = limit->p1.min;
724
clock.p1 <= limit->p1.max; clock.p1++) {
727
intel_clock(dev, refclk, &clock);
728
if (!intel_PLL_is_valid(dev, limit,
732
clock.p != match_clock->p)
735
this_err = abs(clock.dot - target);
736
if (this_err < err) {
745
return (err != target);
749
intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
750
int target, int refclk, intel_clock_t *match_clock,
751
intel_clock_t *best_clock)
753
struct drm_device *dev = crtc->dev;
754
struct drm_i915_private *dev_priv = dev->dev_private;
758
/* approximately equals target * 0.00585 */
759
int err_most = (target >> 8) + (target >> 9);
762
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
765
if (HAS_PCH_SPLIT(dev))
769
if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
771
clock.p2 = limit->p2.p2_fast;
773
clock.p2 = limit->p2.p2_slow;
775
if (target < limit->p2.dot_limit)
776
clock.p2 = limit->p2.p2_slow;
778
clock.p2 = limit->p2.p2_fast;
781
memset(best_clock, 0, sizeof(*best_clock));
782
max_n = limit->n.max;
783
/* based on hardware requirement, prefer smaller n to precision */
784
for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
785
/* based on hardware requirement, prefere larger m1,m2 */
786
for (clock.m1 = limit->m1.max;
787
clock.m1 >= limit->m1.min; clock.m1--) {
788
for (clock.m2 = limit->m2.max;
789
clock.m2 >= limit->m2.min; clock.m2--) {
790
for (clock.p1 = limit->p1.max;
791
clock.p1 >= limit->p1.min; clock.p1--) {
794
intel_clock(dev, refclk, &clock);
795
if (!intel_PLL_is_valid(dev, limit,
799
clock.p != match_clock->p)
802
this_err = abs(clock.dot - target);
803
if (this_err < err_most) {
817
intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
818
int target, int refclk, intel_clock_t *match_clock,
819
intel_clock_t *best_clock)
821
struct drm_device *dev = crtc->dev;
824
if (target < 200000) {
837
intel_clock(dev, refclk, &clock);
838
memcpy(best_clock, &clock, sizeof(intel_clock_t));
842
/* DisplayPort has only two frequencies, 162MHz and 270MHz */
844
intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
845
int target, int refclk, intel_clock_t *match_clock,
846
intel_clock_t *best_clock)
849
if (target < 200000) {
862
clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
863
clock.p = (clock.p1 * clock.p2);
864
clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
866
memcpy(best_clock, &clock, sizeof(intel_clock_t));
870
intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
871
int target, int refclk, intel_clock_t *match_clock,
872
intel_clock_t *best_clock)
874
u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
876
u32 updrate, minupdate, fracbits, p;
877
unsigned long bestppm, ppm, absppm;
881
dotclk = target * 1000;
884
fastclk = dotclk / (2*100);
888
n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
889
bestm1 = bestm2 = bestp1 = bestp2 = 0;
891
/* based on hardware requirement, prefer smaller n to precision */
892
for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
893
updrate = refclk / n;
894
for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
895
for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
899
/* based on hardware requirement, prefer bigger m1,m2 values */
900
for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
901
m2 = (((2*(fastclk * p * n / m1 )) +
902
refclk) / (2*refclk));
905
if (vco >= limit->vco.min && vco < limit->vco.max) {
906
ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
907
absppm = (ppm > 0) ? ppm : (-ppm);
908
if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
912
if (absppm < bestppm - 10) {
929
best_clock->n = bestn;
930
best_clock->m1 = bestm1;
931
best_clock->m2 = bestm2;
932
best_clock->p1 = bestp1;
933
best_clock->p2 = bestp2;
938
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
941
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
942
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
944
return intel_crtc->cpu_transcoder;
947
static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
949
struct drm_i915_private *dev_priv = dev->dev_private;
950
u32 frame, frame_reg = PIPEFRAME(pipe);
952
frame = I915_READ(frame_reg);
954
if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
955
DRM_DEBUG_KMS("vblank wait timed out\n");
959
* intel_wait_for_vblank - wait for vblank on a given pipe
961
* @pipe: pipe to wait for
963
* Wait for vblank to occur on a given pipe. Needed for various bits of
966
void intel_wait_for_vblank(struct drm_device *dev, int pipe)
968
struct drm_i915_private *dev_priv = dev->dev_private;
969
int pipestat_reg = PIPESTAT(pipe);
971
if (INTEL_INFO(dev)->gen >= 5) {
972
ironlake_wait_for_vblank(dev, pipe);
976
/* Clear existing vblank status. Note this will clear any other
977
* sticky status fields as well.
979
* This races with i915_driver_irq_handler() with the result
980
* that either function could miss a vblank event. Here it is not
981
* fatal, as we will either wait upon the next vblank interrupt or
982
* timeout. Generally speaking intel_wait_for_vblank() is only
983
* called during modeset at which time the GPU should be idle and
984
* should *not* be performing page flips and thus not waiting on
986
* Currently, the result of us stealing a vblank from the irq
987
* handler is that a single frame will be skipped during swapbuffers.
989
I915_WRITE(pipestat_reg,
990
I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
992
/* Wait for vblank interrupt bit to set */
993
if (wait_for(I915_READ(pipestat_reg) &
994
PIPE_VBLANK_INTERRUPT_STATUS,
996
DRM_DEBUG_KMS("vblank wait timed out\n");
1000
* intel_wait_for_pipe_off - wait for pipe to turn off
1002
* @pipe: pipe to wait for
1004
* After disabling a pipe, we can't wait for vblank in the usual way,
1005
* spinning on the vblank interrupt status bit, since we won't actually
1006
* see an interrupt when the pipe is disabled.
1008
* On Gen4 and above:
1009
* wait for the pipe register state bit to turn off
1012
* wait for the display line value to settle (it usually
1013
* ends up stopping at the start of the next frame).
1016
void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1018
struct drm_i915_private *dev_priv = dev->dev_private;
1019
enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022
if (INTEL_INFO(dev)->gen >= 4) {
1023
int reg = PIPECONF(cpu_transcoder);
1025
/* Wait for the Pipe State to go off */
1026
if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1028
WARN(1, "pipe_off wait timed out\n");
1030
u32 last_line, line_mask;
1031
int reg = PIPEDSL(pipe);
1032
unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
line_mask = DSL_LINEMASK_GEN2;
1037
line_mask = DSL_LINEMASK_GEN3;
1039
/* Wait for the display line to settle */
1041
last_line = I915_READ(reg) & line_mask;
1043
} while (((I915_READ(reg) & line_mask) != last_line) &&
1044
time_after(timeout, jiffies));
1045
if (time_after(jiffies, timeout))
1046
WARN(1, "pipe_off wait timed out\n");
1050
static const char *state_string(bool enabled)
1052
return enabled ? "on" : "off";
1055
/* Only for pre-ILK configs */
1056
static void assert_pll(struct drm_i915_private *dev_priv,
1057
enum pipe pipe, bool state)
1064
val = I915_READ(reg);
1065
cur_state = !!(val & DPLL_VCO_ENABLE);
1066
WARN(cur_state != state,
1067
"PLL state assertion failure (expected %s, current %s)\n",
1068
state_string(state), state_string(cur_state));
1070
#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1071
#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
static void assert_pch_pll(struct drm_i915_private *dev_priv,
1075
struct intel_pch_pll *pll,
1076
struct intel_crtc *crtc,
1082
if (HAS_PCH_LPT(dev_priv->dev)) {
1083
DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1088
"asserting PCH PLL %s with no PLL\n", state_string(state)))
1091
val = I915_READ(pll->pll_reg);
1092
cur_state = !!(val & DPLL_VCO_ENABLE);
1093
WARN(cur_state != state,
1094
"PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1095
pll->pll_reg, state_string(state), state_string(cur_state), val);
1097
/* Make sure the selected PLL is correctly attached to the transcoder */
1098
if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1101
pch_dpll = I915_READ(PCH_DPLL_SEL);
1102
cur_state = pll->pll_reg == _PCH_DPLL_B;
1103
if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1104
"PLL[%d] not attached to this transcoder %d: %08x\n",
1105
cur_state, crtc->pipe, pch_dpll)) {
1106
cur_state = !!(val >> (4*crtc->pipe + 3));
1107
WARN(cur_state != state,
1108
"PLL[%d] not %s on this transcoder %d: %08x\n",
1109
pll->pll_reg == _PCH_DPLL_B,
1110
state_string(state),
1116
#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1117
#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1119
static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1120
enum pipe pipe, bool state)
1125
enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128
if (IS_HASWELL(dev_priv->dev)) {
1129
/* On Haswell, DDI is used instead of FDI_TX_CTL */
1130
reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1131
val = I915_READ(reg);
1132
cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134
reg = FDI_TX_CTL(pipe);
1135
val = I915_READ(reg);
1136
cur_state = !!(val & FDI_TX_ENABLE);
1138
WARN(cur_state != state,
1139
"FDI TX state assertion failure (expected %s, current %s)\n",
1140
state_string(state), state_string(cur_state));
1142
#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143
#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1145
static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146
enum pipe pipe, bool state)
1152
reg = FDI_RX_CTL(pipe);
1153
val = I915_READ(reg);
1154
cur_state = !!(val & FDI_RX_ENABLE);
1155
WARN(cur_state != state,
1156
"FDI RX state assertion failure (expected %s, current %s)\n",
1157
state_string(state), state_string(cur_state));
1159
#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1160
#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1162
static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1168
/* ILK FDI PLL is always enabled */
1169
if (dev_priv->info->gen == 5)
1172
/* On Haswell, DDI ports are responsible for the FDI PLL setup */
1173
if (IS_HASWELL(dev_priv->dev))
1176
reg = FDI_TX_CTL(pipe);
1177
val = I915_READ(reg);
1178
WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1181
static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1187
reg = FDI_RX_CTL(pipe);
1188
val = I915_READ(reg);
1189
WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1192
static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1195
int pp_reg, lvds_reg;
1197
enum pipe panel_pipe = PIPE_A;
1200
if (HAS_PCH_SPLIT(dev_priv->dev)) {
1201
pp_reg = PCH_PP_CONTROL;
1202
lvds_reg = PCH_LVDS;
1204
pp_reg = PP_CONTROL;
1208
val = I915_READ(pp_reg);
1209
if (!(val & PANEL_POWER_ON) ||
1210
((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1213
if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1214
panel_pipe = PIPE_B;
1216
WARN(panel_pipe == pipe && locked,
1217
"panel assertion failure, pipe %c regs locked\n",
1221
void assert_pipe(struct drm_i915_private *dev_priv,
1222
enum pipe pipe, bool state)
1227
enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1230
/* if we need the pipe A quirk it must be always on */
1231
if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1234
reg = PIPECONF(cpu_transcoder);
1235
val = I915_READ(reg);
1236
cur_state = !!(val & PIPECONF_ENABLE);
1237
WARN(cur_state != state,
1238
"pipe %c assertion failure (expected %s, current %s)\n",
1239
pipe_name(pipe), state_string(state), state_string(cur_state));
1242
static void assert_plane(struct drm_i915_private *dev_priv,
1243
enum plane plane, bool state)
1249
reg = DSPCNTR(plane);
1250
val = I915_READ(reg);
1251
cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1252
WARN(cur_state != state,
1253
"plane %c assertion failure (expected %s, current %s)\n",
1254
plane_name(plane), state_string(state), state_string(cur_state));
1257
#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1258
#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1260
static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1267
/* Planes are fixed to pipes on ILK+ */
1268
if (HAS_PCH_SPLIT(dev_priv->dev)) {
1269
reg = DSPCNTR(pipe);
1270
val = I915_READ(reg);
1271
WARN((val & DISPLAY_PLANE_ENABLE),
1272
"plane %c assertion failure, should be disabled but not\n",
1277
/* Need to check both planes against the pipe */
1278
for (i = 0; i < 2; i++) {
1280
val = I915_READ(reg);
1281
cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1282
DISPPLANE_SEL_PIPE_SHIFT;
1283
WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1284
"plane %c assertion failure, should be off on pipe %c but is still active\n",
1285
plane_name(i), pipe_name(pipe));
1289
static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1294
if (HAS_PCH_LPT(dev_priv->dev)) {
1295
DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1299
val = I915_READ(PCH_DREF_CONTROL);
1300
enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1301
DREF_SUPERSPREAD_SOURCE_MASK));
1302
WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1305
static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1312
reg = TRANSCONF(pipe);
1313
val = I915_READ(reg);
1314
enabled = !!(val & TRANS_ENABLE);
1316
"transcoder assertion failed, should be off on pipe %c but is still active\n",
1320
static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1321
enum pipe pipe, u32 port_sel, u32 val)
1323
if ((val & DP_PORT_EN) == 0)
1326
if (HAS_PCH_CPT(dev_priv->dev)) {
1327
u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1328
u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1329
if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1332
if ((val & DP_PIPE_MASK) != (pipe << 30))
1338
static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1339
enum pipe pipe, u32 val)
1341
if ((val & PORT_ENABLE) == 0)
1344
if (HAS_PCH_CPT(dev_priv->dev)) {
1345
if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348
if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1354
static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1355
enum pipe pipe, u32 val)
1357
if ((val & LVDS_PORT_EN) == 0)
1360
if (HAS_PCH_CPT(dev_priv->dev)) {
1361
if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1364
if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1370
static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1371
enum pipe pipe, u32 val)
1373
if ((val & ADPA_DAC_ENABLE) == 0)
1375
if (HAS_PCH_CPT(dev_priv->dev)) {
1376
if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1379
if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1385
static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1386
enum pipe pipe, int reg, u32 port_sel)
1388
u32 val = I915_READ(reg);
1389
WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1390
"PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1391
reg, pipe_name(pipe));
1393
WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1394
&& (val & DP_PIPEB_SELECT),
1395
"IBX PCH dp port still using transcoder B\n");
1398
static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1399
enum pipe pipe, int reg)
1401
u32 val = I915_READ(reg);
1402
WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1403
"PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1404
reg, pipe_name(pipe));
1406
WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1407
&& (val & SDVO_PIPE_B_SELECT),
1408
"IBX PCH hdmi port still using transcoder B\n");
1411
static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1417
assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1418
assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1419
assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1422
val = I915_READ(reg);
1423
WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1424
"PCH VGA enabled on transcoder %c, should be disabled\n",
1428
val = I915_READ(reg);
1429
WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1430
"PCH LVDS enabled on transcoder %c, should be disabled\n",
1433
assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1434
assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1435
assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1439
* intel_enable_pll - enable a PLL
1440
* @dev_priv: i915 private structure
1441
* @pipe: pipe PLL to enable
1443
* Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1444
* make sure the PLL reg is writable first though, since the panel write
1445
* protect mechanism may be enabled.
1447
* Note! This is for pre-ILK only.
1449
* Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1451
static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1456
/* No really, not for ILK+ */
1457
BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1459
/* PLL is protected by panel, make sure we can write it */
1460
if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1461
assert_panel_unlocked(dev_priv, pipe);
1464
val = I915_READ(reg);
1465
val |= DPLL_VCO_ENABLE;
1467
/* We do this three times for luck */
1468
I915_WRITE(reg, val);
1470
udelay(150); /* wait for warmup */
1471
I915_WRITE(reg, val);
1473
udelay(150); /* wait for warmup */
1474
I915_WRITE(reg, val);
1476
udelay(150); /* wait for warmup */
1480
* intel_disable_pll - disable a PLL
1481
* @dev_priv: i915 private structure
1482
* @pipe: pipe PLL to disable
1484
* Disable the PLL for @pipe, making sure the pipe is off first.
1486
* Note! This is for pre-ILK only.
1488
static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1493
/* Don't disable pipe A or pipe A PLLs if needed */
1494
if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1497
/* Make sure the pipe isn't still relying on us */
1498
assert_pipe_disabled(dev_priv, pipe);
1501
val = I915_READ(reg);
1502
val &= ~DPLL_VCO_ENABLE;
1503
I915_WRITE(reg, val);
1509
intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1510
enum intel_sbi_destination destination)
1512
unsigned long flags;
1515
spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1516
if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) {
1517
DRM_ERROR("timeout waiting for SBI to become ready\n");
1521
I915_WRITE(SBI_ADDR, (reg << 16));
1522
I915_WRITE(SBI_DATA, value);
1524
if (destination == SBI_ICLK)
1525
tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1527
tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1528
I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1530
if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1532
DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1537
spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1541
intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1542
enum intel_sbi_destination destination)
1544
unsigned long flags;
1547
spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1548
if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) {
1549
DRM_ERROR("timeout waiting for SBI to become ready\n");
1553
I915_WRITE(SBI_ADDR, (reg << 16));
1555
if (destination == SBI_ICLK)
1556
value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1558
value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1559
I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1561
if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1563
DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1567
value = I915_READ(SBI_DATA);
1570
spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1575
* ironlake_enable_pch_pll - enable PCH PLL
1576
* @dev_priv: i915 private structure
1577
* @pipe: pipe PLL to enable
1579
* The PCH PLL needs to be enabled before the PCH transcoder, since it
1580
* drives the transcoder clock.
1582
static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1584
struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1585
struct intel_pch_pll *pll;
1589
/* PCH PLLs only available on ILK, SNB and IVB */
1590
BUG_ON(dev_priv->info->gen < 5);
1591
pll = intel_crtc->pch_pll;
1595
if (WARN_ON(pll->refcount == 0))
1598
DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1599
pll->pll_reg, pll->active, pll->on,
1600
intel_crtc->base.base.id);
1602
/* PCH refclock must be enabled first */
1603
assert_pch_refclk_enabled(dev_priv);
1605
if (pll->active++ && pll->on) {
1606
assert_pch_pll_enabled(dev_priv, pll, NULL);
1610
DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1613
val = I915_READ(reg);
1614
val |= DPLL_VCO_ENABLE;
1615
I915_WRITE(reg, val);
1622
static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1624
struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1625
struct intel_pch_pll *pll = intel_crtc->pch_pll;
1629
/* PCH only available on ILK+ */
1630
BUG_ON(dev_priv->info->gen < 5);
1634
if (WARN_ON(pll->refcount == 0))
1637
DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1638
pll->pll_reg, pll->active, pll->on,
1639
intel_crtc->base.base.id);
1641
if (WARN_ON(pll->active == 0)) {
1642
assert_pch_pll_disabled(dev_priv, pll, NULL);
1646
if (--pll->active) {
1647
assert_pch_pll_enabled(dev_priv, pll, NULL);
1651
DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1653
/* Make sure transcoder isn't still depending on us */
1654
assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1657
val = I915_READ(reg);
1658
val &= ~DPLL_VCO_ENABLE;
1659
I915_WRITE(reg, val);
1666
static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1669
struct drm_device *dev = dev_priv->dev;
1670
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1671
uint32_t reg, val, pipeconf_val;
1673
/* PCH only available on ILK+ */
1674
BUG_ON(dev_priv->info->gen < 5);
1676
/* Make sure PCH DPLL is enabled */
1677
assert_pch_pll_enabled(dev_priv,
1678
to_intel_crtc(crtc)->pch_pll,
1679
to_intel_crtc(crtc));
1681
/* FDI must be feeding us bits for PCH ports */
1682
assert_fdi_tx_enabled(dev_priv, pipe);
1683
assert_fdi_rx_enabled(dev_priv, pipe);
1685
if (HAS_PCH_CPT(dev)) {
1686
/* Workaround: Set the timing override bit before enabling the
1687
* pch transcoder. */
1688
reg = TRANS_CHICKEN2(pipe);
1689
val = I915_READ(reg);
1690
val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1691
I915_WRITE(reg, val);
1694
reg = TRANSCONF(pipe);
1695
val = I915_READ(reg);
1696
pipeconf_val = I915_READ(PIPECONF(pipe));
1698
if (HAS_PCH_IBX(dev_priv->dev)) {
1700
* make the BPC in transcoder be consistent with
1701
* that in pipeconf reg.
1703
val &= ~PIPE_BPC_MASK;
1704
val |= pipeconf_val & PIPE_BPC_MASK;
1707
val &= ~TRANS_INTERLACE_MASK;
1708
if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1709
if (HAS_PCH_IBX(dev_priv->dev) &&
1710
intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1711
val |= TRANS_LEGACY_INTERLACED_ILK;
1713
val |= TRANS_INTERLACED;
1715
val |= TRANS_PROGRESSIVE;
1717
I915_WRITE(reg, val | TRANS_ENABLE);
1718
if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1719
DRM_ERROR("failed to enable transcoder %d\n", pipe);
1722
static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1723
enum transcoder cpu_transcoder)
1725
u32 val, pipeconf_val;
1727
/* PCH only available on ILK+ */
1728
BUG_ON(dev_priv->info->gen < 5);
1730
/* FDI must be feeding us bits for PCH ports */
1731
assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1732
assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1734
/* Workaround: set timing override bit. */
1735
val = I915_READ(_TRANSA_CHICKEN2);
1736
val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1737
I915_WRITE(_TRANSA_CHICKEN2, val);
1740
pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1742
if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1743
PIPECONF_INTERLACED_ILK)
1744
val |= TRANS_INTERLACED;
1746
val |= TRANS_PROGRESSIVE;
1748
I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1749
if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1750
DRM_ERROR("Failed to enable PCH transcoder\n");
1753
static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1756
struct drm_device *dev = dev_priv->dev;
1759
/* FDI relies on the transcoder */
1760
assert_fdi_tx_disabled(dev_priv, pipe);
1761
assert_fdi_rx_disabled(dev_priv, pipe);
1763
/* Ports must be off as well */
1764
assert_pch_ports_disabled(dev_priv, pipe);
1766
reg = TRANSCONF(pipe);
1767
val = I915_READ(reg);
1768
val &= ~TRANS_ENABLE;
1769
I915_WRITE(reg, val);
1770
/* wait for PCH transcoder off, transcoder state */
1771
if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1772
DRM_ERROR("failed to disable transcoder %d\n", pipe);
1774
if (!HAS_PCH_IBX(dev)) {
1775
/* Workaround: Clear the timing override chicken bit again. */
1776
reg = TRANS_CHICKEN2(pipe);
1777
val = I915_READ(reg);
1778
val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1779
I915_WRITE(reg, val);
1783
static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1787
val = I915_READ(_TRANSACONF);
1788
val &= ~TRANS_ENABLE;
1789
I915_WRITE(_TRANSACONF, val);
1790
/* wait for PCH transcoder off, transcoder state */
1791
if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1792
DRM_ERROR("Failed to disable PCH transcoder\n");
1794
/* Workaround: clear timing override bit. */
1795
val = I915_READ(_TRANSA_CHICKEN2);
1796
val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1797
I915_WRITE(_TRANSA_CHICKEN2, val);
1801
* intel_enable_pipe - enable a pipe, asserting requirements
1802
* @dev_priv: i915 private structure
1803
* @pipe: pipe to enable
1804
* @pch_port: on ILK+, is this pipe driving a PCH port or not
1806
* Enable @pipe, making sure that various hardware specific requirements
1807
* are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1809
* @pipe should be %PIPE_A or %PIPE_B.
1811
* Will wait until the pipe is actually running (i.e. first vblank) before
1814
static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1817
enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1819
enum transcoder pch_transcoder;
1823
if (IS_HASWELL(dev_priv->dev))
1824
pch_transcoder = TRANSCODER_A;
1826
pch_transcoder = pipe;
1829
* A pipe without a PLL won't actually be able to drive bits from
1830
* a plane. On ILK+ the pipe PLLs are integrated, so we don't
1833
if (!HAS_PCH_SPLIT(dev_priv->dev))
1834
assert_pll_enabled(dev_priv, pipe);
1837
/* if driving the PCH, we need FDI enabled */
1838
assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1839
assert_fdi_tx_pll_enabled(dev_priv, cpu_transcoder);
1841
/* FIXME: assert CPU port conditions for SNB+ */
1844
reg = PIPECONF(cpu_transcoder);
1845
val = I915_READ(reg);
1846
if (val & PIPECONF_ENABLE)
1849
I915_WRITE(reg, val | PIPECONF_ENABLE);
1850
intel_wait_for_vblank(dev_priv->dev, pipe);
1854
* intel_disable_pipe - disable a pipe, asserting requirements
1855
* @dev_priv: i915 private structure
1856
* @pipe: pipe to disable
1858
* Disable @pipe, making sure that various hardware specific requirements
1859
* are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1861
* @pipe should be %PIPE_A or %PIPE_B.
1863
* Will wait until the pipe has shut down before returning.
1865
static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1868
enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1874
* Make sure planes won't keep trying to pump pixels to us,
1875
* or we might hang the display.
1877
assert_planes_disabled(dev_priv, pipe);
1879
/* Don't disable pipe A or pipe A PLLs if needed */
1880
if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1883
reg = PIPECONF(cpu_transcoder);
1884
val = I915_READ(reg);
1885
if ((val & PIPECONF_ENABLE) == 0)
1888
I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1889
intel_wait_for_pipe_off(dev_priv->dev, pipe);
1893
* Plane regs are double buffered, going from enabled->disabled needs a
1894
* trigger in order to latch. The display address reg provides this.
1896
void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1899
if (dev_priv->info->gen >= 4)
1900
I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1902
I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1906
* intel_enable_plane - enable a display plane on a given pipe
1907
* @dev_priv: i915 private structure
1908
* @plane: plane to enable
1909
* @pipe: pipe being fed
1911
* Enable @plane on @pipe, making sure that @pipe is running first.
1913
static void intel_enable_plane(struct drm_i915_private *dev_priv,
1914
enum plane plane, enum pipe pipe)
1919
/* If the pipe isn't enabled, we can't pump pixels and may hang */
1920
assert_pipe_enabled(dev_priv, pipe);
1922
reg = DSPCNTR(plane);
1923
val = I915_READ(reg);
1924
if (val & DISPLAY_PLANE_ENABLE)
1927
I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1928
intel_flush_display_plane(dev_priv, plane);
1929
intel_wait_for_vblank(dev_priv->dev, pipe);
1933
* intel_disable_plane - disable a display plane
1934
* @dev_priv: i915 private structure
1935
* @plane: plane to disable
1936
* @pipe: pipe consuming the data
1938
* Disable @plane; should be an independent operation.
1940
static void intel_disable_plane(struct drm_i915_private *dev_priv,
1941
enum plane plane, enum pipe pipe)
1946
reg = DSPCNTR(plane);
1947
val = I915_READ(reg);
1948
if ((val & DISPLAY_PLANE_ENABLE) == 0)
1951
I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1952
intel_flush_display_plane(dev_priv, plane);
1953
intel_wait_for_vblank(dev_priv->dev, pipe);
1957
intel_pin_and_fence_fb_obj(struct drm_device *dev,
1958
struct drm_i915_gem_object *obj,
1959
struct intel_ring_buffer *pipelined)
1961
struct drm_i915_private *dev_priv = dev->dev_private;
1965
switch (obj->tiling_mode) {
1966
case I915_TILING_NONE:
1967
if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1968
alignment = 128 * 1024;
1969
else if (INTEL_INFO(dev)->gen >= 4)
1970
alignment = 4 * 1024;
1972
alignment = 64 * 1024;
1975
/* pin() will align the object as required by fence */
1979
/* FIXME: Is this true? */
1980
DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1986
dev_priv->mm.interruptible = false;
1987
ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1989
goto err_interruptible;
1991
/* Install a fence for tiled scan-out. Pre-i965 always needs a
1992
* fence, whereas 965+ only requires a fence if using
1993
* framebuffer compression. For simplicity, we always install
1994
* a fence as the cost is not that onerous.
1996
ret = i915_gem_object_get_fence(obj);
2000
i915_gem_object_pin_fence(obj);
2002
dev_priv->mm.interruptible = true;
2006
i915_gem_object_unpin(obj);
2008
dev_priv->mm.interruptible = true;
2012
void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2014
i915_gem_object_unpin_fence(obj);
2015
i915_gem_object_unpin(obj);
2018
/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2019
* is assumed to be a power-of-two. */
2020
unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2024
int tile_rows, tiles;
2028
tiles = *x / (512/bpp);
2031
return tile_rows * pitch * 8 + tiles * 4096;
2034
static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2037
struct drm_device *dev = crtc->dev;
2038
struct drm_i915_private *dev_priv = dev->dev_private;
2039
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2040
struct intel_framebuffer *intel_fb;
2041
struct drm_i915_gem_object *obj;
2042
int plane = intel_crtc->plane;
2043
unsigned long linear_offset;
2052
DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2056
intel_fb = to_intel_framebuffer(fb);
2057
obj = intel_fb->obj;
2059
reg = DSPCNTR(plane);
2060
dspcntr = I915_READ(reg);
2061
/* Mask out pixel format bits in case we change it */
2062
dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2063
switch (fb->pixel_format) {
2065
dspcntr |= DISPPLANE_8BPP;
2067
case DRM_FORMAT_XRGB1555:
2068
case DRM_FORMAT_ARGB1555:
2069
dspcntr |= DISPPLANE_BGRX555;
2071
case DRM_FORMAT_RGB565:
2072
dspcntr |= DISPPLANE_BGRX565;
2074
case DRM_FORMAT_XRGB8888:
2075
case DRM_FORMAT_ARGB8888:
2076
dspcntr |= DISPPLANE_BGRX888;
2078
case DRM_FORMAT_XBGR8888:
2079
case DRM_FORMAT_ABGR8888:
2080
dspcntr |= DISPPLANE_RGBX888;
2082
case DRM_FORMAT_XRGB2101010:
2083
case DRM_FORMAT_ARGB2101010:
2084
dspcntr |= DISPPLANE_BGRX101010;
2086
case DRM_FORMAT_XBGR2101010:
2087
case DRM_FORMAT_ABGR2101010:
2088
dspcntr |= DISPPLANE_RGBX101010;
2091
DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2095
if (INTEL_INFO(dev)->gen >= 4) {
2096
if (obj->tiling_mode != I915_TILING_NONE)
2097
dspcntr |= DISPPLANE_TILED;
2099
dspcntr &= ~DISPPLANE_TILED;
2102
I915_WRITE(reg, dspcntr);
2104
linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2106
if (INTEL_INFO(dev)->gen >= 4) {
2107
intel_crtc->dspaddr_offset =
2108
intel_gen4_compute_offset_xtiled(&x, &y,
2109
fb->bits_per_pixel / 8,
2111
linear_offset -= intel_crtc->dspaddr_offset;
2113
intel_crtc->dspaddr_offset = linear_offset;
2116
DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2117
obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2118
I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2119
if (INTEL_INFO(dev)->gen >= 4) {
2120
I915_MODIFY_DISPBASE(DSPSURF(plane),
2121
obj->gtt_offset + intel_crtc->dspaddr_offset);
2122
I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2123
I915_WRITE(DSPLINOFF(plane), linear_offset);
2125
I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2131
static int ironlake_update_plane(struct drm_crtc *crtc,
2132
struct drm_framebuffer *fb, int x, int y)
2134
struct drm_device *dev = crtc->dev;
2135
struct drm_i915_private *dev_priv = dev->dev_private;
2136
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2137
struct intel_framebuffer *intel_fb;
2138
struct drm_i915_gem_object *obj;
2139
int plane = intel_crtc->plane;
2140
unsigned long linear_offset;
2150
DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2154
intel_fb = to_intel_framebuffer(fb);
2155
obj = intel_fb->obj;
2157
reg = DSPCNTR(plane);
2158
dspcntr = I915_READ(reg);
2159
/* Mask out pixel format bits in case we change it */
2160
dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2161
switch (fb->pixel_format) {
2163
dspcntr |= DISPPLANE_8BPP;
2165
case DRM_FORMAT_RGB565:
2166
dspcntr |= DISPPLANE_BGRX565;
2168
case DRM_FORMAT_XRGB8888:
2169
case DRM_FORMAT_ARGB8888:
2170
dspcntr |= DISPPLANE_BGRX888;
2172
case DRM_FORMAT_XBGR8888:
2173
case DRM_FORMAT_ABGR8888:
2174
dspcntr |= DISPPLANE_RGBX888;
2176
case DRM_FORMAT_XRGB2101010:
2177
case DRM_FORMAT_ARGB2101010:
2178
dspcntr |= DISPPLANE_BGRX101010;
2180
case DRM_FORMAT_XBGR2101010:
2181
case DRM_FORMAT_ABGR2101010:
2182
dspcntr |= DISPPLANE_RGBX101010;
2185
DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2189
if (obj->tiling_mode != I915_TILING_NONE)
2190
dspcntr |= DISPPLANE_TILED;
2192
dspcntr &= ~DISPPLANE_TILED;
2195
dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2197
I915_WRITE(reg, dspcntr);
2199
linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2200
intel_crtc->dspaddr_offset =
2201
intel_gen4_compute_offset_xtiled(&x, &y,
2202
fb->bits_per_pixel / 8,
2204
linear_offset -= intel_crtc->dspaddr_offset;
2206
DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2207
obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2208
I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2209
I915_MODIFY_DISPBASE(DSPSURF(plane),
2210
obj->gtt_offset + intel_crtc->dspaddr_offset);
2211
if (IS_HASWELL(dev)) {
2212
I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2214
I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2215
I915_WRITE(DSPLINOFF(plane), linear_offset);
2222
/* Assume fb object is pinned & idle & fenced and just update base pointers */
2224
intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2225
int x, int y, enum mode_set_atomic state)
2227
struct drm_device *dev = crtc->dev;
2228
struct drm_i915_private *dev_priv = dev->dev_private;
2230
if (dev_priv->display.disable_fbc)
2231
dev_priv->display.disable_fbc(dev);
2232
intel_increase_pllclock(crtc);
2234
return dev_priv->display.update_plane(crtc, fb, x, y);
2238
intel_finish_fb(struct drm_framebuffer *old_fb)
2240
struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2241
struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2242
bool was_interruptible = dev_priv->mm.interruptible;
2245
wait_event(dev_priv->pending_flip_queue,
2246
atomic_read(&dev_priv->mm.wedged) ||
2247
atomic_read(&obj->pending_flip) == 0);
2249
/* Big Hammer, we also need to ensure that any pending
2250
* MI_WAIT_FOR_EVENT inside a user batch buffer on the
2251
* current scanout is retired before unpinning the old
2254
* This should only fail upon a hung GPU, in which case we
2255
* can safely continue.
2257
dev_priv->mm.interruptible = false;
2258
ret = i915_gem_object_finish_gpu(obj);
2259
dev_priv->mm.interruptible = was_interruptible;
2264
static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2266
struct drm_device *dev = crtc->dev;
2267
struct drm_i915_master_private *master_priv;
2268
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2270
if (!dev->primary->master)
2273
master_priv = dev->primary->master->driver_priv;
2274
if (!master_priv->sarea_priv)
2277
switch (intel_crtc->pipe) {
2279
master_priv->sarea_priv->pipeA_x = x;
2280
master_priv->sarea_priv->pipeA_y = y;
2283
master_priv->sarea_priv->pipeB_x = x;
2284
master_priv->sarea_priv->pipeB_y = y;
2292
intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2293
struct drm_framebuffer *fb)
2295
struct drm_device *dev = crtc->dev;
2296
struct drm_i915_private *dev_priv = dev->dev_private;
2297
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2298
struct drm_framebuffer *old_fb;
2303
DRM_ERROR("No FB bound\n");
2307
if(intel_crtc->plane > dev_priv->num_pipe) {
2308
DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2310
dev_priv->num_pipe);
2314
mutex_lock(&dev->struct_mutex);
2315
ret = intel_pin_and_fence_fb_obj(dev,
2316
to_intel_framebuffer(fb)->obj,
2319
mutex_unlock(&dev->struct_mutex);
2320
DRM_ERROR("pin & fence failed\n");
2325
intel_finish_fb(crtc->fb);
2327
ret = dev_priv->display.update_plane(crtc, fb, x, y);
2329
intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2330
mutex_unlock(&dev->struct_mutex);
2331
DRM_ERROR("failed to update base address\n");
2341
intel_wait_for_vblank(dev, intel_crtc->pipe);
2342
intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2345
intel_update_fbc(dev);
2346
mutex_unlock(&dev->struct_mutex);
2348
intel_crtc_update_sarea_pos(crtc, x, y);
2353
static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2355
struct drm_device *dev = crtc->dev;
2356
struct drm_i915_private *dev_priv = dev->dev_private;
2359
DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2360
dpa_ctl = I915_READ(DP_A);
2361
dpa_ctl &= ~DP_PLL_FREQ_MASK;
2363
if (clock < 200000) {
2365
dpa_ctl |= DP_PLL_FREQ_160MHZ;
2366
/* workaround for 160Mhz:
2367
1) program 0x4600c bits 15:0 = 0x8124
2368
2) program 0x46010 bit 0 = 1
2369
3) program 0x46034 bit 24 = 1
2370
4) program 0x64000 bit 14 = 1
2372
temp = I915_READ(0x4600c);
2374
I915_WRITE(0x4600c, temp | 0x8124);
2376
temp = I915_READ(0x46010);
2377
I915_WRITE(0x46010, temp | 1);
2379
temp = I915_READ(0x46034);
2380
I915_WRITE(0x46034, temp | (1 << 24));
2382
dpa_ctl |= DP_PLL_FREQ_270MHZ;
2384
I915_WRITE(DP_A, dpa_ctl);
2390
static void intel_fdi_normal_train(struct drm_crtc *crtc)
2392
struct drm_device *dev = crtc->dev;
2393
struct drm_i915_private *dev_priv = dev->dev_private;
2394
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2395
int pipe = intel_crtc->pipe;
2398
/* enable normal train */
2399
reg = FDI_TX_CTL(pipe);
2400
temp = I915_READ(reg);
2401
if (IS_IVYBRIDGE(dev)) {
2402
temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2403
temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2405
temp &= ~FDI_LINK_TRAIN_NONE;
2406
temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2408
I915_WRITE(reg, temp);
2410
reg = FDI_RX_CTL(pipe);
2411
temp = I915_READ(reg);
2412
if (HAS_PCH_CPT(dev)) {
2413
temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2414
temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2416
temp &= ~FDI_LINK_TRAIN_NONE;
2417
temp |= FDI_LINK_TRAIN_NONE;
2419
I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2421
/* wait one idle pattern time */
2425
/* IVB wants error correction enabled */
2426
if (IS_IVYBRIDGE(dev))
2427
I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2428
FDI_FE_ERRC_ENABLE);
2431
static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2433
struct drm_i915_private *dev_priv = dev->dev_private;
2434
u32 flags = I915_READ(SOUTH_CHICKEN1);
2436
flags |= FDI_PHASE_SYNC_OVR(pipe);
2437
I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2438
flags |= FDI_PHASE_SYNC_EN(pipe);
2439
I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2440
POSTING_READ(SOUTH_CHICKEN1);
2443
static void ivb_modeset_global_resources(struct drm_device *dev)
2445
struct drm_i915_private *dev_priv = dev->dev_private;
2446
struct intel_crtc *pipe_B_crtc =
2447
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2448
struct intel_crtc *pipe_C_crtc =
2449
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2452
/* When everything is off disable fdi C so that we could enable fdi B
2453
* with all lanes. XXX: This misses the case where a pipe is not using
2454
* any pch resources and so doesn't need any fdi lanes. */
2455
if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2456
WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2457
WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2459
temp = I915_READ(SOUTH_CHICKEN1);
2460
temp &= ~FDI_BC_BIFURCATION_SELECT;
2461
DRM_DEBUG_KMS("disabling fdi C rx\n");
2462
I915_WRITE(SOUTH_CHICKEN1, temp);
2466
/* The FDI link training functions for ILK/Ibexpeak. */
2467
static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2469
struct drm_device *dev = crtc->dev;
2470
struct drm_i915_private *dev_priv = dev->dev_private;
2471
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2472
int pipe = intel_crtc->pipe;
2473
int plane = intel_crtc->plane;
2474
u32 reg, temp, tries;
2476
/* FDI needs bits from pipe & plane first */
2477
assert_pipe_enabled(dev_priv, pipe);
2478
assert_plane_enabled(dev_priv, plane);
2480
/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2482
reg = FDI_RX_IMR(pipe);
2483
temp = I915_READ(reg);
2484
temp &= ~FDI_RX_SYMBOL_LOCK;
2485
temp &= ~FDI_RX_BIT_LOCK;
2486
I915_WRITE(reg, temp);
2490
/* enable CPU FDI TX and PCH FDI RX */
2491
reg = FDI_TX_CTL(pipe);
2492
temp = I915_READ(reg);
2494
temp |= (intel_crtc->fdi_lanes - 1) << 19;
2495
temp &= ~FDI_LINK_TRAIN_NONE;
2496
temp |= FDI_LINK_TRAIN_PATTERN_1;
2497
I915_WRITE(reg, temp | FDI_TX_ENABLE);
2499
reg = FDI_RX_CTL(pipe);
2500
temp = I915_READ(reg);
2501
temp &= ~FDI_LINK_TRAIN_NONE;
2502
temp |= FDI_LINK_TRAIN_PATTERN_1;
2503
I915_WRITE(reg, temp | FDI_RX_ENABLE);
2508
/* Ironlake workaround, enable clock pointer after FDI enable*/
2509
I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2510
I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2511
FDI_RX_PHASE_SYNC_POINTER_EN);
2513
reg = FDI_RX_IIR(pipe);
2514
for (tries = 0; tries < 5; tries++) {
2515
temp = I915_READ(reg);
2516
DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2518
if ((temp & FDI_RX_BIT_LOCK)) {
2519
DRM_DEBUG_KMS("FDI train 1 done.\n");
2520
I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2525
DRM_ERROR("FDI train 1 fail!\n");
2528
reg = FDI_TX_CTL(pipe);
2529
temp = I915_READ(reg);
2530
temp &= ~FDI_LINK_TRAIN_NONE;
2531
temp |= FDI_LINK_TRAIN_PATTERN_2;
2532
I915_WRITE(reg, temp);
2534
reg = FDI_RX_CTL(pipe);
2535
temp = I915_READ(reg);
2536
temp &= ~FDI_LINK_TRAIN_NONE;
2537
temp |= FDI_LINK_TRAIN_PATTERN_2;
2538
I915_WRITE(reg, temp);
2543
reg = FDI_RX_IIR(pipe);
2544
for (tries = 0; tries < 5; tries++) {
2545
temp = I915_READ(reg);
2546
DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2548
if (temp & FDI_RX_SYMBOL_LOCK) {
2549
I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2550
DRM_DEBUG_KMS("FDI train 2 done.\n");
2555
DRM_ERROR("FDI train 2 fail!\n");
2557
DRM_DEBUG_KMS("FDI train done\n");
2561
static const int snb_b_fdi_train_param[] = {
2562
FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2563
FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2564
FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2565
FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2568
/* The FDI link training functions for SNB/Cougarpoint. */
2569
static void gen6_fdi_link_train(struct drm_crtc *crtc)
2571
struct drm_device *dev = crtc->dev;
2572
struct drm_i915_private *dev_priv = dev->dev_private;
2573
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2574
int pipe = intel_crtc->pipe;
2575
u32 reg, temp, i, retry;
2577
/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2579
reg = FDI_RX_IMR(pipe);
2580
temp = I915_READ(reg);
2581
temp &= ~FDI_RX_SYMBOL_LOCK;
2582
temp &= ~FDI_RX_BIT_LOCK;
2583
I915_WRITE(reg, temp);
2588
/* enable CPU FDI TX and PCH FDI RX */
2589
reg = FDI_TX_CTL(pipe);
2590
temp = I915_READ(reg);
2592
temp |= (intel_crtc->fdi_lanes - 1) << 19;
2593
temp &= ~FDI_LINK_TRAIN_NONE;
2594
temp |= FDI_LINK_TRAIN_PATTERN_1;
2595
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2597
temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2598
I915_WRITE(reg, temp | FDI_TX_ENABLE);
2600
I915_WRITE(FDI_RX_MISC(pipe),
2601
FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2603
reg = FDI_RX_CTL(pipe);
2604
temp = I915_READ(reg);
2605
if (HAS_PCH_CPT(dev)) {
2606
temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2607
temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2609
temp &= ~FDI_LINK_TRAIN_NONE;
2610
temp |= FDI_LINK_TRAIN_PATTERN_1;
2612
I915_WRITE(reg, temp | FDI_RX_ENABLE);
2617
cpt_phase_pointer_enable(dev, pipe);
2619
for (i = 0; i < 4; i++) {
2620
reg = FDI_TX_CTL(pipe);
2621
temp = I915_READ(reg);
2622
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2623
temp |= snb_b_fdi_train_param[i];
2624
I915_WRITE(reg, temp);
2629
for (retry = 0; retry < 5; retry++) {
2630
reg = FDI_RX_IIR(pipe);
2631
temp = I915_READ(reg);
2632
DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2633
if (temp & FDI_RX_BIT_LOCK) {
2634
I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2635
DRM_DEBUG_KMS("FDI train 1 done.\n");
2644
DRM_ERROR("FDI train 1 fail!\n");
2647
reg = FDI_TX_CTL(pipe);
2648
temp = I915_READ(reg);
2649
temp &= ~FDI_LINK_TRAIN_NONE;
2650
temp |= FDI_LINK_TRAIN_PATTERN_2;
2652
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2654
temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2656
I915_WRITE(reg, temp);
2658
reg = FDI_RX_CTL(pipe);
2659
temp = I915_READ(reg);
2660
if (HAS_PCH_CPT(dev)) {
2661
temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2662
temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2664
temp &= ~FDI_LINK_TRAIN_NONE;
2665
temp |= FDI_LINK_TRAIN_PATTERN_2;
2667
I915_WRITE(reg, temp);
2672
for (i = 0; i < 4; i++) {
2673
reg = FDI_TX_CTL(pipe);
2674
temp = I915_READ(reg);
2675
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2676
temp |= snb_b_fdi_train_param[i];
2677
I915_WRITE(reg, temp);
2682
for (retry = 0; retry < 5; retry++) {
2683
reg = FDI_RX_IIR(pipe);
2684
temp = I915_READ(reg);
2685
DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2686
if (temp & FDI_RX_SYMBOL_LOCK) {
2687
I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2688
DRM_DEBUG_KMS("FDI train 2 done.\n");
2697
DRM_ERROR("FDI train 2 fail!\n");
2699
DRM_DEBUG_KMS("FDI train done.\n");
2702
/* Manual link training for Ivy Bridge A0 parts */
2703
static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2705
struct drm_device *dev = crtc->dev;
2706
struct drm_i915_private *dev_priv = dev->dev_private;
2707
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2708
int pipe = intel_crtc->pipe;
2711
/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2713
reg = FDI_RX_IMR(pipe);
2714
temp = I915_READ(reg);
2715
temp &= ~FDI_RX_SYMBOL_LOCK;
2716
temp &= ~FDI_RX_BIT_LOCK;
2717
I915_WRITE(reg, temp);
2722
DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2723
I915_READ(FDI_RX_IIR(pipe)));
2725
/* enable CPU FDI TX and PCH FDI RX */
2726
reg = FDI_TX_CTL(pipe);
2727
temp = I915_READ(reg);
2729
temp |= (intel_crtc->fdi_lanes - 1) << 19;
2730
temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2731
temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2732
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2733
temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2734
temp |= FDI_COMPOSITE_SYNC;
2735
I915_WRITE(reg, temp | FDI_TX_ENABLE);
2737
I915_WRITE(FDI_RX_MISC(pipe),
2738
FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2740
reg = FDI_RX_CTL(pipe);
2741
temp = I915_READ(reg);
2742
temp &= ~FDI_LINK_TRAIN_AUTO;
2743
temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2744
temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2745
temp |= FDI_COMPOSITE_SYNC;
2746
I915_WRITE(reg, temp | FDI_RX_ENABLE);
2751
cpt_phase_pointer_enable(dev, pipe);
2753
for (i = 0; i < 4; i++) {
2754
reg = FDI_TX_CTL(pipe);
2755
temp = I915_READ(reg);
2756
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2757
temp |= snb_b_fdi_train_param[i];
2758
I915_WRITE(reg, temp);
2763
reg = FDI_RX_IIR(pipe);
2764
temp = I915_READ(reg);
2765
DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2767
if (temp & FDI_RX_BIT_LOCK ||
2768
(I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2769
I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2770
DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2775
DRM_ERROR("FDI train 1 fail!\n");
2778
reg = FDI_TX_CTL(pipe);
2779
temp = I915_READ(reg);
2780
temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2781
temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2782
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2783
temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2784
I915_WRITE(reg, temp);
2786
reg = FDI_RX_CTL(pipe);
2787
temp = I915_READ(reg);
2788
temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2789
temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2790
I915_WRITE(reg, temp);
2795
for (i = 0; i < 4; i++) {
2796
reg = FDI_TX_CTL(pipe);
2797
temp = I915_READ(reg);
2798
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2799
temp |= snb_b_fdi_train_param[i];
2800
I915_WRITE(reg, temp);
2805
reg = FDI_RX_IIR(pipe);
2806
temp = I915_READ(reg);
2807
DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2809
if (temp & FDI_RX_SYMBOL_LOCK) {
2810
I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2811
DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2816
DRM_ERROR("FDI train 2 fail!\n");
2818
DRM_DEBUG_KMS("FDI train done.\n");
2821
static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2823
struct drm_device *dev = intel_crtc->base.dev;
2824
struct drm_i915_private *dev_priv = dev->dev_private;
2825
int pipe = intel_crtc->pipe;
2829
/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2830
reg = FDI_RX_CTL(pipe);
2831
temp = I915_READ(reg);
2832
temp &= ~((0x7 << 19) | (0x7 << 16));
2833
temp |= (intel_crtc->fdi_lanes - 1) << 19;
2834
temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2835
I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2840
/* Switch from Rawclk to PCDclk */
2841
temp = I915_READ(reg);
2842
I915_WRITE(reg, temp | FDI_PCDCLK);
2847
/* On Haswell, the PLL configuration for ports and pipes is handled
2848
* separately, as part of DDI setup */
2849
if (!IS_HASWELL(dev)) {
2850
/* Enable CPU FDI TX PLL, always on for Ironlake */
2851
reg = FDI_TX_CTL(pipe);
2852
temp = I915_READ(reg);
2853
if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2854
I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2862
static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2864
struct drm_device *dev = intel_crtc->base.dev;
2865
struct drm_i915_private *dev_priv = dev->dev_private;
2866
int pipe = intel_crtc->pipe;
2869
/* Switch from PCDclk to Rawclk */
2870
reg = FDI_RX_CTL(pipe);
2871
temp = I915_READ(reg);
2872
I915_WRITE(reg, temp & ~FDI_PCDCLK);
2874
/* Disable CPU FDI TX PLL */
2875
reg = FDI_TX_CTL(pipe);
2876
temp = I915_READ(reg);
2877
I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2882
reg = FDI_RX_CTL(pipe);
2883
temp = I915_READ(reg);
2884
I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2886
/* Wait for the clocks to turn off. */
2891
static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2893
struct drm_i915_private *dev_priv = dev->dev_private;
2894
u32 flags = I915_READ(SOUTH_CHICKEN1);
2896
flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2897
I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2898
flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2899
I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2900
POSTING_READ(SOUTH_CHICKEN1);
2902
static void ironlake_fdi_disable(struct drm_crtc *crtc)
2904
struct drm_device *dev = crtc->dev;
2905
struct drm_i915_private *dev_priv = dev->dev_private;
2906
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2907
int pipe = intel_crtc->pipe;
2910
/* disable CPU FDI tx and PCH FDI rx */
2911
reg = FDI_TX_CTL(pipe);
2912
temp = I915_READ(reg);
2913
I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2916
reg = FDI_RX_CTL(pipe);
2917
temp = I915_READ(reg);
2918
temp &= ~(0x7 << 16);
2919
temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2920
I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2925
/* Ironlake workaround, disable clock pointer after downing FDI */
2926
if (HAS_PCH_IBX(dev)) {
2927
I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2928
} else if (HAS_PCH_CPT(dev)) {
2929
cpt_phase_pointer_disable(dev, pipe);
2932
/* still set train pattern 1 */
2933
reg = FDI_TX_CTL(pipe);
2934
temp = I915_READ(reg);
2935
temp &= ~FDI_LINK_TRAIN_NONE;
2936
temp |= FDI_LINK_TRAIN_PATTERN_1;
2937
I915_WRITE(reg, temp);
2939
reg = FDI_RX_CTL(pipe);
2940
temp = I915_READ(reg);
2941
if (HAS_PCH_CPT(dev)) {
2942
temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2943
temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2945
temp &= ~FDI_LINK_TRAIN_NONE;
2946
temp |= FDI_LINK_TRAIN_PATTERN_1;
2948
/* BPC in FDI rx is consistent with that in PIPECONF */
2949
temp &= ~(0x07 << 16);
2950
temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2951
I915_WRITE(reg, temp);
2957
static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2959
struct drm_device *dev = crtc->dev;
2960
struct drm_i915_private *dev_priv = dev->dev_private;
2961
unsigned long flags;
2964
if (atomic_read(&dev_priv->mm.wedged))
2967
spin_lock_irqsave(&dev->event_lock, flags);
2968
pending = to_intel_crtc(crtc)->unpin_work != NULL;
2969
spin_unlock_irqrestore(&dev->event_lock, flags);
2974
static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2976
struct drm_device *dev = crtc->dev;
2977
struct drm_i915_private *dev_priv = dev->dev_private;
2979
if (crtc->fb == NULL)
2982
wait_event(dev_priv->pending_flip_queue,
2983
!intel_crtc_has_pending_flip(crtc));
2985
mutex_lock(&dev->struct_mutex);
2986
intel_finish_fb(crtc->fb);
2987
mutex_unlock(&dev->struct_mutex);
2990
static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2992
struct drm_device *dev = crtc->dev;
2993
struct intel_encoder *intel_encoder;
2996
* If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2997
* must be driven by its own crtc; no sharing is possible.
2999
for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3000
switch (intel_encoder->type) {
3001
case INTEL_OUTPUT_EDP:
3002
if (!intel_encoder_is_pch_edp(&intel_encoder->base))
3011
static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3013
return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3016
/* Program iCLKIP clock to the desired frequency */
3017
static void lpt_program_iclkip(struct drm_crtc *crtc)
3019
struct drm_device *dev = crtc->dev;
3020
struct drm_i915_private *dev_priv = dev->dev_private;
3021
u32 divsel, phaseinc, auxdiv, phasedir = 0;
3024
/* It is necessary to ungate the pixclk gate prior to programming
3025
* the divisors, and gate it back when it is done.
3027
I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3029
/* Disable SSCCTL */
3030
intel_sbi_write(dev_priv, SBI_SSCCTL6,
3031
intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3035
/* 20MHz is a corner case which is out of range for the 7-bit divisor */
3036
if (crtc->mode.clock == 20000) {
3041
/* The iCLK virtual clock root frequency is in MHz,
3042
* but the crtc->mode.clock in in KHz. To get the divisors,
3043
* it is necessary to divide one by another, so we
3044
* convert the virtual clock precision to KHz here for higher
3047
u32 iclk_virtual_root_freq = 172800 * 1000;
3048
u32 iclk_pi_range = 64;
3049
u32 desired_divisor, msb_divisor_value, pi_value;
3051
desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3052
msb_divisor_value = desired_divisor / iclk_pi_range;
3053
pi_value = desired_divisor % iclk_pi_range;
3056
divsel = msb_divisor_value - 2;
3057
phaseinc = pi_value;
3060
/* This should not happen with any sane values */
3061
WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3062
~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3063
WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3064
~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3066
DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3073
/* Program SSCDIVINTPHASE6 */
3074
temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3075
temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3076
temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3077
temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3078
temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3079
temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3080
temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3081
intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3083
/* Program SSCAUXDIV */
3084
temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3085
temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3086
temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3087
intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3089
/* Enable modulator and associated divider */
3090
temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3091
temp &= ~SBI_SSCCTL_DISABLE;
3092
intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3094
/* Wait for initialization time */
3097
I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3101
* Enable PCH resources required for PCH ports:
3103
* - FDI training & RX/TX
3104
* - update transcoder timings
3105
* - DP transcoding bits
3108
static void ironlake_pch_enable(struct drm_crtc *crtc)
3110
struct drm_device *dev = crtc->dev;
3111
struct drm_i915_private *dev_priv = dev->dev_private;
3112
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3113
int pipe = intel_crtc->pipe;
3116
assert_transcoder_disabled(dev_priv, pipe);
3118
/* Write the TU size bits before fdi link training, so that error
3119
* detection works. */
3120
I915_WRITE(FDI_RX_TUSIZE1(pipe),
3121
I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3123
/* For PCH output, training FDI link */
3124
dev_priv->display.fdi_link_train(crtc);
3126
/* XXX: pch pll's can be enabled any time before we enable the PCH
3127
* transcoder, and we actually should do this to not upset any PCH
3128
* transcoder that already use the clock when we share it.
3130
* Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3131
* unconditionally resets the pll - we need that to have the right LVDS
3132
* enable sequence. */
3133
ironlake_enable_pch_pll(intel_crtc);
3135
if (HAS_PCH_CPT(dev)) {
3138
temp = I915_READ(PCH_DPLL_SEL);
3142
temp |= TRANSA_DPLL_ENABLE;
3143
sel = TRANSA_DPLLB_SEL;
3146
temp |= TRANSB_DPLL_ENABLE;
3147
sel = TRANSB_DPLLB_SEL;
3150
temp |= TRANSC_DPLL_ENABLE;
3151
sel = TRANSC_DPLLB_SEL;
3154
if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3158
I915_WRITE(PCH_DPLL_SEL, temp);
3161
/* set transcoder timing, panel must allow it */
3162
assert_panel_unlocked(dev_priv, pipe);
3163
I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3164
I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3165
I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3167
I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3168
I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3169
I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3170
I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3172
intel_fdi_normal_train(crtc);
3174
/* For PCH DP, enable TRANS_DP_CTL */
3175
if (HAS_PCH_CPT(dev) &&
3176
(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3177
intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3178
u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3179
reg = TRANS_DP_CTL(pipe);
3180
temp = I915_READ(reg);
3181
temp &= ~(TRANS_DP_PORT_SEL_MASK |
3182
TRANS_DP_SYNC_MASK |
3184
temp |= (TRANS_DP_OUTPUT_ENABLE |
3185
TRANS_DP_ENH_FRAMING);
3186
temp |= bpc << 9; /* same format but at 11:9 */
3188
if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3189
temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3190
if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3191
temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3193
switch (intel_trans_dp_port_sel(crtc)) {
3195
temp |= TRANS_DP_PORT_SEL_B;
3198
temp |= TRANS_DP_PORT_SEL_C;
3201
temp |= TRANS_DP_PORT_SEL_D;
3207
I915_WRITE(reg, temp);
3210
ironlake_enable_pch_transcoder(dev_priv, pipe);
3213
static void lpt_pch_enable(struct drm_crtc *crtc)
3215
struct drm_device *dev = crtc->dev;
3216
struct drm_i915_private *dev_priv = dev->dev_private;
3217
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3218
enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3220
assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3222
lpt_program_iclkip(crtc);
3224
/* Set transcoder timing. */
3225
I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3226
I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3227
I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3229
I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3230
I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3231
I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3232
I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3234
lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3237
static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3239
struct intel_pch_pll *pll = intel_crtc->pch_pll;
3244
if (pll->refcount == 0) {
3245
WARN(1, "bad PCH PLL refcount\n");
3250
intel_crtc->pch_pll = NULL;
3253
static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3255
struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3256
struct intel_pch_pll *pll;
3259
pll = intel_crtc->pch_pll;
3261
DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3262
intel_crtc->base.base.id, pll->pll_reg);
3266
if (HAS_PCH_IBX(dev_priv->dev)) {
3267
/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3268
i = intel_crtc->pipe;
3269
pll = &dev_priv->pch_plls[i];
3271
DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3272
intel_crtc->base.base.id, pll->pll_reg);
3277
for (i = 0; i < dev_priv->num_pch_pll; i++) {
3278
pll = &dev_priv->pch_plls[i];
3280
/* Only want to check enabled timings first */
3281
if (pll->refcount == 0)
3284
if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3285
fp == I915_READ(pll->fp0_reg)) {
3286
DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3287
intel_crtc->base.base.id,
3288
pll->pll_reg, pll->refcount, pll->active);
3294
/* Ok no matching timings, maybe there's a free one? */
3295
for (i = 0; i < dev_priv->num_pch_pll; i++) {
3296
pll = &dev_priv->pch_plls[i];
3297
if (pll->refcount == 0) {
3298
DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3299
intel_crtc->base.base.id, pll->pll_reg);
3307
intel_crtc->pch_pll = pll;
3309
DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3310
prepare: /* separate function? */
3311
DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3313
/* Wait for the clocks to stabilize before rewriting the regs */
3314
I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3315
POSTING_READ(pll->pll_reg);
3318
I915_WRITE(pll->fp0_reg, fp);
3319
I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3324
void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3326
struct drm_i915_private *dev_priv = dev->dev_private;
3327
int dslreg = PIPEDSL(pipe);
3330
temp = I915_READ(dslreg);
3332
if (wait_for(I915_READ(dslreg) != temp, 5)) {
3333
if (wait_for(I915_READ(dslreg) != temp, 5))
3334
DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3338
static void ironlake_crtc_enable(struct drm_crtc *crtc)
3340
struct drm_device *dev = crtc->dev;
3341
struct drm_i915_private *dev_priv = dev->dev_private;
3342
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3343
struct intel_encoder *encoder;
3344
int pipe = intel_crtc->pipe;
3345
int plane = intel_crtc->plane;
3349
WARN_ON(!crtc->enabled);
3351
if (intel_crtc->active)
3354
intel_crtc->active = true;
3355
intel_update_watermarks(dev);
3357
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3358
temp = I915_READ(PCH_LVDS);
3359
if ((temp & LVDS_PORT_EN) == 0)
3360
I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3363
is_pch_port = ironlake_crtc_driving_pch(crtc);
3366
/* Note: FDI PLL enabling _must_ be done before we enable the
3367
* cpu pipes, hence this is separate from all the other fdi/pch
3369
ironlake_fdi_pll_enable(intel_crtc);
3371
assert_fdi_tx_disabled(dev_priv, pipe);
3372
assert_fdi_rx_disabled(dev_priv, pipe);
3375
for_each_encoder_on_crtc(dev, crtc, encoder)
3376
if (encoder->pre_enable)
3377
encoder->pre_enable(encoder);
3379
/* Enable panel fitting for LVDS */
3380
if (dev_priv->pch_pf_size &&
3381
(intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3382
intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3383
/* Force use of hard-coded filter coefficients
3384
* as some pre-programmed values are broken,
3387
if (IS_IVYBRIDGE(dev))
3388
I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3389
PF_PIPE_SEL_IVB(pipe));
3391
I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3392
I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3393
I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3397
* On ILK+ LUT must be loaded before the pipe is running but with
3400
intel_crtc_load_lut(crtc);
3402
intel_enable_pipe(dev_priv, pipe, is_pch_port);
3403
intel_enable_plane(dev_priv, plane, pipe);
3406
ironlake_pch_enable(crtc);
3408
mutex_lock(&dev->struct_mutex);
3409
intel_update_fbc(dev);
3410
mutex_unlock(&dev->struct_mutex);
3412
intel_crtc_update_cursor(crtc, true);
3414
for_each_encoder_on_crtc(dev, crtc, encoder)
3415
encoder->enable(encoder);
3417
if (HAS_PCH_CPT(dev))
3418
intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3421
* There seems to be a race in PCH platform hw (at least on some
3422
* outputs) where an enabled pipe still completes any pageflip right
3423
* away (as if the pipe is off) instead of waiting for vblank. As soon
3424
* as the first vblank happend, everything works as expected. Hence just
3425
* wait for one vblank before returning to avoid strange things
3428
intel_wait_for_vblank(dev, intel_crtc->pipe);
3431
static void haswell_crtc_enable(struct drm_crtc *crtc)
3433
struct drm_device *dev = crtc->dev;
3434
struct drm_i915_private *dev_priv = dev->dev_private;
3435
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3436
struct intel_encoder *encoder;
3437
int pipe = intel_crtc->pipe;
3438
int plane = intel_crtc->plane;
3441
WARN_ON(!crtc->enabled);
3443
if (intel_crtc->active)
3446
intel_crtc->active = true;
3447
intel_update_watermarks(dev);
3449
is_pch_port = haswell_crtc_driving_pch(crtc);
3452
dev_priv->display.fdi_link_train(crtc);
3454
for_each_encoder_on_crtc(dev, crtc, encoder)
3455
if (encoder->pre_enable)
3456
encoder->pre_enable(encoder);
3458
intel_ddi_enable_pipe_clock(intel_crtc);
3460
/* Enable panel fitting for eDP */
3461
if (dev_priv->pch_pf_size &&
3462
intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3463
/* Force use of hard-coded filter coefficients
3464
* as some pre-programmed values are broken,
3467
I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3468
PF_PIPE_SEL_IVB(pipe));
3469
I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3470
I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3474
* On ILK+ LUT must be loaded before the pipe is running but with
3477
intel_crtc_load_lut(crtc);
3479
intel_ddi_set_pipe_settings(crtc);
3480
intel_ddi_enable_pipe_func(crtc);
3482
intel_enable_pipe(dev_priv, pipe, is_pch_port);
3483
intel_enable_plane(dev_priv, plane, pipe);
3486
lpt_pch_enable(crtc);
3488
mutex_lock(&dev->struct_mutex);
3489
intel_update_fbc(dev);
3490
mutex_unlock(&dev->struct_mutex);
3492
intel_crtc_update_cursor(crtc, true);
3494
for_each_encoder_on_crtc(dev, crtc, encoder)
3495
encoder->enable(encoder);
3498
* There seems to be a race in PCH platform hw (at least on some
3499
* outputs) where an enabled pipe still completes any pageflip right
3500
* away (as if the pipe is off) instead of waiting for vblank. As soon
3501
* as the first vblank happend, everything works as expected. Hence just
3502
* wait for one vblank before returning to avoid strange things
3505
intel_wait_for_vblank(dev, intel_crtc->pipe);
3508
static void ironlake_crtc_disable(struct drm_crtc *crtc)
3510
struct drm_device *dev = crtc->dev;
3511
struct drm_i915_private *dev_priv = dev->dev_private;
3512
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3513
struct intel_encoder *encoder;
3514
int pipe = intel_crtc->pipe;
3515
int plane = intel_crtc->plane;
3519
if (!intel_crtc->active)
3522
for_each_encoder_on_crtc(dev, crtc, encoder)
3523
encoder->disable(encoder);
3525
intel_crtc_wait_for_pending_flips(crtc);
3526
drm_vblank_off(dev, pipe);
3527
intel_crtc_update_cursor(crtc, false);
3529
intel_disable_plane(dev_priv, plane, pipe);
3531
if (dev_priv->cfb_plane == plane)
3532
intel_disable_fbc(dev);
3534
intel_disable_pipe(dev_priv, pipe);
3537
I915_WRITE(PF_CTL(pipe), 0);
3538
I915_WRITE(PF_WIN_SZ(pipe), 0);
3540
for_each_encoder_on_crtc(dev, crtc, encoder)
3541
if (encoder->post_disable)
3542
encoder->post_disable(encoder);
3544
ironlake_fdi_disable(crtc);
3546
ironlake_disable_pch_transcoder(dev_priv, pipe);
3548
if (HAS_PCH_CPT(dev)) {
3549
/* disable TRANS_DP_CTL */
3550
reg = TRANS_DP_CTL(pipe);
3551
temp = I915_READ(reg);
3552
temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3553
temp |= TRANS_DP_PORT_SEL_NONE;
3554
I915_WRITE(reg, temp);
3556
/* disable DPLL_SEL */
3557
temp = I915_READ(PCH_DPLL_SEL);
3560
temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3563
temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3566
/* C shares PLL A or B */
3567
temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3572
I915_WRITE(PCH_DPLL_SEL, temp);
3575
/* disable PCH DPLL */
3576
intel_disable_pch_pll(intel_crtc);
3578
ironlake_fdi_pll_disable(intel_crtc);
3580
intel_crtc->active = false;
3581
intel_update_watermarks(dev);
3583
mutex_lock(&dev->struct_mutex);
3584
intel_update_fbc(dev);
3585
mutex_unlock(&dev->struct_mutex);
3588
static void haswell_crtc_disable(struct drm_crtc *crtc)
3590
struct drm_device *dev = crtc->dev;
3591
struct drm_i915_private *dev_priv = dev->dev_private;
3592
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3593
struct intel_encoder *encoder;
3594
int pipe = intel_crtc->pipe;
3595
int plane = intel_crtc->plane;
3596
enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3599
if (!intel_crtc->active)
3602
is_pch_port = haswell_crtc_driving_pch(crtc);
3604
for_each_encoder_on_crtc(dev, crtc, encoder)
3605
encoder->disable(encoder);
3607
intel_crtc_wait_for_pending_flips(crtc);
3608
drm_vblank_off(dev, pipe);
3609
intel_crtc_update_cursor(crtc, false);
3611
intel_disable_plane(dev_priv, plane, pipe);
3613
if (dev_priv->cfb_plane == plane)
3614
intel_disable_fbc(dev);
3616
intel_disable_pipe(dev_priv, pipe);
3618
intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3621
I915_WRITE(PF_CTL(pipe), 0);
3622
I915_WRITE(PF_WIN_SZ(pipe), 0);
3624
intel_ddi_disable_pipe_clock(intel_crtc);
3626
for_each_encoder_on_crtc(dev, crtc, encoder)
3627
if (encoder->post_disable)
3628
encoder->post_disable(encoder);
3631
lpt_disable_pch_transcoder(dev_priv);
3632
intel_ddi_fdi_disable(crtc);
3635
intel_crtc->active = false;
3636
intel_update_watermarks(dev);
3638
mutex_lock(&dev->struct_mutex);
3639
intel_update_fbc(dev);
3640
mutex_unlock(&dev->struct_mutex);
3643
static void ironlake_crtc_off(struct drm_crtc *crtc)
3645
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3646
intel_put_pch_pll(intel_crtc);
3649
static void haswell_crtc_off(struct drm_crtc *crtc)
3651
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3653
/* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3654
* start using it. */
3655
intel_crtc->cpu_transcoder = intel_crtc->pipe;
3657
intel_ddi_put_crtc_pll(crtc);
3660
static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3662
if (!enable && intel_crtc->overlay) {
3663
struct drm_device *dev = intel_crtc->base.dev;
3664
struct drm_i915_private *dev_priv = dev->dev_private;
3666
mutex_lock(&dev->struct_mutex);
3667
dev_priv->mm.interruptible = false;
3668
(void) intel_overlay_switch_off(intel_crtc->overlay);
3669
dev_priv->mm.interruptible = true;
3670
mutex_unlock(&dev->struct_mutex);
3673
/* Let userspace switch the overlay on again. In most cases userspace
3674
* has to recompute where to put it anyway.
3678
static void i9xx_crtc_enable(struct drm_crtc *crtc)
3680
struct drm_device *dev = crtc->dev;
3681
struct drm_i915_private *dev_priv = dev->dev_private;
3682
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3683
struct intel_encoder *encoder;
3684
int pipe = intel_crtc->pipe;
3685
int plane = intel_crtc->plane;
3687
WARN_ON(!crtc->enabled);
3689
if (intel_crtc->active)
3692
intel_crtc->active = true;
3693
intel_update_watermarks(dev);
3695
intel_enable_pll(dev_priv, pipe);
3696
intel_enable_pipe(dev_priv, pipe, false);
3697
intel_enable_plane(dev_priv, plane, pipe);
3699
intel_crtc_load_lut(crtc);
3700
intel_update_fbc(dev);
3702
/* Give the overlay scaler a chance to enable if it's on this pipe */
3703
intel_crtc_dpms_overlay(intel_crtc, true);
3704
intel_crtc_update_cursor(crtc, true);
3706
for_each_encoder_on_crtc(dev, crtc, encoder)
3707
encoder->enable(encoder);
3710
static void i9xx_crtc_disable(struct drm_crtc *crtc)
3712
struct drm_device *dev = crtc->dev;
3713
struct drm_i915_private *dev_priv = dev->dev_private;
3714
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3715
struct intel_encoder *encoder;
3716
int pipe = intel_crtc->pipe;
3717
int plane = intel_crtc->plane;
3720
if (!intel_crtc->active)
3723
for_each_encoder_on_crtc(dev, crtc, encoder)
3724
encoder->disable(encoder);
3726
/* Give the overlay scaler a chance to disable if it's on this pipe */
3727
intel_crtc_wait_for_pending_flips(crtc);
3728
drm_vblank_off(dev, pipe);
3729
intel_crtc_dpms_overlay(intel_crtc, false);
3730
intel_crtc_update_cursor(crtc, false);
3732
if (dev_priv->cfb_plane == plane)
3733
intel_disable_fbc(dev);
3735
intel_disable_plane(dev_priv, plane, pipe);
3736
intel_disable_pipe(dev_priv, pipe);
3737
intel_disable_pll(dev_priv, pipe);
3739
intel_crtc->active = false;
3740
intel_update_fbc(dev);
3741
intel_update_watermarks(dev);
3744
static void i9xx_crtc_off(struct drm_crtc *crtc)
3748
static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3751
struct drm_device *dev = crtc->dev;
3752
struct drm_i915_master_private *master_priv;
3753
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3754
int pipe = intel_crtc->pipe;
3756
if (!dev->primary->master)
3759
master_priv = dev->primary->master->driver_priv;
3760
if (!master_priv->sarea_priv)
3765
master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3766
master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3769
master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3770
master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3773
DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3779
* Sets the power management mode of the pipe and plane.
3781
void intel_crtc_update_dpms(struct drm_crtc *crtc)
3783
struct drm_device *dev = crtc->dev;
3784
struct drm_i915_private *dev_priv = dev->dev_private;
3785
struct intel_encoder *intel_encoder;
3786
bool enable = false;
3788
for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3789
enable |= intel_encoder->connectors_active;
3792
dev_priv->display.crtc_enable(crtc);
3794
dev_priv->display.crtc_disable(crtc);
3796
intel_crtc_update_sarea(crtc, enable);
3799
static void intel_crtc_noop(struct drm_crtc *crtc)
3803
static void intel_crtc_disable(struct drm_crtc *crtc)
3805
struct drm_device *dev = crtc->dev;
3806
struct drm_connector *connector;
3807
struct drm_i915_private *dev_priv = dev->dev_private;
3809
/* crtc should still be enabled when we disable it. */
3810
WARN_ON(!crtc->enabled);
3812
dev_priv->display.crtc_disable(crtc);
3813
intel_crtc_update_sarea(crtc, false);
3814
dev_priv->display.off(crtc);
3816
assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3817
assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3820
mutex_lock(&dev->struct_mutex);
3821
intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3822
mutex_unlock(&dev->struct_mutex);
3826
/* Update computed state. */
3827
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3828
if (!connector->encoder || !connector->encoder->crtc)
3831
if (connector->encoder->crtc != crtc)
3834
connector->dpms = DRM_MODE_DPMS_OFF;
3835
to_intel_encoder(connector->encoder)->connectors_active = false;
3839
void intel_modeset_disable(struct drm_device *dev)
3841
struct drm_crtc *crtc;
3843
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3845
intel_crtc_disable(crtc);
3849
void intel_encoder_noop(struct drm_encoder *encoder)
3853
void intel_encoder_destroy(struct drm_encoder *encoder)
3855
struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3857
drm_encoder_cleanup(encoder);
3858
kfree(intel_encoder);
3861
/* Simple dpms helper for encodres with just one connector, no cloning and only
3862
* one kind of off state. It clamps all !ON modes to fully OFF and changes the
3863
* state of the entire output pipe. */
3864
void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3866
if (mode == DRM_MODE_DPMS_ON) {
3867
encoder->connectors_active = true;
3869
intel_crtc_update_dpms(encoder->base.crtc);
3871
encoder->connectors_active = false;
3873
intel_crtc_update_dpms(encoder->base.crtc);
3877
/* Cross check the actual hw state with our own modeset state tracking (and it's
3878
* internal consistency). */
3879
static void intel_connector_check_state(struct intel_connector *connector)
3881
if (connector->get_hw_state(connector)) {
3882
struct intel_encoder *encoder = connector->encoder;
3883
struct drm_crtc *crtc;
3884
bool encoder_enabled;
3887
DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3888
connector->base.base.id,
3889
drm_get_connector_name(&connector->base));
3891
WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3892
"wrong connector dpms state\n");
3893
WARN(connector->base.encoder != &encoder->base,
3894
"active connector not linked to encoder\n");
3895
WARN(!encoder->connectors_active,
3896
"encoder->connectors_active not set\n");
3898
encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3899
WARN(!encoder_enabled, "encoder not enabled\n");
3900
if (WARN_ON(!encoder->base.crtc))
3903
crtc = encoder->base.crtc;
3905
WARN(!crtc->enabled, "crtc not enabled\n");
3906
WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3907
WARN(pipe != to_intel_crtc(crtc)->pipe,
3908
"encoder active on the wrong pipe\n");
3912
/* Even simpler default implementation, if there's really no special case to
3914
void intel_connector_dpms(struct drm_connector *connector, int mode)
3916
struct intel_encoder *encoder = intel_attached_encoder(connector);
3918
/* All the simple cases only support two dpms states. */
3919
if (mode != DRM_MODE_DPMS_ON)
3920
mode = DRM_MODE_DPMS_OFF;
3922
if (mode == connector->dpms)
3925
connector->dpms = mode;
3927
/* Only need to change hw state when actually enabled */
3928
if (encoder->base.crtc)
3929
intel_encoder_dpms(encoder, mode);
3931
WARN_ON(encoder->connectors_active != false);
3933
intel_modeset_check_state(connector->dev);
3936
/* Simple connector->get_hw_state implementation for encoders that support only
3937
* one connector and no cloning and hence the encoder state determines the state
3938
* of the connector. */
3939
bool intel_connector_get_hw_state(struct intel_connector *connector)
3942
struct intel_encoder *encoder = connector->encoder;
3944
return encoder->get_hw_state(encoder, &pipe);
3947
static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3948
const struct drm_display_mode *mode,
3949
struct drm_display_mode *adjusted_mode)
3951
struct drm_device *dev = crtc->dev;
3953
if (HAS_PCH_SPLIT(dev)) {
3954
/* FDI link clock is fixed at 2.7G */
3955
if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3959
/* All interlaced capable intel hw wants timings in frames. Note though
3960
* that intel_lvds_mode_fixup does some funny tricks with the crtc
3961
* timings, so we need to be careful not to clobber these.*/
3962
if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3963
drm_mode_set_crtcinfo(adjusted_mode, 0);
3965
/* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3966
* with a hsync front porch of 0.
3968
if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3969
adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3975
static int valleyview_get_display_clock_speed(struct drm_device *dev)
3977
return 400000; /* FIXME */
3980
static int i945_get_display_clock_speed(struct drm_device *dev)
3985
static int i915_get_display_clock_speed(struct drm_device *dev)
3990
static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3995
static int i915gm_get_display_clock_speed(struct drm_device *dev)
3999
pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4001
if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4004
switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4005
case GC_DISPLAY_CLOCK_333_MHZ:
4008
case GC_DISPLAY_CLOCK_190_200_MHZ:
4014
static int i865_get_display_clock_speed(struct drm_device *dev)
4019
static int i855_get_display_clock_speed(struct drm_device *dev)
4022
/* Assume that the hardware is in the high speed state. This
4023
* should be the default.
4025
switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4026
case GC_CLOCK_133_200:
4027
case GC_CLOCK_100_200:
4029
case GC_CLOCK_166_250:
4031
case GC_CLOCK_100_133:
4035
/* Shouldn't happen */
4039
static int i830_get_display_clock_speed(struct drm_device *dev)
4053
fdi_reduce_ratio(u32 *num, u32 *den)
4055
while (*num > 0xffffff || *den > 0xffffff) {
4062
ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4063
int link_clock, struct fdi_m_n *m_n)
4065
m_n->tu = 64; /* default size */
4067
/* BUG_ON(pixel_clock > INT_MAX / 36); */
4068
m_n->gmch_m = bits_per_pixel * pixel_clock;
4069
m_n->gmch_n = link_clock * nlanes * 8;
4070
fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4072
m_n->link_m = pixel_clock;
4073
m_n->link_n = link_clock;
4074
fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4077
static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4079
if (i915_panel_use_ssc >= 0)
4080
return i915_panel_use_ssc != 0;
4081
return dev_priv->lvds_use_ssc
4082
&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4086
* intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4087
* @crtc: CRTC structure
4088
* @mode: requested mode
4090
* A pipe may be connected to one or more outputs. Based on the depth of the
4091
* attached framebuffer, choose a good color depth to use on the pipe.
4093
* If possible, match the pipe depth to the fb depth. In some cases, this
4094
* isn't ideal, because the connected output supports a lesser or restricted
4095
* set of depths. Resolve that here:
4096
* LVDS typically supports only 6bpc, so clamp down in that case
4097
* HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4098
* Displays may support a restricted set as well, check EDID and clamp as
4100
* DP may want to dither down to 6bpc to fit larger modes
4103
* Dithering requirement (i.e. false if display bpc and pipe bpc match,
4104
* true if they don't match).
4106
static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4107
struct drm_framebuffer *fb,
4108
unsigned int *pipe_bpp,
4109
struct drm_display_mode *mode)
4111
struct drm_device *dev = crtc->dev;
4112
struct drm_i915_private *dev_priv = dev->dev_private;
4113
struct drm_connector *connector;
4114
struct intel_encoder *intel_encoder;
4115
unsigned int display_bpc = UINT_MAX, bpc;
4117
/* Walk the encoders & connectors on this crtc, get min bpc */
4118
for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4120
if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4121
unsigned int lvds_bpc;
4123
if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4129
if (lvds_bpc < display_bpc) {
4130
DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4131
display_bpc = lvds_bpc;
4136
/* Not one of the known troublemakers, check the EDID */
4137
list_for_each_entry(connector, &dev->mode_config.connector_list,
4139
if (connector->encoder != &intel_encoder->base)
4142
/* Don't use an invalid EDID bpc value */
4143
if (connector->display_info.bpc &&
4144
connector->display_info.bpc < display_bpc) {
4145
DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4146
display_bpc = connector->display_info.bpc;
4150
if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4151
/* Use VBT settings if we have an eDP panel */
4152
unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4154
if (edp_bpc && edp_bpc < display_bpc) {
4155
DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4156
display_bpc = edp_bpc;
4162
* HDMI is either 12 or 8, so if the display lets 10bpc sneak
4163
* through, clamp it down. (Note: >12bpc will be caught below.)
4165
if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4166
if (display_bpc > 8 && display_bpc < 12) {
4167
DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4170
DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4176
if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4177
DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4182
* We could just drive the pipe at the highest bpc all the time and
4183
* enable dithering as needed, but that costs bandwidth. So choose
4184
* the minimum value that expresses the full color range of the fb but
4185
* also stays within the max display bpc discovered above.
4188
switch (fb->depth) {
4190
bpc = 8; /* since we go through a colormap */
4194
bpc = 6; /* min is 18bpp */
4206
DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4207
bpc = min((unsigned int)8, display_bpc);
4211
display_bpc = min(display_bpc, bpc);
4213
DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4216
*pipe_bpp = display_bpc * 3;
4218
return display_bpc != bpc;
4221
static int vlv_get_refclk(struct drm_crtc *crtc)
4223
struct drm_device *dev = crtc->dev;
4224
struct drm_i915_private *dev_priv = dev->dev_private;
4225
int refclk = 27000; /* for DP & HDMI */
4227
return 100000; /* only one validated so far */
4229
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4231
} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4232
if (intel_panel_use_ssc(dev_priv))
4236
} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4243
static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4245
struct drm_device *dev = crtc->dev;
4246
struct drm_i915_private *dev_priv = dev->dev_private;
4249
if (IS_VALLEYVIEW(dev)) {
4250
refclk = vlv_get_refclk(crtc);
4251
} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4252
intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4253
refclk = dev_priv->lvds_ssc_freq * 1000;
4254
DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4256
} else if (!IS_GEN2(dev)) {
4265
static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4266
intel_clock_t *clock)
4268
/* SDVO TV has fixed PLL values depend on its clock range,
4269
this mirrors vbios setting. */
4270
if (adjusted_mode->clock >= 100000
4271
&& adjusted_mode->clock < 140500) {
4277
} else if (adjusted_mode->clock >= 140500
4278
&& adjusted_mode->clock <= 200000) {
4287
static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4288
intel_clock_t *clock,
4289
intel_clock_t *reduced_clock)
4291
struct drm_device *dev = crtc->dev;
4292
struct drm_i915_private *dev_priv = dev->dev_private;
4293
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4294
int pipe = intel_crtc->pipe;
4297
if (IS_PINEVIEW(dev)) {
4298
fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4300
fp2 = (1 << reduced_clock->n) << 16 |
4301
reduced_clock->m1 << 8 | reduced_clock->m2;
4303
fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4305
fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4309
I915_WRITE(FP0(pipe), fp);
4311
intel_crtc->lowfreq_avail = false;
4312
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4313
reduced_clock && i915_powersave) {
4314
I915_WRITE(FP1(pipe), fp2);
4315
intel_crtc->lowfreq_avail = true;
4317
I915_WRITE(FP1(pipe), fp);
4321
static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4322
struct drm_display_mode *adjusted_mode)
4324
struct drm_device *dev = crtc->dev;
4325
struct drm_i915_private *dev_priv = dev->dev_private;
4326
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4327
int pipe = intel_crtc->pipe;
4330
temp = I915_READ(LVDS);
4331
temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4333
temp |= LVDS_PIPEB_SELECT;
4335
temp &= ~LVDS_PIPEB_SELECT;
4337
/* set the corresponsding LVDS_BORDER bit */
4338
temp |= dev_priv->lvds_border_bits;
4339
/* Set the B0-B3 data pairs corresponding to whether we're going to
4340
* set the DPLLs for dual-channel mode or not.
4343
temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4345
temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4347
/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4348
* appropriately here, but we need to look more thoroughly into how
4349
* panels behave in the two modes.
4351
/* set the dithering flag on LVDS as needed */
4352
if (INTEL_INFO(dev)->gen >= 4) {
4353
if (dev_priv->lvds_dither)
4354
temp |= LVDS_ENABLE_DITHER;
4356
temp &= ~LVDS_ENABLE_DITHER;
4358
temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4359
if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4360
temp |= LVDS_HSYNC_POLARITY;
4361
if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4362
temp |= LVDS_VSYNC_POLARITY;
4363
I915_WRITE(LVDS, temp);
4366
static void vlv_update_pll(struct drm_crtc *crtc,
4367
struct drm_display_mode *mode,
4368
struct drm_display_mode *adjusted_mode,
4369
intel_clock_t *clock, intel_clock_t *reduced_clock,
4372
struct drm_device *dev = crtc->dev;
4373
struct drm_i915_private *dev_priv = dev->dev_private;
4374
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4375
int pipe = intel_crtc->pipe;
4376
u32 dpll, mdiv, pdiv;
4377
u32 bestn, bestm1, bestm2, bestp1, bestp2;
4381
is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4382
intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4384
dpll = DPLL_VGA_MODE_DIS;
4385
dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4386
dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4387
dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4389
I915_WRITE(DPLL(pipe), dpll);
4390
POSTING_READ(DPLL(pipe));
4399
* In Valleyview PLL and program lane counter registers are exposed
4400
* through DPIO interface
4402
mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4403
mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4404
mdiv |= ((bestn << DPIO_N_SHIFT));
4405
mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4406
mdiv |= (1 << DPIO_K_SHIFT);
4407
mdiv |= DPIO_ENABLE_CALIBRATION;
4408
intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4410
intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4412
pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4413
(3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4414
(7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4415
(5 << DPIO_CLK_BIAS_CTL_SHIFT);
4416
intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4418
intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4420
dpll |= DPLL_VCO_ENABLE;
4421
I915_WRITE(DPLL(pipe), dpll);
4422
POSTING_READ(DPLL(pipe));
4423
if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4424
DRM_ERROR("DPLL %d failed to lock\n", pipe);
4426
intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4428
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4429
intel_dp_set_m_n(crtc, mode, adjusted_mode);
4431
I915_WRITE(DPLL(pipe), dpll);
4433
/* Wait for the clocks to stabilize. */
4434
POSTING_READ(DPLL(pipe));
4439
temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4441
temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4445
I915_WRITE(DPLL_MD(pipe), temp);
4446
POSTING_READ(DPLL_MD(pipe));
4448
/* Now program lane control registers */
4449
if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4450
|| intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4455
intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4457
if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4462
intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4466
static void i9xx_update_pll(struct drm_crtc *crtc,
4467
struct drm_display_mode *mode,
4468
struct drm_display_mode *adjusted_mode,
4469
intel_clock_t *clock, intel_clock_t *reduced_clock,
4472
struct drm_device *dev = crtc->dev;
4473
struct drm_i915_private *dev_priv = dev->dev_private;
4474
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4475
int pipe = intel_crtc->pipe;
4479
i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4481
is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4482
intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4484
dpll = DPLL_VGA_MODE_DIS;
4486
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4487
dpll |= DPLLB_MODE_LVDS;
4489
dpll |= DPLLB_MODE_DAC_SERIAL;
4491
int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4492
if (pixel_multiplier > 1) {
4493
if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4494
dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4496
dpll |= DPLL_DVO_HIGH_SPEED;
4498
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4499
dpll |= DPLL_DVO_HIGH_SPEED;
4501
/* compute bitmask from p1 value */
4502
if (IS_PINEVIEW(dev))
4503
dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4505
dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4506
if (IS_G4X(dev) && reduced_clock)
4507
dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4509
switch (clock->p2) {
4511
dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4514
dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4517
dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4520
dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4523
if (INTEL_INFO(dev)->gen >= 4)
4524
dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4526
if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4527
dpll |= PLL_REF_INPUT_TVCLKINBC;
4528
else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4529
/* XXX: just matching BIOS for now */
4530
/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4532
else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4533
intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4534
dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4536
dpll |= PLL_REF_INPUT_DREFCLK;
4538
dpll |= DPLL_VCO_ENABLE;
4539
I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4540
POSTING_READ(DPLL(pipe));
4543
/* The LVDS pin pair needs to be on before the DPLLs are enabled.
4544
* This is an exception to the general rule that mode_set doesn't turn
4547
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4548
intel_update_lvds(crtc, clock, adjusted_mode);
4550
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4551
intel_dp_set_m_n(crtc, mode, adjusted_mode);
4553
I915_WRITE(DPLL(pipe), dpll);
4555
/* Wait for the clocks to stabilize. */
4556
POSTING_READ(DPLL(pipe));
4559
if (INTEL_INFO(dev)->gen >= 4) {
4562
temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4564
temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4568
I915_WRITE(DPLL_MD(pipe), temp);
4570
/* The pixel multiplier can only be updated once the
4571
* DPLL is enabled and the clocks are stable.
4573
* So write it again.
4575
I915_WRITE(DPLL(pipe), dpll);
4579
static void i8xx_update_pll(struct drm_crtc *crtc,
4580
struct drm_display_mode *adjusted_mode,
4581
intel_clock_t *clock, intel_clock_t *reduced_clock,
4584
struct drm_device *dev = crtc->dev;
4585
struct drm_i915_private *dev_priv = dev->dev_private;
4586
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4587
int pipe = intel_crtc->pipe;
4590
i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4592
dpll = DPLL_VGA_MODE_DIS;
4594
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4595
dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4598
dpll |= PLL_P1_DIVIDE_BY_TWO;
4600
dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4602
dpll |= PLL_P2_DIVIDE_BY_4;
4605
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4606
/* XXX: just matching BIOS for now */
4607
/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4609
else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4610
intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4611
dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4613
dpll |= PLL_REF_INPUT_DREFCLK;
4615
dpll |= DPLL_VCO_ENABLE;
4616
I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4617
POSTING_READ(DPLL(pipe));
4620
/* The LVDS pin pair needs to be on before the DPLLs are enabled.
4621
* This is an exception to the general rule that mode_set doesn't turn
4624
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4625
intel_update_lvds(crtc, clock, adjusted_mode);
4627
I915_WRITE(DPLL(pipe), dpll);
4629
/* Wait for the clocks to stabilize. */
4630
POSTING_READ(DPLL(pipe));
4633
/* The pixel multiplier can only be updated once the
4634
* DPLL is enabled and the clocks are stable.
4636
* So write it again.
4638
I915_WRITE(DPLL(pipe), dpll);
4641
static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4642
struct drm_display_mode *mode,
4643
struct drm_display_mode *adjusted_mode)
4645
struct drm_device *dev = intel_crtc->base.dev;
4646
struct drm_i915_private *dev_priv = dev->dev_private;
4647
enum pipe pipe = intel_crtc->pipe;
4648
enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4649
uint32_t vsyncshift;
4651
if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4652
/* the chip adds 2 halflines automatically */
4653
adjusted_mode->crtc_vtotal -= 1;
4654
adjusted_mode->crtc_vblank_end -= 1;
4655
vsyncshift = adjusted_mode->crtc_hsync_start
4656
- adjusted_mode->crtc_htotal / 2;
4661
if (INTEL_INFO(dev)->gen > 3)
4662
I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4664
I915_WRITE(HTOTAL(cpu_transcoder),
4665
(adjusted_mode->crtc_hdisplay - 1) |
4666
((adjusted_mode->crtc_htotal - 1) << 16));
4667
I915_WRITE(HBLANK(cpu_transcoder),
4668
(adjusted_mode->crtc_hblank_start - 1) |
4669
((adjusted_mode->crtc_hblank_end - 1) << 16));
4670
I915_WRITE(HSYNC(cpu_transcoder),
4671
(adjusted_mode->crtc_hsync_start - 1) |
4672
((adjusted_mode->crtc_hsync_end - 1) << 16));
4674
I915_WRITE(VTOTAL(cpu_transcoder),
4675
(adjusted_mode->crtc_vdisplay - 1) |
4676
((adjusted_mode->crtc_vtotal - 1) << 16));
4677
I915_WRITE(VBLANK(cpu_transcoder),
4678
(adjusted_mode->crtc_vblank_start - 1) |
4679
((adjusted_mode->crtc_vblank_end - 1) << 16));
4680
I915_WRITE(VSYNC(cpu_transcoder),
4681
(adjusted_mode->crtc_vsync_start - 1) |
4682
((adjusted_mode->crtc_vsync_end - 1) << 16));
4684
/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4685
* programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4686
* documented on the DDI_FUNC_CTL register description, EDP Input Select
4688
if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4689
(pipe == PIPE_B || pipe == PIPE_C))
4690
I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4692
/* pipesrc controls the size that is scaled from, which should
4693
* always be the user's requested size.
4695
I915_WRITE(PIPESRC(pipe),
4696
((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4699
static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4700
struct drm_display_mode *mode,
4701
struct drm_display_mode *adjusted_mode,
4703
struct drm_framebuffer *fb)
4705
struct drm_device *dev = crtc->dev;
4706
struct drm_i915_private *dev_priv = dev->dev_private;
4707
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4708
int pipe = intel_crtc->pipe;
4709
int plane = intel_crtc->plane;
4710
int refclk, num_connectors = 0;
4711
intel_clock_t clock, reduced_clock;
4712
u32 dspcntr, pipeconf;
4713
bool ok, has_reduced_clock = false, is_sdvo = false;
4714
bool is_lvds = false, is_tv = false, is_dp = false;
4715
struct intel_encoder *encoder;
4716
const intel_limit_t *limit;
4719
for_each_encoder_on_crtc(dev, crtc, encoder) {
4720
switch (encoder->type) {
4721
case INTEL_OUTPUT_LVDS:
4724
case INTEL_OUTPUT_SDVO:
4725
case INTEL_OUTPUT_HDMI:
4727
if (encoder->needs_tv_clock)
4730
case INTEL_OUTPUT_TVOUT:
4733
case INTEL_OUTPUT_DISPLAYPORT:
4741
refclk = i9xx_get_refclk(crtc, num_connectors);
4744
* Returns a set of divisors for the desired target clock with the given
4745
* refclk, or FALSE. The returned values represent the clock equation:
4746
* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4748
limit = intel_limit(crtc, refclk);
4749
ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4752
DRM_ERROR("Couldn't find PLL settings for mode!\n");
4756
/* Ensure that the cursor is valid for the new mode before changing... */
4757
intel_crtc_update_cursor(crtc, true);
4759
if (is_lvds && dev_priv->lvds_downclock_avail) {
4761
* Ensure we match the reduced clock's P to the target clock.
4762
* If the clocks don't match, we can't switch the display clock
4763
* by using the FP0/FP1. In such case we will disable the LVDS
4764
* downclock feature.
4766
has_reduced_clock = limit->find_pll(limit, crtc,
4767
dev_priv->lvds_downclock,
4773
if (is_sdvo && is_tv)
4774
i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4777
i8xx_update_pll(crtc, adjusted_mode, &clock,
4778
has_reduced_clock ? &reduced_clock : NULL,
4780
else if (IS_VALLEYVIEW(dev))
4781
vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4782
has_reduced_clock ? &reduced_clock : NULL,
4785
i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4786
has_reduced_clock ? &reduced_clock : NULL,
4789
/* setup pipeconf */
4790
pipeconf = I915_READ(PIPECONF(pipe));
4792
/* Set up the display plane register */
4793
dspcntr = DISPPLANE_GAMMA_ENABLE;
4796
dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4798
dspcntr |= DISPPLANE_SEL_PIPE_B;
4800
if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4801
/* Enable pixel doubling when the dot clock is > 90% of the (display)
4804
* XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4808
dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4809
pipeconf |= PIPECONF_DOUBLE_WIDE;
4811
pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4814
/* default to 8bpc */
4815
pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4817
if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4818
pipeconf |= PIPECONF_BPP_6 |
4819
PIPECONF_DITHER_EN |
4820
PIPECONF_DITHER_TYPE_SP;
4824
if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4825
if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4826
pipeconf |= PIPECONF_BPP_6 |
4828
I965_PIPECONF_ACTIVE;
4832
DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4833
drm_mode_debug_printmodeline(mode);
4835
if (HAS_PIPE_CXSR(dev)) {
4836
if (intel_crtc->lowfreq_avail) {
4837
DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4838
pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4840
DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4841
pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4845
pipeconf &= ~PIPECONF_INTERLACE_MASK;
4846
if (!IS_GEN2(dev) &&
4847
adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4848
pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4850
pipeconf |= PIPECONF_PROGRESSIVE;
4852
intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4854
/* pipesrc and dspsize control the size that is scaled from,
4855
* which should always be the user's requested size.
4857
I915_WRITE(DSPSIZE(plane),
4858
((mode->vdisplay - 1) << 16) |
4859
(mode->hdisplay - 1));
4860
I915_WRITE(DSPPOS(plane), 0);
4862
I915_WRITE(PIPECONF(pipe), pipeconf);
4863
POSTING_READ(PIPECONF(pipe));
4864
intel_enable_pipe(dev_priv, pipe, false);
4866
intel_wait_for_vblank(dev, pipe);
4868
I915_WRITE(DSPCNTR(plane), dspcntr);
4869
POSTING_READ(DSPCNTR(plane));
4871
ret = intel_pipe_set_base(crtc, x, y, fb);
4873
intel_update_watermarks(dev);
4878
static void ironlake_init_pch_refclk(struct drm_device *dev)
4880
struct drm_i915_private *dev_priv = dev->dev_private;
4881
struct drm_mode_config *mode_config = &dev->mode_config;
4882
struct intel_encoder *encoder;
4884
bool has_lvds = false;
4885
bool has_cpu_edp = false;
4886
bool has_pch_edp = false;
4887
bool has_panel = false;
4888
bool has_ck505 = false;
4889
bool can_ssc = false;
4891
/* We need to take the global config into account */
4892
list_for_each_entry(encoder, &mode_config->encoder_list,
4894
switch (encoder->type) {
4895
case INTEL_OUTPUT_LVDS:
4899
case INTEL_OUTPUT_EDP:
4901
if (intel_encoder_is_pch_edp(&encoder->base))
4909
if (HAS_PCH_IBX(dev)) {
4910
has_ck505 = dev_priv->display_clock_mode;
4911
can_ssc = has_ck505;
4917
DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4918
has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4921
/* Ironlake: try to setup display ref clock before DPLL
4922
* enabling. This is only under driver's control after
4923
* PCH B stepping, previous chipset stepping should be
4924
* ignoring this setting.
4926
temp = I915_READ(PCH_DREF_CONTROL);
4927
/* Always enable nonspread source */
4928
temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4931
temp |= DREF_NONSPREAD_CK505_ENABLE;
4933
temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4936
temp &= ~DREF_SSC_SOURCE_MASK;
4937
temp |= DREF_SSC_SOURCE_ENABLE;
4939
/* SSC must be turned on before enabling the CPU output */
4940
if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4941
DRM_DEBUG_KMS("Using SSC on panel\n");
4942
temp |= DREF_SSC1_ENABLE;
4944
temp &= ~DREF_SSC1_ENABLE;
4946
/* Get SSC going before enabling the outputs */
4947
I915_WRITE(PCH_DREF_CONTROL, temp);
4948
POSTING_READ(PCH_DREF_CONTROL);
4951
temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4953
/* Enable CPU source on CPU attached eDP */
4955
if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4956
DRM_DEBUG_KMS("Using SSC on eDP\n");
4957
temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4960
temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4962
temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4964
I915_WRITE(PCH_DREF_CONTROL, temp);
4965
POSTING_READ(PCH_DREF_CONTROL);
4968
DRM_DEBUG_KMS("Disabling SSC entirely\n");
4970
temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4972
/* Turn off CPU output */
4973
temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4975
I915_WRITE(PCH_DREF_CONTROL, temp);
4976
POSTING_READ(PCH_DREF_CONTROL);
4979
/* Turn off the SSC source */
4980
temp &= ~DREF_SSC_SOURCE_MASK;
4981
temp |= DREF_SSC_SOURCE_DISABLE;
4984
temp &= ~ DREF_SSC1_ENABLE;
4986
I915_WRITE(PCH_DREF_CONTROL, temp);
4987
POSTING_READ(PCH_DREF_CONTROL);
4992
/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4993
static void lpt_init_pch_refclk(struct drm_device *dev)
4995
struct drm_i915_private *dev_priv = dev->dev_private;
4996
struct drm_mode_config *mode_config = &dev->mode_config;
4997
struct intel_encoder *encoder;
4998
bool has_vga = false;
4999
bool is_sdv = false;
5002
list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5003
switch (encoder->type) {
5004
case INTEL_OUTPUT_ANALOG:
5013
if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5016
tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5017
tmp &= ~SBI_SSCCTL_DISABLE;
5018
tmp |= SBI_SSCCTL_PATHALT;
5019
intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5023
tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5024
tmp &= ~SBI_SSCCTL_PATHALT;
5025
intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5028
tmp = I915_READ(SOUTH_CHICKEN2);
5029
tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5030
I915_WRITE(SOUTH_CHICKEN2, tmp);
5032
if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5033
FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5034
DRM_ERROR("FDI mPHY resert assert timeout\n");
5036
tmp = I915_READ(SOUTH_CHICKEN2);
5037
tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5038
I915_WRITE(SOUTH_CHICKEN2, tmp);
5040
if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5041
FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5043
DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5046
tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5047
tmp &= ~(0xFF << 24);
5048
tmp |= (0x12 << 24);
5049
intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5052
tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
5054
tmp |= (1 << 6) | (1 << 0);
5055
intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
5059
tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5061
intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5064
tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5066
intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5068
tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5070
intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5073
tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5074
tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5075
intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5077
tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5078
tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5079
intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5081
tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5083
intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5085
tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5087
intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5090
tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5091
tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5092
intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5094
tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5095
tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5096
intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5099
tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5102
intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5104
tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5107
intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5110
tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5113
intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5115
tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5118
intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5120
tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5121
tmp &= ~(0xFF << 16);
5122
tmp |= (0x1C << 16);
5123
intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5125
tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5126
tmp &= ~(0xFF << 16);
5127
tmp |= (0x1C << 16);
5128
intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5131
tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5133
intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5135
tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5137
intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5139
tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5140
tmp &= ~(0xF << 28);
5142
intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5144
tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5145
tmp &= ~(0xF << 28);
5147
intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5150
tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5151
tmp |= SBI_DBUFF0_ENABLE;
5152
intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5156
* Initialize reference clocks when the driver loads
5158
void intel_init_pch_refclk(struct drm_device *dev)
5160
if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5161
ironlake_init_pch_refclk(dev);
5162
else if (HAS_PCH_LPT(dev))
5163
lpt_init_pch_refclk(dev);
5166
static int ironlake_get_refclk(struct drm_crtc *crtc)
5168
struct drm_device *dev = crtc->dev;
5169
struct drm_i915_private *dev_priv = dev->dev_private;
5170
struct intel_encoder *encoder;
5171
struct intel_encoder *edp_encoder = NULL;
5172
int num_connectors = 0;
5173
bool is_lvds = false;
5175
for_each_encoder_on_crtc(dev, crtc, encoder) {
5176
switch (encoder->type) {
5177
case INTEL_OUTPUT_LVDS:
5180
case INTEL_OUTPUT_EDP:
5181
edp_encoder = encoder;
5187
if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5188
DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5189
dev_priv->lvds_ssc_freq);
5190
return dev_priv->lvds_ssc_freq * 1000;
5196
static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5197
struct drm_display_mode *adjusted_mode,
5200
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5201
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5202
int pipe = intel_crtc->pipe;
5205
val = I915_READ(PIPECONF(pipe));
5207
val &= ~PIPE_BPC_MASK;
5208
switch (intel_crtc->bpp) {
5222
/* Case prevented by intel_choose_pipe_bpp_dither. */
5226
val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5228
val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5230
val &= ~PIPECONF_INTERLACE_MASK;
5231
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5232
val |= PIPECONF_INTERLACED_ILK;
5234
val |= PIPECONF_PROGRESSIVE;
5236
I915_WRITE(PIPECONF(pipe), val);
5237
POSTING_READ(PIPECONF(pipe));
5240
static void haswell_set_pipeconf(struct drm_crtc *crtc,
5241
struct drm_display_mode *adjusted_mode,
5244
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5245
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5246
enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5249
val = I915_READ(PIPECONF(cpu_transcoder));
5251
val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5253
val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5255
val &= ~PIPECONF_INTERLACE_MASK_HSW;
5256
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5257
val |= PIPECONF_INTERLACED_ILK;
5259
val |= PIPECONF_PROGRESSIVE;
5261
I915_WRITE(PIPECONF(cpu_transcoder), val);
5262
POSTING_READ(PIPECONF(cpu_transcoder));
5265
static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5266
struct drm_display_mode *adjusted_mode,
5267
intel_clock_t *clock,
5268
bool *has_reduced_clock,
5269
intel_clock_t *reduced_clock)
5271
struct drm_device *dev = crtc->dev;
5272
struct drm_i915_private *dev_priv = dev->dev_private;
5273
struct intel_encoder *intel_encoder;
5275
const intel_limit_t *limit;
5276
bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5278
for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5279
switch (intel_encoder->type) {
5280
case INTEL_OUTPUT_LVDS:
5283
case INTEL_OUTPUT_SDVO:
5284
case INTEL_OUTPUT_HDMI:
5286
if (intel_encoder->needs_tv_clock)
5289
case INTEL_OUTPUT_TVOUT:
5295
refclk = ironlake_get_refclk(crtc);
5298
* Returns a set of divisors for the desired target clock with the given
5299
* refclk, or FALSE. The returned values represent the clock equation:
5300
* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5302
limit = intel_limit(crtc, refclk);
5303
ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5308
if (is_lvds && dev_priv->lvds_downclock_avail) {
5310
* Ensure we match the reduced clock's P to the target clock.
5311
* If the clocks don't match, we can't switch the display clock
5312
* by using the FP0/FP1. In such case we will disable the LVDS
5313
* downclock feature.
5315
*has_reduced_clock = limit->find_pll(limit, crtc,
5316
dev_priv->lvds_downclock,
5322
if (is_sdvo && is_tv)
5323
i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5328
static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5330
struct drm_i915_private *dev_priv = dev->dev_private;
5333
temp = I915_READ(SOUTH_CHICKEN1);
5334
if (temp & FDI_BC_BIFURCATION_SELECT)
5337
WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5338
WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5340
temp |= FDI_BC_BIFURCATION_SELECT;
5341
DRM_DEBUG_KMS("enabling fdi C rx\n");
5342
I915_WRITE(SOUTH_CHICKEN1, temp);
5343
POSTING_READ(SOUTH_CHICKEN1);
5346
static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5348
struct drm_device *dev = intel_crtc->base.dev;
5349
struct drm_i915_private *dev_priv = dev->dev_private;
5350
struct intel_crtc *pipe_B_crtc =
5351
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5353
DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5354
intel_crtc->pipe, intel_crtc->fdi_lanes);
5355
if (intel_crtc->fdi_lanes > 4) {
5356
DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5357
intel_crtc->pipe, intel_crtc->fdi_lanes);
5358
/* Clamp lanes to avoid programming the hw with bogus values. */
5359
intel_crtc->fdi_lanes = 4;
5364
if (dev_priv->num_pipe == 2)
5367
switch (intel_crtc->pipe) {
5371
if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5372
intel_crtc->fdi_lanes > 2) {
5373
DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5374
intel_crtc->pipe, intel_crtc->fdi_lanes);
5375
/* Clamp lanes to avoid programming the hw with bogus values. */
5376
intel_crtc->fdi_lanes = 2;
5381
if (intel_crtc->fdi_lanes > 2)
5382
WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5384
cpt_enable_fdi_bc_bifurcation(dev);
5388
if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5389
if (intel_crtc->fdi_lanes > 2) {
5390
DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5391
intel_crtc->pipe, intel_crtc->fdi_lanes);
5392
/* Clamp lanes to avoid programming the hw with bogus values. */
5393
intel_crtc->fdi_lanes = 2;
5398
DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5402
cpt_enable_fdi_bc_bifurcation(dev);
5410
int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5413
* Account for spread spectrum to avoid
5414
* oversubscribing the link. Max center spread
5415
* is 2.5%; use 5% for safety's sake.
5417
u32 bps = target_clock * bpp * 21 / 20;
5418
return bps / (link_bw * 8) + 1;
5421
static void ironlake_set_m_n(struct drm_crtc *crtc,
5422
struct drm_display_mode *mode,
5423
struct drm_display_mode *adjusted_mode)
5425
struct drm_device *dev = crtc->dev;
5426
struct drm_i915_private *dev_priv = dev->dev_private;
5427
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5428
enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5429
struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5430
struct fdi_m_n m_n = {0};
5431
int target_clock, pixel_multiplier, lane, link_bw;
5432
bool is_dp = false, is_cpu_edp = false;
5434
for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5435
switch (intel_encoder->type) {
5436
case INTEL_OUTPUT_DISPLAYPORT:
5439
case INTEL_OUTPUT_EDP:
5441
if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5443
edp_encoder = intel_encoder;
5449
pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5451
/* CPU eDP doesn't require FDI link, so just set DP M/N
5452
according to current link config */
5454
intel_edp_link_config(edp_encoder, &lane, &link_bw);
5456
/* FDI is a binary signal running at ~2.7GHz, encoding
5457
* each output octet as 10 bits. The actual frequency
5458
* is stored as a divider into a 100MHz clock, and the
5459
* mode pixel clock is stored in units of 1KHz.
5460
* Hence the bw of each lane in terms of the mode signal
5463
link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5466
/* [e]DP over FDI requires target mode clock instead of link clock. */
5468
target_clock = intel_edp_target_clock(edp_encoder, mode);
5470
target_clock = mode->clock;
5472
target_clock = adjusted_mode->clock;
5475
lane = ironlake_get_lanes_required(target_clock, link_bw,
5478
intel_crtc->fdi_lanes = lane;
5480
if (pixel_multiplier > 1)
5481
link_bw *= pixel_multiplier;
5482
ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5485
I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5486
I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5487
I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5488
I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5491
static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5492
struct drm_display_mode *adjusted_mode,
5493
intel_clock_t *clock, u32 fp)
5495
struct drm_crtc *crtc = &intel_crtc->base;
5496
struct drm_device *dev = crtc->dev;
5497
struct drm_i915_private *dev_priv = dev->dev_private;
5498
struct intel_encoder *intel_encoder;
5500
int factor, pixel_multiplier, num_connectors = 0;
5501
bool is_lvds = false, is_sdvo = false, is_tv = false;
5502
bool is_dp = false, is_cpu_edp = false;
5504
for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5505
switch (intel_encoder->type) {
5506
case INTEL_OUTPUT_LVDS:
5509
case INTEL_OUTPUT_SDVO:
5510
case INTEL_OUTPUT_HDMI:
5512
if (intel_encoder->needs_tv_clock)
5515
case INTEL_OUTPUT_TVOUT:
5518
case INTEL_OUTPUT_DISPLAYPORT:
5521
case INTEL_OUTPUT_EDP:
5523
if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5531
/* Enable autotuning of the PLL clock (if permissible) */
5534
if ((intel_panel_use_ssc(dev_priv) &&
5535
dev_priv->lvds_ssc_freq == 100) ||
5536
(I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5538
} else if (is_sdvo && is_tv)
5541
if (clock->m < factor * clock->n)
5547
dpll |= DPLLB_MODE_LVDS;
5549
dpll |= DPLLB_MODE_DAC_SERIAL;
5551
pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5552
if (pixel_multiplier > 1) {
5553
dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5555
dpll |= DPLL_DVO_HIGH_SPEED;
5557
if (is_dp && !is_cpu_edp)
5558
dpll |= DPLL_DVO_HIGH_SPEED;
5560
/* compute bitmask from p1 value */
5561
dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5563
dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5565
switch (clock->p2) {
5567
dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5570
dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5573
dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5576
dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5580
if (is_sdvo && is_tv)
5581
dpll |= PLL_REF_INPUT_TVCLKINBC;
5583
/* XXX: just matching BIOS for now */
5584
/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5586
else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5587
dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5589
dpll |= PLL_REF_INPUT_DREFCLK;
5594
static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5595
struct drm_display_mode *mode,
5596
struct drm_display_mode *adjusted_mode,
5598
struct drm_framebuffer *fb)
5600
struct drm_device *dev = crtc->dev;
5601
struct drm_i915_private *dev_priv = dev->dev_private;
5602
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5603
int pipe = intel_crtc->pipe;
5604
int plane = intel_crtc->plane;
5605
int num_connectors = 0;
5606
intel_clock_t clock, reduced_clock;
5607
u32 dpll, fp = 0, fp2 = 0;
5608
bool ok, has_reduced_clock = false;
5609
bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5610
struct intel_encoder *encoder;
5613
bool dither, fdi_config_ok;
5615
for_each_encoder_on_crtc(dev, crtc, encoder) {
5616
switch (encoder->type) {
5617
case INTEL_OUTPUT_LVDS:
5620
case INTEL_OUTPUT_DISPLAYPORT:
5623
case INTEL_OUTPUT_EDP:
5625
if (!intel_encoder_is_pch_edp(&encoder->base))
5633
WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5634
"Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5636
ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5637
&has_reduced_clock, &reduced_clock);
5639
DRM_ERROR("Couldn't find PLL settings for mode!\n");
5643
/* Ensure that the cursor is valid for the new mode before changing... */
5644
intel_crtc_update_cursor(crtc, true);
5646
/* determine panel color depth */
5647
dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5649
if (is_lvds && dev_priv->lvds_dither)
5652
fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5653
if (has_reduced_clock)
5654
fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5657
dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5659
DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5660
drm_mode_debug_printmodeline(mode);
5662
/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5664
struct intel_pch_pll *pll;
5666
pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5668
DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5673
intel_put_pch_pll(intel_crtc);
5675
/* The LVDS pin pair needs to be on before the DPLLs are enabled.
5676
* This is an exception to the general rule that mode_set doesn't turn
5680
temp = I915_READ(PCH_LVDS);
5681
temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5682
if (HAS_PCH_CPT(dev)) {
5683
temp &= ~PORT_TRANS_SEL_MASK;
5684
temp |= PORT_TRANS_SEL_CPT(pipe);
5687
temp |= LVDS_PIPEB_SELECT;
5689
temp &= ~LVDS_PIPEB_SELECT;
5692
/* set the corresponsding LVDS_BORDER bit */
5693
temp |= dev_priv->lvds_border_bits;
5694
/* Set the B0-B3 data pairs corresponding to whether we're going to
5695
* set the DPLLs for dual-channel mode or not.
5698
temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5700
temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5702
/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5703
* appropriately here, but we need to look more thoroughly into how
5704
* panels behave in the two modes.
5706
temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5707
if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5708
temp |= LVDS_HSYNC_POLARITY;
5709
if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5710
temp |= LVDS_VSYNC_POLARITY;
5711
I915_WRITE(PCH_LVDS, temp);
5714
if (is_dp && !is_cpu_edp) {
5715
intel_dp_set_m_n(crtc, mode, adjusted_mode);
5717
/* For non-DP output, clear any trans DP clock recovery setting.*/
5718
I915_WRITE(TRANSDATA_M1(pipe), 0);
5719
I915_WRITE(TRANSDATA_N1(pipe), 0);
5720
I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5721
I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5724
if (intel_crtc->pch_pll) {
5725
I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5727
/* Wait for the clocks to stabilize. */
5728
POSTING_READ(intel_crtc->pch_pll->pll_reg);
5731
/* The pixel multiplier can only be updated once the
5732
* DPLL is enabled and the clocks are stable.
5734
* So write it again.
5736
I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5739
intel_crtc->lowfreq_avail = false;
5740
if (intel_crtc->pch_pll) {
5741
if (is_lvds && has_reduced_clock && i915_powersave) {
5742
I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5743
intel_crtc->lowfreq_avail = true;
5745
I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5749
intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5751
/* Note, this also computes intel_crtc->fdi_lanes which is used below in
5752
* ironlake_check_fdi_lanes. */
5753
ironlake_set_m_n(crtc, mode, adjusted_mode);
5755
fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5758
ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5760
ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5762
intel_wait_for_vblank(dev, pipe);
5764
/* Set up the display plane register */
5765
I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5766
POSTING_READ(DSPCNTR(plane));
5768
ret = intel_pipe_set_base(crtc, x, y, fb);
5770
intel_update_watermarks(dev);
5772
intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5774
return fdi_config_ok ? ret : -EINVAL;
5777
static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5778
struct drm_display_mode *mode,
5779
struct drm_display_mode *adjusted_mode,
5781
struct drm_framebuffer *fb)
5783
struct drm_device *dev = crtc->dev;
5784
struct drm_i915_private *dev_priv = dev->dev_private;
5785
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5786
int pipe = intel_crtc->pipe;
5787
int plane = intel_crtc->plane;
5788
int num_connectors = 0;
5789
intel_clock_t clock, reduced_clock;
5790
u32 dpll = 0, fp = 0, fp2 = 0;
5791
bool ok, has_reduced_clock = false;
5792
bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5793
struct intel_encoder *encoder;
5798
for_each_encoder_on_crtc(dev, crtc, encoder) {
5799
switch (encoder->type) {
5800
case INTEL_OUTPUT_LVDS:
5803
case INTEL_OUTPUT_DISPLAYPORT:
5806
case INTEL_OUTPUT_EDP:
5808
if (!intel_encoder_is_pch_edp(&encoder->base))
5817
intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5819
intel_crtc->cpu_transcoder = pipe;
5821
/* We are not sure yet this won't happen. */
5822
WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5823
INTEL_PCH_TYPE(dev));
5825
WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5826
num_connectors, pipe_name(pipe));
5828
WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5829
(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5831
WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5833
if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5836
if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5837
ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5841
DRM_ERROR("Couldn't find PLL settings for mode!\n");
5846
/* Ensure that the cursor is valid for the new mode before changing... */
5847
intel_crtc_update_cursor(crtc, true);
5849
/* determine panel color depth */
5850
dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5852
if (is_lvds && dev_priv->lvds_dither)
5855
DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5856
drm_mode_debug_printmodeline(mode);
5858
if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5859
fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5860
if (has_reduced_clock)
5861
fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5864
dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5867
/* CPU eDP is the only output that doesn't need a PCH PLL of its
5868
* own on pre-Haswell/LPT generation */
5870
struct intel_pch_pll *pll;
5872
pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5874
DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5879
intel_put_pch_pll(intel_crtc);
5881
/* The LVDS pin pair needs to be on before the DPLLs are
5882
* enabled. This is an exception to the general rule that
5883
* mode_set doesn't turn things on.
5886
temp = I915_READ(PCH_LVDS);
5887
temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5888
if (HAS_PCH_CPT(dev)) {
5889
temp &= ~PORT_TRANS_SEL_MASK;
5890
temp |= PORT_TRANS_SEL_CPT(pipe);
5893
temp |= LVDS_PIPEB_SELECT;
5895
temp &= ~LVDS_PIPEB_SELECT;
5898
/* set the corresponsding LVDS_BORDER bit */
5899
temp |= dev_priv->lvds_border_bits;
5900
/* Set the B0-B3 data pairs corresponding to whether
5901
* we're going to set the DPLLs for dual-channel mode or
5905
temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5907
temp &= ~(LVDS_B0B3_POWER_UP |
5908
LVDS_CLKB_POWER_UP);
5910
/* It would be nice to set 24 vs 18-bit mode
5911
* (LVDS_A3_POWER_UP) appropriately here, but we need to
5912
* look more thoroughly into how panels behave in the
5915
temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5916
if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5917
temp |= LVDS_HSYNC_POLARITY;
5918
if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5919
temp |= LVDS_VSYNC_POLARITY;
5920
I915_WRITE(PCH_LVDS, temp);
5924
if (is_dp && !is_cpu_edp) {
5925
intel_dp_set_m_n(crtc, mode, adjusted_mode);
5927
if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5928
/* For non-DP output, clear any trans DP clock recovery
5930
I915_WRITE(TRANSDATA_M1(pipe), 0);
5931
I915_WRITE(TRANSDATA_N1(pipe), 0);
5932
I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5933
I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5937
intel_crtc->lowfreq_avail = false;
5938
if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5939
if (intel_crtc->pch_pll) {
5940
I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5942
/* Wait for the clocks to stabilize. */
5943
POSTING_READ(intel_crtc->pch_pll->pll_reg);
5946
/* The pixel multiplier can only be updated once the
5947
* DPLL is enabled and the clocks are stable.
5949
* So write it again.
5951
I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5954
if (intel_crtc->pch_pll) {
5955
if (is_lvds && has_reduced_clock && i915_powersave) {
5956
I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5957
intel_crtc->lowfreq_avail = true;
5959
I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5964
intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5966
if (!is_dp || is_cpu_edp)
5967
ironlake_set_m_n(crtc, mode, adjusted_mode);
5969
if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5971
ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5973
haswell_set_pipeconf(crtc, adjusted_mode, dither);
5975
/* Set up the display plane register */
5976
I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5977
POSTING_READ(DSPCNTR(plane));
5979
ret = intel_pipe_set_base(crtc, x, y, fb);
5981
intel_update_watermarks(dev);
5983
intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5988
static int intel_crtc_mode_set(struct drm_crtc *crtc,
5989
struct drm_display_mode *mode,
5990
struct drm_display_mode *adjusted_mode,
5992
struct drm_framebuffer *fb)
5994
struct drm_device *dev = crtc->dev;
5995
struct drm_i915_private *dev_priv = dev->dev_private;
5996
struct drm_encoder_helper_funcs *encoder_funcs;
5997
struct intel_encoder *encoder;
5998
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5999
int pipe = intel_crtc->pipe;
6002
drm_vblank_pre_modeset(dev, pipe);
6004
ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6006
drm_vblank_post_modeset(dev, pipe);
6011
for_each_encoder_on_crtc(dev, crtc, encoder) {
6012
DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6013
encoder->base.base.id,
6014
drm_get_encoder_name(&encoder->base),
6015
mode->base.id, mode->name);
6016
encoder_funcs = encoder->base.helper_private;
6017
encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6023
static bool intel_eld_uptodate(struct drm_connector *connector,
6024
int reg_eldv, uint32_t bits_eldv,
6025
int reg_elda, uint32_t bits_elda,
6028
struct drm_i915_private *dev_priv = connector->dev->dev_private;
6029
uint8_t *eld = connector->eld;
6032
i = I915_READ(reg_eldv);
6041
i = I915_READ(reg_elda);
6043
I915_WRITE(reg_elda, i);
6045
for (i = 0; i < eld[2]; i++)
6046
if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6052
static void g4x_write_eld(struct drm_connector *connector,
6053
struct drm_crtc *crtc)
6055
struct drm_i915_private *dev_priv = connector->dev->dev_private;
6056
uint8_t *eld = connector->eld;
6061
i = I915_READ(G4X_AUD_VID_DID);
6063
if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6064
eldv = G4X_ELDV_DEVCL_DEVBLC;
6066
eldv = G4X_ELDV_DEVCTG;
6068
if (intel_eld_uptodate(connector,
6069
G4X_AUD_CNTL_ST, eldv,
6070
G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6071
G4X_HDMIW_HDMIEDID))
6074
i = I915_READ(G4X_AUD_CNTL_ST);
6075
i &= ~(eldv | G4X_ELD_ADDR);
6076
len = (i >> 9) & 0x1f; /* ELD buffer size */
6077
I915_WRITE(G4X_AUD_CNTL_ST, i);
6082
len = min_t(uint8_t, eld[2], len);
6083
DRM_DEBUG_DRIVER("ELD size %d\n", len);
6084
for (i = 0; i < len; i++)
6085
I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6087
i = I915_READ(G4X_AUD_CNTL_ST);
6089
I915_WRITE(G4X_AUD_CNTL_ST, i);
6092
static void haswell_write_eld(struct drm_connector *connector,
6093
struct drm_crtc *crtc)
6095
struct drm_i915_private *dev_priv = connector->dev->dev_private;
6096
uint8_t *eld = connector->eld;
6097
struct drm_device *dev = crtc->dev;
6101
int pipe = to_intel_crtc(crtc)->pipe;
6104
int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6105
int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6106
int aud_config = HSW_AUD_CFG(pipe);
6107
int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6110
DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6112
/* Audio output enable */
6113
DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6114
tmp = I915_READ(aud_cntrl_st2);
6115
tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6116
I915_WRITE(aud_cntrl_st2, tmp);
6118
/* Wait for 1 vertical blank */
6119
intel_wait_for_vblank(dev, pipe);
6121
/* Set ELD valid state */
6122
tmp = I915_READ(aud_cntrl_st2);
6123
DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6124
tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6125
I915_WRITE(aud_cntrl_st2, tmp);
6126
tmp = I915_READ(aud_cntrl_st2);
6127
DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6129
/* Enable HDMI mode */
6130
tmp = I915_READ(aud_config);
6131
DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6132
/* clear N_programing_enable and N_value_index */
6133
tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6134
I915_WRITE(aud_config, tmp);
6136
DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6138
eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6140
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6141
DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6142
eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6143
I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6145
I915_WRITE(aud_config, 0);
6147
if (intel_eld_uptodate(connector,
6148
aud_cntrl_st2, eldv,
6149
aud_cntl_st, IBX_ELD_ADDRESS,
6153
i = I915_READ(aud_cntrl_st2);
6155
I915_WRITE(aud_cntrl_st2, i);
6160
i = I915_READ(aud_cntl_st);
6161
i &= ~IBX_ELD_ADDRESS;
6162
I915_WRITE(aud_cntl_st, i);
6163
i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6164
DRM_DEBUG_DRIVER("port num:%d\n", i);
6166
len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6167
DRM_DEBUG_DRIVER("ELD size %d\n", len);
6168
for (i = 0; i < len; i++)
6169
I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6171
i = I915_READ(aud_cntrl_st2);
6173
I915_WRITE(aud_cntrl_st2, i);
6177
static void ironlake_write_eld(struct drm_connector *connector,
6178
struct drm_crtc *crtc)
6180
struct drm_i915_private *dev_priv = connector->dev->dev_private;
6181
uint8_t *eld = connector->eld;
6189
int pipe = to_intel_crtc(crtc)->pipe;
6191
if (HAS_PCH_IBX(connector->dev)) {
6192
hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6193
aud_config = IBX_AUD_CFG(pipe);
6194
aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6195
aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6197
hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6198
aud_config = CPT_AUD_CFG(pipe);
6199
aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6200
aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6203
DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6205
i = I915_READ(aud_cntl_st);
6206
i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6208
DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6209
/* operate blindly on all ports */
6210
eldv = IBX_ELD_VALIDB;
6211
eldv |= IBX_ELD_VALIDB << 4;
6212
eldv |= IBX_ELD_VALIDB << 8;
6214
DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6215
eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6218
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6219
DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6220
eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6221
I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6223
I915_WRITE(aud_config, 0);
6225
if (intel_eld_uptodate(connector,
6226
aud_cntrl_st2, eldv,
6227
aud_cntl_st, IBX_ELD_ADDRESS,
6231
i = I915_READ(aud_cntrl_st2);
6233
I915_WRITE(aud_cntrl_st2, i);
6238
i = I915_READ(aud_cntl_st);
6239
i &= ~IBX_ELD_ADDRESS;
6240
I915_WRITE(aud_cntl_st, i);
6242
len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6243
DRM_DEBUG_DRIVER("ELD size %d\n", len);
6244
for (i = 0; i < len; i++)
6245
I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6247
i = I915_READ(aud_cntrl_st2);
6249
I915_WRITE(aud_cntrl_st2, i);
6252
void intel_write_eld(struct drm_encoder *encoder,
6253
struct drm_display_mode *mode)
6255
struct drm_crtc *crtc = encoder->crtc;
6256
struct drm_connector *connector;
6257
struct drm_device *dev = encoder->dev;
6258
struct drm_i915_private *dev_priv = dev->dev_private;
6260
connector = drm_select_eld(encoder, mode);
6264
DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6266
drm_get_connector_name(connector),
6267
connector->encoder->base.id,
6268
drm_get_encoder_name(connector->encoder));
6270
connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6272
if (dev_priv->display.write_eld)
6273
dev_priv->display.write_eld(connector, crtc);
6276
/** Loads the palette/gamma unit for the CRTC with the prepared values */
6277
void intel_crtc_load_lut(struct drm_crtc *crtc)
6279
struct drm_device *dev = crtc->dev;
6280
struct drm_i915_private *dev_priv = dev->dev_private;
6281
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6282
int palreg = PALETTE(intel_crtc->pipe);
6285
/* The clocks have to be on to load the palette. */
6286
if (!crtc->enabled || !intel_crtc->active)
6289
/* use legacy palette for Ironlake */
6290
if (HAS_PCH_SPLIT(dev))
6291
palreg = LGC_PALETTE(intel_crtc->pipe);
6293
for (i = 0; i < 256; i++) {
6294
I915_WRITE(palreg + 4 * i,
6295
(intel_crtc->lut_r[i] << 16) |
6296
(intel_crtc->lut_g[i] << 8) |
6297
intel_crtc->lut_b[i]);
6301
static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6303
struct drm_device *dev = crtc->dev;
6304
struct drm_i915_private *dev_priv = dev->dev_private;
6305
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6306
bool visible = base != 0;
6309
if (intel_crtc->cursor_visible == visible)
6312
cntl = I915_READ(_CURACNTR);
6314
/* On these chipsets we can only modify the base whilst
6315
* the cursor is disabled.
6317
I915_WRITE(_CURABASE, base);
6319
cntl &= ~(CURSOR_FORMAT_MASK);
6320
/* XXX width must be 64, stride 256 => 0x00 << 28 */
6321
cntl |= CURSOR_ENABLE |
6322
CURSOR_GAMMA_ENABLE |
6325
cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6326
I915_WRITE(_CURACNTR, cntl);
6328
intel_crtc->cursor_visible = visible;
6331
static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6333
struct drm_device *dev = crtc->dev;
6334
struct drm_i915_private *dev_priv = dev->dev_private;
6335
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6336
int pipe = intel_crtc->pipe;
6337
bool visible = base != 0;
6339
if (intel_crtc->cursor_visible != visible) {
6340
uint32_t cntl = I915_READ(CURCNTR(pipe));
6342
cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6343
cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6344
cntl |= pipe << 28; /* Connect to correct pipe */
6346
cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6347
cntl |= CURSOR_MODE_DISABLE;
6349
I915_WRITE(CURCNTR(pipe), cntl);
6351
intel_crtc->cursor_visible = visible;
6353
/* and commit changes on next vblank */
6354
I915_WRITE(CURBASE(pipe), base);
6357
static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6359
struct drm_device *dev = crtc->dev;
6360
struct drm_i915_private *dev_priv = dev->dev_private;
6361
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6362
int pipe = intel_crtc->pipe;
6363
bool visible = base != 0;
6365
if (intel_crtc->cursor_visible != visible) {
6366
uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6368
cntl &= ~CURSOR_MODE;
6369
cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6371
cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6372
cntl |= CURSOR_MODE_DISABLE;
6374
I915_WRITE(CURCNTR_IVB(pipe), cntl);
6376
intel_crtc->cursor_visible = visible;
6378
/* and commit changes on next vblank */
6379
I915_WRITE(CURBASE_IVB(pipe), base);
6382
/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6383
static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6386
struct drm_device *dev = crtc->dev;
6387
struct drm_i915_private *dev_priv = dev->dev_private;
6388
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6389
int pipe = intel_crtc->pipe;
6390
int x = intel_crtc->cursor_x;
6391
int y = intel_crtc->cursor_y;
6397
if (on && crtc->enabled && crtc->fb) {
6398
base = intel_crtc->cursor_addr;
6399
if (x > (int) crtc->fb->width)
6402
if (y > (int) crtc->fb->height)
6408
if (x + intel_crtc->cursor_width < 0)
6411
pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6414
pos |= x << CURSOR_X_SHIFT;
6417
if (y + intel_crtc->cursor_height < 0)
6420
pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6423
pos |= y << CURSOR_Y_SHIFT;
6425
visible = base != 0;
6426
if (!visible && !intel_crtc->cursor_visible)
6429
if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6430
I915_WRITE(CURPOS_IVB(pipe), pos);
6431
ivb_update_cursor(crtc, base);
6433
I915_WRITE(CURPOS(pipe), pos);
6434
if (IS_845G(dev) || IS_I865G(dev))
6435
i845_update_cursor(crtc, base);
6437
i9xx_update_cursor(crtc, base);
6441
static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6442
struct drm_file *file,
6444
uint32_t width, uint32_t height)
6446
struct drm_device *dev = crtc->dev;
6447
struct drm_i915_private *dev_priv = dev->dev_private;
6448
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6449
struct drm_i915_gem_object *obj;
6453
/* if we want to turn off the cursor ignore width and height */
6455
DRM_DEBUG_KMS("cursor off\n");
6458
mutex_lock(&dev->struct_mutex);
6462
/* Currently we only support 64x64 cursors */
6463
if (width != 64 || height != 64) {
6464
DRM_ERROR("we currently only support 64x64 cursors\n");
6468
obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6469
if (&obj->base == NULL)
6472
if (obj->base.size < width * height * 4) {
6473
DRM_ERROR("buffer is to small\n");
6478
/* we only need to pin inside GTT if cursor is non-phy */
6479
mutex_lock(&dev->struct_mutex);
6480
if (!dev_priv->info->cursor_needs_physical) {
6481
if (obj->tiling_mode) {
6482
DRM_ERROR("cursor cannot be tiled\n");
6487
ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6489
DRM_ERROR("failed to move cursor bo into the GTT\n");
6493
ret = i915_gem_object_put_fence(obj);
6495
DRM_ERROR("failed to release fence for cursor");
6499
addr = obj->gtt_offset;
6501
int align = IS_I830(dev) ? 16 * 1024 : 256;
6502
ret = i915_gem_attach_phys_object(dev, obj,
6503
(intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6506
DRM_ERROR("failed to attach phys object\n");
6509
addr = obj->phys_obj->handle->busaddr;
6513
I915_WRITE(CURSIZE, (height << 12) | width);
6516
if (intel_crtc->cursor_bo) {
6517
if (dev_priv->info->cursor_needs_physical) {
6518
if (intel_crtc->cursor_bo != obj)
6519
i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6521
i915_gem_object_unpin(intel_crtc->cursor_bo);
6522
drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6525
mutex_unlock(&dev->struct_mutex);
6527
intel_crtc->cursor_addr = addr;
6528
intel_crtc->cursor_bo = obj;
6529
intel_crtc->cursor_width = width;
6530
intel_crtc->cursor_height = height;
6532
intel_crtc_update_cursor(crtc, true);
6536
i915_gem_object_unpin(obj);
6538
mutex_unlock(&dev->struct_mutex);
6540
drm_gem_object_unreference_unlocked(&obj->base);
6544
static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6546
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6548
intel_crtc->cursor_x = x;
6549
intel_crtc->cursor_y = y;
6551
intel_crtc_update_cursor(crtc, true);
6556
/** Sets the color ramps on behalf of RandR */
6557
void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6558
u16 blue, int regno)
6560
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6562
intel_crtc->lut_r[regno] = red >> 8;
6563
intel_crtc->lut_g[regno] = green >> 8;
6564
intel_crtc->lut_b[regno] = blue >> 8;
6567
void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6568
u16 *blue, int regno)
6570
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6572
*red = intel_crtc->lut_r[regno] << 8;
6573
*green = intel_crtc->lut_g[regno] << 8;
6574
*blue = intel_crtc->lut_b[regno] << 8;
6577
static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6578
u16 *blue, uint32_t start, uint32_t size)
6580
int end = (start + size > 256) ? 256 : start + size, i;
6581
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6583
for (i = start; i < end; i++) {
6584
intel_crtc->lut_r[i] = red[i] >> 8;
6585
intel_crtc->lut_g[i] = green[i] >> 8;
6586
intel_crtc->lut_b[i] = blue[i] >> 8;
6589
intel_crtc_load_lut(crtc);
6593
* Get a pipe with a simple mode set on it for doing load-based monitor
6596
* It will be up to the load-detect code to adjust the pipe as appropriate for
6597
* its requirements. The pipe will be connected to no other encoders.
6599
* Currently this code will only succeed if there is a pipe with no encoders
6600
* configured for it. In the future, it could choose to temporarily disable
6601
* some outputs to free up a pipe for its use.
6603
* \return crtc, or NULL if no pipes are available.
6606
/* VESA 640x480x72Hz mode to set on the pipe */
6607
static struct drm_display_mode load_detect_mode = {
6608
DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6609
704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6612
static struct drm_framebuffer *
6613
intel_framebuffer_create(struct drm_device *dev,
6614
struct drm_mode_fb_cmd2 *mode_cmd,
6615
struct drm_i915_gem_object *obj)
6617
struct intel_framebuffer *intel_fb;
6620
intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6622
drm_gem_object_unreference_unlocked(&obj->base);
6623
return ERR_PTR(-ENOMEM);
6626
ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6628
drm_gem_object_unreference_unlocked(&obj->base);
6630
return ERR_PTR(ret);
6633
return &intel_fb->base;
6637
intel_framebuffer_pitch_for_width(int width, int bpp)
6639
u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6640
return ALIGN(pitch, 64);
6644
intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6646
u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6647
return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6650
static struct drm_framebuffer *
6651
intel_framebuffer_create_for_mode(struct drm_device *dev,
6652
struct drm_display_mode *mode,
6655
struct drm_i915_gem_object *obj;
6656
struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6658
obj = i915_gem_alloc_object(dev,
6659
intel_framebuffer_size_for_mode(mode, bpp));
6661
return ERR_PTR(-ENOMEM);
6663
mode_cmd.width = mode->hdisplay;
6664
mode_cmd.height = mode->vdisplay;
6665
mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6667
mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6669
return intel_framebuffer_create(dev, &mode_cmd, obj);
6672
static struct drm_framebuffer *
6673
mode_fits_in_fbdev(struct drm_device *dev,
6674
struct drm_display_mode *mode)
6676
struct drm_i915_private *dev_priv = dev->dev_private;
6677
struct drm_i915_gem_object *obj;
6678
struct drm_framebuffer *fb;
6680
if (dev_priv->fbdev == NULL)
6683
obj = dev_priv->fbdev->ifb.obj;
6687
fb = &dev_priv->fbdev->ifb.base;
6688
if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6689
fb->bits_per_pixel))
6692
if (obj->base.size < mode->vdisplay * fb->pitches[0])
6698
bool intel_get_load_detect_pipe(struct drm_connector *connector,
6699
struct drm_display_mode *mode,
6700
struct intel_load_detect_pipe *old)
6702
struct intel_crtc *intel_crtc;
6703
struct intel_encoder *intel_encoder =
6704
intel_attached_encoder(connector);
6705
struct drm_crtc *possible_crtc;
6706
struct drm_encoder *encoder = &intel_encoder->base;
6707
struct drm_crtc *crtc = NULL;
6708
struct drm_device *dev = encoder->dev;
6709
struct drm_framebuffer *fb;
6712
DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6713
connector->base.id, drm_get_connector_name(connector),
6714
encoder->base.id, drm_get_encoder_name(encoder));
6717
* Algorithm gets a little messy:
6719
* - if the connector already has an assigned crtc, use it (but make
6720
* sure it's on first)
6722
* - try to find the first unused crtc that can drive this connector,
6723
* and use that if we find one
6726
/* See if we already have a CRTC for this connector */
6727
if (encoder->crtc) {
6728
crtc = encoder->crtc;
6730
old->dpms_mode = connector->dpms;
6731
old->load_detect_temp = false;
6733
/* Make sure the crtc and connector are running */
6734
if (connector->dpms != DRM_MODE_DPMS_ON)
6735
connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6740
/* Find an unused one (if possible) */
6741
list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6743
if (!(encoder->possible_crtcs & (1 << i)))
6745
if (!possible_crtc->enabled) {
6746
crtc = possible_crtc;
6752
* If we didn't find an unused CRTC, don't use any.
6755
DRM_DEBUG_KMS("no pipe available for load-detect\n");
6759
intel_encoder->new_crtc = to_intel_crtc(crtc);
6760
to_intel_connector(connector)->new_encoder = intel_encoder;
6762
intel_crtc = to_intel_crtc(crtc);
6763
old->dpms_mode = connector->dpms;
6764
old->load_detect_temp = true;
6765
old->release_fb = NULL;
6768
mode = &load_detect_mode;
6770
/* We need a framebuffer large enough to accommodate all accesses
6771
* that the plane may generate whilst we perform load detection.
6772
* We can not rely on the fbcon either being present (we get called
6773
* during its initialisation to detect all boot displays, or it may
6774
* not even exist) or that it is large enough to satisfy the
6777
fb = mode_fits_in_fbdev(dev, mode);
6779
DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6780
fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6781
old->release_fb = fb;
6783
DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6785
DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6789
if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6790
DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6791
if (old->release_fb)
6792
old->release_fb->funcs->destroy(old->release_fb);
6796
/* let the connector get through one full cycle before testing */
6797
intel_wait_for_vblank(dev, intel_crtc->pipe);
6801
void intel_release_load_detect_pipe(struct drm_connector *connector,
6802
struct intel_load_detect_pipe *old)
6804
struct intel_encoder *intel_encoder =
6805
intel_attached_encoder(connector);
6806
struct drm_encoder *encoder = &intel_encoder->base;
6808
DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6809
connector->base.id, drm_get_connector_name(connector),
6810
encoder->base.id, drm_get_encoder_name(encoder));
6812
if (old->load_detect_temp) {
6813
struct drm_crtc *crtc = encoder->crtc;
6815
to_intel_connector(connector)->new_encoder = NULL;
6816
intel_encoder->new_crtc = NULL;
6817
intel_set_mode(crtc, NULL, 0, 0, NULL);
6819
if (old->release_fb)
6820
old->release_fb->funcs->destroy(old->release_fb);
6825
/* Switch crtc and encoder back off if necessary */
6826
if (old->dpms_mode != DRM_MODE_DPMS_ON)
6827
connector->funcs->dpms(connector, old->dpms_mode);
6830
/* Returns the clock of the currently programmed mode of the given pipe. */
6831
static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6833
struct drm_i915_private *dev_priv = dev->dev_private;
6834
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6835
int pipe = intel_crtc->pipe;
6836
u32 dpll = I915_READ(DPLL(pipe));
6838
intel_clock_t clock;
6840
if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6841
fp = I915_READ(FP0(pipe));
6843
fp = I915_READ(FP1(pipe));
6845
clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6846
if (IS_PINEVIEW(dev)) {
6847
clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6848
clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6850
clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6851
clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6854
if (!IS_GEN2(dev)) {
6855
if (IS_PINEVIEW(dev))
6856
clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6857
DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6859
clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6860
DPLL_FPA01_P1_POST_DIV_SHIFT);
6862
switch (dpll & DPLL_MODE_MASK) {
6863
case DPLLB_MODE_DAC_SERIAL:
6864
clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6867
case DPLLB_MODE_LVDS:
6868
clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6872
DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6873
"mode\n", (int)(dpll & DPLL_MODE_MASK));
6877
/* XXX: Handle the 100Mhz refclk */
6878
intel_clock(dev, 96000, &clock);
6880
bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6883
clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6884
DPLL_FPA01_P1_POST_DIV_SHIFT);
6887
if ((dpll & PLL_REF_INPUT_MASK) ==
6888
PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6889
/* XXX: might not be 66MHz */
6890
intel_clock(dev, 66000, &clock);
6892
intel_clock(dev, 48000, &clock);
6894
if (dpll & PLL_P1_DIVIDE_BY_TWO)
6897
clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6898
DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6900
if (dpll & PLL_P2_DIVIDE_BY_4)
6905
intel_clock(dev, 48000, &clock);
6909
/* XXX: It would be nice to validate the clocks, but we can't reuse
6910
* i830PllIsValid() because it relies on the xf86_config connector
6911
* configuration being accurate, which it isn't necessarily.
6917
/** Returns the currently programmed mode of the given pipe. */
6918
struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6919
struct drm_crtc *crtc)
6921
struct drm_i915_private *dev_priv = dev->dev_private;
6922
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6923
enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6924
struct drm_display_mode *mode;
6925
int htot = I915_READ(HTOTAL(cpu_transcoder));
6926
int hsync = I915_READ(HSYNC(cpu_transcoder));
6927
int vtot = I915_READ(VTOTAL(cpu_transcoder));
6928
int vsync = I915_READ(VSYNC(cpu_transcoder));
6930
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6934
mode->clock = intel_crtc_clock_get(dev, crtc);
6935
mode->hdisplay = (htot & 0xffff) + 1;
6936
mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6937
mode->hsync_start = (hsync & 0xffff) + 1;
6938
mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6939
mode->vdisplay = (vtot & 0xffff) + 1;
6940
mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6941
mode->vsync_start = (vsync & 0xffff) + 1;
6942
mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6944
drm_mode_set_name(mode);
6949
static void intel_increase_pllclock(struct drm_crtc *crtc)
6951
struct drm_device *dev = crtc->dev;
6952
drm_i915_private_t *dev_priv = dev->dev_private;
6953
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6954
int pipe = intel_crtc->pipe;
6955
int dpll_reg = DPLL(pipe);
6958
if (HAS_PCH_SPLIT(dev))
6961
if (!dev_priv->lvds_downclock_avail)
6964
dpll = I915_READ(dpll_reg);
6965
if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6966
DRM_DEBUG_DRIVER("upclocking LVDS\n");
6968
assert_panel_unlocked(dev_priv, pipe);
6970
dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6971
I915_WRITE(dpll_reg, dpll);
6972
intel_wait_for_vblank(dev, pipe);
6974
dpll = I915_READ(dpll_reg);
6975
if (dpll & DISPLAY_RATE_SELECT_FPA1)
6976
DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6980
static void intel_decrease_pllclock(struct drm_crtc *crtc)
6982
struct drm_device *dev = crtc->dev;
6983
drm_i915_private_t *dev_priv = dev->dev_private;
6984
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6986
if (HAS_PCH_SPLIT(dev))
6989
if (!dev_priv->lvds_downclock_avail)
6993
* Since this is called by a timer, we should never get here in
6996
if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6997
int pipe = intel_crtc->pipe;
6998
int dpll_reg = DPLL(pipe);
7001
DRM_DEBUG_DRIVER("downclocking LVDS\n");
7003
assert_panel_unlocked(dev_priv, pipe);
7005
dpll = I915_READ(dpll_reg);
7006
dpll |= DISPLAY_RATE_SELECT_FPA1;
7007
I915_WRITE(dpll_reg, dpll);
7008
intel_wait_for_vblank(dev, pipe);
7009
dpll = I915_READ(dpll_reg);
7010
if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7011
DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7016
void intel_mark_busy(struct drm_device *dev)
7018
i915_update_gfx_val(dev->dev_private);
7021
void intel_mark_idle(struct drm_device *dev)
7025
void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7027
struct drm_device *dev = obj->base.dev;
7028
struct drm_crtc *crtc;
7030
if (!i915_powersave)
7033
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7037
if (to_intel_framebuffer(crtc->fb)->obj == obj)
7038
intel_increase_pllclock(crtc);
7042
void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
7044
struct drm_device *dev = obj->base.dev;
7045
struct drm_crtc *crtc;
7047
if (!i915_powersave)
7050
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7054
if (to_intel_framebuffer(crtc->fb)->obj == obj)
7055
intel_decrease_pllclock(crtc);
7059
static void intel_crtc_destroy(struct drm_crtc *crtc)
7061
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7062
struct drm_device *dev = crtc->dev;
7063
struct intel_unpin_work *work;
7064
unsigned long flags;
7066
spin_lock_irqsave(&dev->event_lock, flags);
7067
work = intel_crtc->unpin_work;
7068
intel_crtc->unpin_work = NULL;
7069
spin_unlock_irqrestore(&dev->event_lock, flags);
7072
cancel_work_sync(&work->work);
7076
drm_crtc_cleanup(crtc);
7081
static void intel_unpin_work_fn(struct work_struct *__work)
7083
struct intel_unpin_work *work =
7084
container_of(__work, struct intel_unpin_work, work);
7085
struct drm_device *dev = work->crtc->dev;
7087
mutex_lock(&dev->struct_mutex);
7088
intel_unpin_fb_obj(work->old_fb_obj);
7089
drm_gem_object_unreference(&work->pending_flip_obj->base);
7090
drm_gem_object_unreference(&work->old_fb_obj->base);
7092
intel_update_fbc(dev);
7093
mutex_unlock(&dev->struct_mutex);
7095
BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7096
atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7101
static void do_intel_finish_page_flip(struct drm_device *dev,
7102
struct drm_crtc *crtc)
7104
drm_i915_private_t *dev_priv = dev->dev_private;
7105
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7106
struct intel_unpin_work *work;
7107
struct drm_i915_gem_object *obj;
7108
struct drm_pending_vblank_event *e;
7109
struct timeval tvbl;
7110
unsigned long flags;
7112
/* Ignore early vblank irqs */
7113
if (intel_crtc == NULL)
7116
spin_lock_irqsave(&dev->event_lock, flags);
7117
work = intel_crtc->unpin_work;
7118
if (work == NULL || !work->pending) {
7119
spin_unlock_irqrestore(&dev->event_lock, flags);
7123
intel_crtc->unpin_work = NULL;
7127
e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
7129
e->event.tv_sec = tvbl.tv_sec;
7130
e->event.tv_usec = tvbl.tv_usec;
7132
list_add_tail(&e->base.link,
7133
&e->base.file_priv->event_list);
7134
wake_up_interruptible(&e->base.file_priv->event_wait);
7137
drm_vblank_put(dev, intel_crtc->pipe);
7139
spin_unlock_irqrestore(&dev->event_lock, flags);
7141
obj = work->old_fb_obj;
7143
atomic_clear_mask(1 << intel_crtc->plane,
7144
&obj->pending_flip.counter);
7145
wake_up(&dev_priv->pending_flip_queue);
7147
queue_work(dev_priv->wq, &work->work);
7149
trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7152
void intel_finish_page_flip(struct drm_device *dev, int pipe)
7154
drm_i915_private_t *dev_priv = dev->dev_private;
7155
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7157
do_intel_finish_page_flip(dev, crtc);
7160
void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7162
drm_i915_private_t *dev_priv = dev->dev_private;
7163
struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7165
do_intel_finish_page_flip(dev, crtc);
7168
void intel_prepare_page_flip(struct drm_device *dev, int plane)
7170
drm_i915_private_t *dev_priv = dev->dev_private;
7171
struct intel_crtc *intel_crtc =
7172
to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7173
unsigned long flags;
7175
spin_lock_irqsave(&dev->event_lock, flags);
7176
if (intel_crtc->unpin_work) {
7177
if ((++intel_crtc->unpin_work->pending) > 1)
7178
DRM_ERROR("Prepared flip multiple times\n");
7180
DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7182
spin_unlock_irqrestore(&dev->event_lock, flags);
7185
static int intel_gen2_queue_flip(struct drm_device *dev,
7186
struct drm_crtc *crtc,
7187
struct drm_framebuffer *fb,
7188
struct drm_i915_gem_object *obj)
7190
struct drm_i915_private *dev_priv = dev->dev_private;
7191
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7193
struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7196
ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7200
ret = intel_ring_begin(ring, 6);
7204
/* Can't queue multiple flips, so wait for the previous
7205
* one to finish before executing the next.
7207
if (intel_crtc->plane)
7208
flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7210
flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7211
intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7212
intel_ring_emit(ring, MI_NOOP);
7213
intel_ring_emit(ring, MI_DISPLAY_FLIP |
7214
MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7215
intel_ring_emit(ring, fb->pitches[0]);
7216
intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7217
intel_ring_emit(ring, 0); /* aux display base address, unused */
7218
intel_ring_advance(ring);
7222
intel_unpin_fb_obj(obj);
7227
static int intel_gen3_queue_flip(struct drm_device *dev,
7228
struct drm_crtc *crtc,
7229
struct drm_framebuffer *fb,
7230
struct drm_i915_gem_object *obj)
7232
struct drm_i915_private *dev_priv = dev->dev_private;
7233
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7235
struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7238
ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7242
ret = intel_ring_begin(ring, 6);
7246
if (intel_crtc->plane)
7247
flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7249
flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7250
intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7251
intel_ring_emit(ring, MI_NOOP);
7252
intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7253
MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7254
intel_ring_emit(ring, fb->pitches[0]);
7255
intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7256
intel_ring_emit(ring, MI_NOOP);
7258
intel_ring_advance(ring);
7262
intel_unpin_fb_obj(obj);
7267
static int intel_gen4_queue_flip(struct drm_device *dev,
7268
struct drm_crtc *crtc,
7269
struct drm_framebuffer *fb,
7270
struct drm_i915_gem_object *obj)
7272
struct drm_i915_private *dev_priv = dev->dev_private;
7273
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7274
uint32_t pf, pipesrc;
7275
struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7278
ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7282
ret = intel_ring_begin(ring, 4);
7286
/* i965+ uses the linear or tiled offsets from the
7287
* Display Registers (which do not change across a page-flip)
7288
* so we need only reprogram the base address.
7290
intel_ring_emit(ring, MI_DISPLAY_FLIP |
7291
MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7292
intel_ring_emit(ring, fb->pitches[0]);
7293
intel_ring_emit(ring,
7294
(obj->gtt_offset + intel_crtc->dspaddr_offset) |
7297
/* XXX Enabling the panel-fitter across page-flip is so far
7298
* untested on non-native modes, so ignore it for now.
7299
* pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7302
pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7303
intel_ring_emit(ring, pf | pipesrc);
7304
intel_ring_advance(ring);
7308
intel_unpin_fb_obj(obj);
7313
static int intel_gen6_queue_flip(struct drm_device *dev,
7314
struct drm_crtc *crtc,
7315
struct drm_framebuffer *fb,
7316
struct drm_i915_gem_object *obj)
7318
struct drm_i915_private *dev_priv = dev->dev_private;
7319
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7320
struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7321
uint32_t pf, pipesrc;
7324
ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7328
ret = intel_ring_begin(ring, 4);
7332
intel_ring_emit(ring, MI_DISPLAY_FLIP |
7333
MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7334
intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7335
intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7337
/* Contrary to the suggestions in the documentation,
7338
* "Enable Panel Fitter" does not seem to be required when page
7339
* flipping with a non-native mode, and worse causes a normal
7341
* pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7344
pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7345
intel_ring_emit(ring, pf | pipesrc);
7346
intel_ring_advance(ring);
7350
intel_unpin_fb_obj(obj);
7356
* On gen7 we currently use the blit ring because (in early silicon at least)
7357
* the render ring doesn't give us interrpts for page flip completion, which
7358
* means clients will hang after the first flip is queued. Fortunately the
7359
* blit ring generates interrupts properly, so use it instead.
7361
static int intel_gen7_queue_flip(struct drm_device *dev,
7362
struct drm_crtc *crtc,
7363
struct drm_framebuffer *fb,
7364
struct drm_i915_gem_object *obj)
7366
struct drm_i915_private *dev_priv = dev->dev_private;
7367
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7368
struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7369
uint32_t plane_bit = 0;
7372
ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7376
switch(intel_crtc->plane) {
7378
plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7381
plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7384
plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7387
WARN_ONCE(1, "unknown plane in flip command\n");
7392
ret = intel_ring_begin(ring, 4);
7396
intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7397
intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7398
intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7399
intel_ring_emit(ring, (MI_NOOP));
7400
intel_ring_advance(ring);
7404
intel_unpin_fb_obj(obj);
7409
static int intel_default_queue_flip(struct drm_device *dev,
7410
struct drm_crtc *crtc,
7411
struct drm_framebuffer *fb,
7412
struct drm_i915_gem_object *obj)
7417
static int intel_crtc_page_flip(struct drm_crtc *crtc,
7418
struct drm_framebuffer *fb,
7419
struct drm_pending_vblank_event *event)
7421
struct drm_device *dev = crtc->dev;
7422
struct drm_i915_private *dev_priv = dev->dev_private;
7423
struct intel_framebuffer *intel_fb;
7424
struct drm_i915_gem_object *obj;
7425
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7426
struct intel_unpin_work *work;
7427
unsigned long flags;
7430
/* Can't change pixel format via MI display flips. */
7431
if (fb->pixel_format != crtc->fb->pixel_format)
7435
* TILEOFF/LINOFF registers can't be changed via MI display flips.
7436
* Note that pitch changes could also affect these register.
7438
if (INTEL_INFO(dev)->gen > 3 &&
7439
(fb->offsets[0] != crtc->fb->offsets[0] ||
7440
fb->pitches[0] != crtc->fb->pitches[0]))
7443
work = kzalloc(sizeof *work, GFP_KERNEL);
7447
work->event = event;
7449
intel_fb = to_intel_framebuffer(crtc->fb);
7450
work->old_fb_obj = intel_fb->obj;
7451
INIT_WORK(&work->work, intel_unpin_work_fn);
7453
ret = drm_vblank_get(dev, intel_crtc->pipe);
7457
/* We borrow the event spin lock for protecting unpin_work */
7458
spin_lock_irqsave(&dev->event_lock, flags);
7459
if (intel_crtc->unpin_work) {
7460
spin_unlock_irqrestore(&dev->event_lock, flags);
7462
drm_vblank_put(dev, intel_crtc->pipe);
7464
DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7467
intel_crtc->unpin_work = work;
7468
spin_unlock_irqrestore(&dev->event_lock, flags);
7470
intel_fb = to_intel_framebuffer(fb);
7471
obj = intel_fb->obj;
7473
if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7474
flush_workqueue(dev_priv->wq);
7476
ret = i915_mutex_lock_interruptible(dev);
7480
/* Reference the objects for the scheduled work. */
7481
drm_gem_object_reference(&work->old_fb_obj->base);
7482
drm_gem_object_reference(&obj->base);
7486
work->pending_flip_obj = obj;
7488
work->enable_stall_check = true;
7490
/* Block clients from rendering to the new back buffer until
7491
* the flip occurs and the object is no longer visible.
7493
atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7494
atomic_inc(&intel_crtc->unpin_work_count);
7496
ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7498
goto cleanup_pending;
7500
intel_disable_fbc(dev);
7501
intel_mark_fb_busy(obj);
7502
mutex_unlock(&dev->struct_mutex);
7504
trace_i915_flip_request(intel_crtc->plane, obj);
7509
atomic_dec(&intel_crtc->unpin_work_count);
7510
atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7511
drm_gem_object_unreference(&work->old_fb_obj->base);
7512
drm_gem_object_unreference(&obj->base);
7513
mutex_unlock(&dev->struct_mutex);
7516
spin_lock_irqsave(&dev->event_lock, flags);
7517
intel_crtc->unpin_work = NULL;
7518
spin_unlock_irqrestore(&dev->event_lock, flags);
7520
drm_vblank_put(dev, intel_crtc->pipe);
7527
static struct drm_crtc_helper_funcs intel_helper_funcs = {
7528
.mode_set_base_atomic = intel_pipe_set_base_atomic,
7529
.load_lut = intel_crtc_load_lut,
7530
.disable = intel_crtc_noop,
7533
bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7535
struct intel_encoder *other_encoder;
7536
struct drm_crtc *crtc = &encoder->new_crtc->base;
7541
list_for_each_entry(other_encoder,
7542
&crtc->dev->mode_config.encoder_list,
7545
if (&other_encoder->new_crtc->base != crtc ||
7546
encoder == other_encoder)
7555
static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7556
struct drm_crtc *crtc)
7558
struct drm_device *dev;
7559
struct drm_crtc *tmp;
7562
WARN(!crtc, "checking null crtc?\n");
7566
list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7572
if (encoder->possible_crtcs & crtc_mask)
7578
* intel_modeset_update_staged_output_state
7580
* Updates the staged output configuration state, e.g. after we've read out the
7583
static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7585
struct intel_encoder *encoder;
7586
struct intel_connector *connector;
7588
list_for_each_entry(connector, &dev->mode_config.connector_list,
7590
connector->new_encoder =
7591
to_intel_encoder(connector->base.encoder);
7594
list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7597
to_intel_crtc(encoder->base.crtc);
7602
* intel_modeset_commit_output_state
7604
* This function copies the stage display pipe configuration to the real one.
7606
static void intel_modeset_commit_output_state(struct drm_device *dev)
7608
struct intel_encoder *encoder;
7609
struct intel_connector *connector;
7611
list_for_each_entry(connector, &dev->mode_config.connector_list,
7613
connector->base.encoder = &connector->new_encoder->base;
7616
list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7618
encoder->base.crtc = &encoder->new_crtc->base;
7622
static struct drm_display_mode *
7623
intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7624
struct drm_display_mode *mode)
7626
struct drm_device *dev = crtc->dev;
7627
struct drm_display_mode *adjusted_mode;
7628
struct drm_encoder_helper_funcs *encoder_funcs;
7629
struct intel_encoder *encoder;
7631
adjusted_mode = drm_mode_duplicate(dev, mode);
7633
return ERR_PTR(-ENOMEM);
7635
/* Pass our mode to the connectors and the CRTC to give them a chance to
7636
* adjust it according to limitations or connector properties, and also
7637
* a chance to reject the mode entirely.
7639
list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7642
if (&encoder->new_crtc->base != crtc)
7644
encoder_funcs = encoder->base.helper_private;
7645
if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7647
DRM_DEBUG_KMS("Encoder fixup failed\n");
7652
if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7653
DRM_DEBUG_KMS("CRTC fixup failed\n");
7656
DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7658
return adjusted_mode;
7660
drm_mode_destroy(dev, adjusted_mode);
7661
return ERR_PTR(-EINVAL);
7664
/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7665
* simplicity we use the crtc's pipe number (because it's easier to obtain). */
7667
intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7668
unsigned *prepare_pipes, unsigned *disable_pipes)
7670
struct intel_crtc *intel_crtc;
7671
struct drm_device *dev = crtc->dev;
7672
struct intel_encoder *encoder;
7673
struct intel_connector *connector;
7674
struct drm_crtc *tmp_crtc;
7676
*disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7678
/* Check which crtcs have changed outputs connected to them, these need
7679
* to be part of the prepare_pipes mask. We don't (yet) support global
7680
* modeset across multiple crtcs, so modeset_pipes will only have one
7681
* bit set at most. */
7682
list_for_each_entry(connector, &dev->mode_config.connector_list,
7684
if (connector->base.encoder == &connector->new_encoder->base)
7687
if (connector->base.encoder) {
7688
tmp_crtc = connector->base.encoder->crtc;
7690
*prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7693
if (connector->new_encoder)
7695
1 << connector->new_encoder->new_crtc->pipe;
7698
list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7700
if (encoder->base.crtc == &encoder->new_crtc->base)
7703
if (encoder->base.crtc) {
7704
tmp_crtc = encoder->base.crtc;
7706
*prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7709
if (encoder->new_crtc)
7710
*prepare_pipes |= 1 << encoder->new_crtc->pipe;
7713
/* Check for any pipes that will be fully disabled ... */
7714
list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7718
/* Don't try to disable disabled crtcs. */
7719
if (!intel_crtc->base.enabled)
7722
list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7724
if (encoder->new_crtc == intel_crtc)
7729
*disable_pipes |= 1 << intel_crtc->pipe;
7733
/* set_mode is also used to update properties on life display pipes. */
7734
intel_crtc = to_intel_crtc(crtc);
7736
*prepare_pipes |= 1 << intel_crtc->pipe;
7738
/* We only support modeset on one single crtc, hence we need to do that
7739
* only for the passed in crtc iff we change anything else than just
7742
* This is actually not true, to be fully compatible with the old crtc
7743
* helper we automatically disable _any_ output (i.e. doesn't need to be
7744
* connected to the crtc we're modesetting on) if it's disconnected.
7745
* Which is a rather nutty api (since changed the output configuration
7746
* without userspace's explicit request can lead to confusion), but
7747
* alas. Hence we currently need to modeset on all pipes we prepare. */
7749
*modeset_pipes = *prepare_pipes;
7751
/* ... and mask these out. */
7752
*modeset_pipes &= ~(*disable_pipes);
7753
*prepare_pipes &= ~(*disable_pipes);
7756
static bool intel_crtc_in_use(struct drm_crtc *crtc)
7758
struct drm_encoder *encoder;
7759
struct drm_device *dev = crtc->dev;
7761
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7762
if (encoder->crtc == crtc)
7769
intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7771
struct intel_encoder *intel_encoder;
7772
struct intel_crtc *intel_crtc;
7773
struct drm_connector *connector;
7775
list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7777
if (!intel_encoder->base.crtc)
7780
intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7782
if (prepare_pipes & (1 << intel_crtc->pipe))
7783
intel_encoder->connectors_active = false;
7786
intel_modeset_commit_output_state(dev);
7788
/* Update computed state. */
7789
list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7791
intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7794
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7795
if (!connector->encoder || !connector->encoder->crtc)
7798
intel_crtc = to_intel_crtc(connector->encoder->crtc);
7800
if (prepare_pipes & (1 << intel_crtc->pipe)) {
7801
struct drm_property *dpms_property =
7802
dev->mode_config.dpms_property;
7804
connector->dpms = DRM_MODE_DPMS_ON;
7805
drm_connector_property_set_value(connector,
7809
intel_encoder = to_intel_encoder(connector->encoder);
7810
intel_encoder->connectors_active = true;
7816
#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7817
list_for_each_entry((intel_crtc), \
7818
&(dev)->mode_config.crtc_list, \
7820
if (mask & (1 <<(intel_crtc)->pipe)) \
7823
intel_modeset_check_state(struct drm_device *dev)
7825
struct intel_crtc *crtc;
7826
struct intel_encoder *encoder;
7827
struct intel_connector *connector;
7829
list_for_each_entry(connector, &dev->mode_config.connector_list,
7831
/* This also checks the encoder/connector hw state with the
7832
* ->get_hw_state callbacks. */
7833
intel_connector_check_state(connector);
7835
WARN(&connector->new_encoder->base != connector->base.encoder,
7836
"connector's staged encoder doesn't match current encoder\n");
7839
list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7841
bool enabled = false;
7842
bool active = false;
7843
enum pipe pipe, tracked_pipe;
7845
DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7846
encoder->base.base.id,
7847
drm_get_encoder_name(&encoder->base));
7849
WARN(&encoder->new_crtc->base != encoder->base.crtc,
7850
"encoder's stage crtc doesn't match current crtc\n");
7851
WARN(encoder->connectors_active && !encoder->base.crtc,
7852
"encoder's active_connectors set, but no crtc\n");
7854
list_for_each_entry(connector, &dev->mode_config.connector_list,
7856
if (connector->base.encoder != &encoder->base)
7859
if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7862
WARN(!!encoder->base.crtc != enabled,
7863
"encoder's enabled state mismatch "
7864
"(expected %i, found %i)\n",
7865
!!encoder->base.crtc, enabled);
7866
WARN(active && !encoder->base.crtc,
7867
"active encoder with no crtc\n");
7869
WARN(encoder->connectors_active != active,
7870
"encoder's computed active state doesn't match tracked active state "
7871
"(expected %i, found %i)\n", active, encoder->connectors_active);
7873
active = encoder->get_hw_state(encoder, &pipe);
7874
WARN(active != encoder->connectors_active,
7875
"encoder's hw state doesn't match sw tracking "
7876
"(expected %i, found %i)\n",
7877
encoder->connectors_active, active);
7879
if (!encoder->base.crtc)
7882
tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7883
WARN(active && pipe != tracked_pipe,
7884
"active encoder's pipe doesn't match"
7885
"(expected %i, found %i)\n",
7886
tracked_pipe, pipe);
7890
list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7892
bool enabled = false;
7893
bool active = false;
7895
DRM_DEBUG_KMS("[CRTC:%d]\n",
7896
crtc->base.base.id);
7898
WARN(crtc->active && !crtc->base.enabled,
7899
"active crtc, but not enabled in sw tracking\n");
7901
list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7903
if (encoder->base.crtc != &crtc->base)
7906
if (encoder->connectors_active)
7909
WARN(active != crtc->active,
7910
"crtc's computed active state doesn't match tracked active state "
7911
"(expected %i, found %i)\n", active, crtc->active);
7912
WARN(enabled != crtc->base.enabled,
7913
"crtc's computed enabled state doesn't match tracked enabled state "
7914
"(expected %i, found %i)\n", enabled, crtc->base.enabled);
7916
assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7920
bool intel_set_mode(struct drm_crtc *crtc,
7921
struct drm_display_mode *mode,
7922
int x, int y, struct drm_framebuffer *fb)
7924
struct drm_device *dev = crtc->dev;
7925
drm_i915_private_t *dev_priv = dev->dev_private;
7926
struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7927
struct intel_crtc *intel_crtc;
7928
unsigned disable_pipes, prepare_pipes, modeset_pipes;
7931
intel_modeset_affected_pipes(crtc, &modeset_pipes,
7932
&prepare_pipes, &disable_pipes);
7934
DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7935
modeset_pipes, prepare_pipes, disable_pipes);
7937
for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7938
intel_crtc_disable(&intel_crtc->base);
7940
saved_hwmode = crtc->hwmode;
7941
saved_mode = crtc->mode;
7943
/* Hack: Because we don't (yet) support global modeset on multiple
7944
* crtcs, we don't keep track of the new mode for more than one crtc.
7945
* Hence simply check whether any bit is set in modeset_pipes in all the
7946
* pieces of code that are not yet converted to deal with mutliple crtcs
7947
* changing their mode at the same time. */
7948
adjusted_mode = NULL;
7949
if (modeset_pipes) {
7950
adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7951
if (IS_ERR(adjusted_mode)) {
7956
for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7957
if (intel_crtc->base.enabled)
7958
dev_priv->display.crtc_disable(&intel_crtc->base);
7961
/* crtc->mode is already used by the ->mode_set callbacks, hence we need
7962
* to set it here already despite that we pass it down the callchain.
7967
/* Only after disabling all output pipelines that will be changed can we
7968
* update the the output configuration. */
7969
intel_modeset_update_state(dev, prepare_pipes);
7971
if (dev_priv->display.modeset_global_resources)
7972
dev_priv->display.modeset_global_resources(dev);
7974
/* Set up the DPLL and any encoders state that needs to adjust or depend
7977
for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7978
ret = !intel_crtc_mode_set(&intel_crtc->base,
7979
mode, adjusted_mode,
7985
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
7986
for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7987
dev_priv->display.crtc_enable(&intel_crtc->base);
7989
if (modeset_pipes) {
7990
/* Store real post-adjustment hardware mode. */
7991
crtc->hwmode = *adjusted_mode;
7993
/* Calculate and store various constants which
7994
* are later needed by vblank and swap-completion
7995
* timestamping. They are derived from true hwmode.
7997
drm_calc_timestamping_constants(crtc);
8000
/* FIXME: add subpixel order */
8002
drm_mode_destroy(dev, adjusted_mode);
8003
if (!ret && crtc->enabled) {
8004
crtc->hwmode = saved_hwmode;
8005
crtc->mode = saved_mode;
8007
intel_modeset_check_state(dev);
8013
#undef for_each_intel_crtc_masked
8015
static void intel_set_config_free(struct intel_set_config *config)
8020
kfree(config->save_connector_encoders);
8021
kfree(config->save_encoder_crtcs);
8025
static int intel_set_config_save_state(struct drm_device *dev,
8026
struct intel_set_config *config)
8028
struct drm_encoder *encoder;
8029
struct drm_connector *connector;
8032
config->save_encoder_crtcs =
8033
kcalloc(dev->mode_config.num_encoder,
8034
sizeof(struct drm_crtc *), GFP_KERNEL);
8035
if (!config->save_encoder_crtcs)
8038
config->save_connector_encoders =
8039
kcalloc(dev->mode_config.num_connector,
8040
sizeof(struct drm_encoder *), GFP_KERNEL);
8041
if (!config->save_connector_encoders)
8044
/* Copy data. Note that driver private data is not affected.
8045
* Should anything bad happen only the expected state is
8046
* restored, not the drivers personal bookkeeping.
8049
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8050
config->save_encoder_crtcs[count++] = encoder->crtc;
8054
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8055
config->save_connector_encoders[count++] = connector->encoder;
8061
static void intel_set_config_restore_state(struct drm_device *dev,
8062
struct intel_set_config *config)
8064
struct intel_encoder *encoder;
8065
struct intel_connector *connector;
8069
list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8071
to_intel_crtc(config->save_encoder_crtcs[count++]);
8075
list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8076
connector->new_encoder =
8077
to_intel_encoder(config->save_connector_encoders[count++]);
8082
intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8083
struct intel_set_config *config)
8086
/* We should be able to check here if the fb has the same properties
8087
* and then just flip_or_move it */
8088
if (set->crtc->fb != set->fb) {
8089
/* If we have no fb then treat it as a full mode set */
8090
if (set->crtc->fb == NULL) {
8091
DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8092
config->mode_changed = true;
8093
} else if (set->fb == NULL) {
8094
config->mode_changed = true;
8095
} else if (set->fb->depth != set->crtc->fb->depth) {
8096
config->mode_changed = true;
8097
} else if (set->fb->bits_per_pixel !=
8098
set->crtc->fb->bits_per_pixel) {
8099
config->mode_changed = true;
8101
config->fb_changed = true;
8104
if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8105
config->fb_changed = true;
8107
if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8108
DRM_DEBUG_KMS("modes are different, full mode set\n");
8109
drm_mode_debug_printmodeline(&set->crtc->mode);
8110
drm_mode_debug_printmodeline(set->mode);
8111
config->mode_changed = true;
8116
intel_modeset_stage_output_state(struct drm_device *dev,
8117
struct drm_mode_set *set,
8118
struct intel_set_config *config)
8120
struct drm_crtc *new_crtc;
8121
struct intel_connector *connector;
8122
struct intel_encoder *encoder;
8125
/* The upper layers ensure that we either disabl a crtc or have a list
8126
* of connectors. For paranoia, double-check this. */
8127
WARN_ON(!set->fb && (set->num_connectors != 0));
8128
WARN_ON(set->fb && (set->num_connectors == 0));
8131
list_for_each_entry(connector, &dev->mode_config.connector_list,
8133
/* Otherwise traverse passed in connector list and get encoders
8135
for (ro = 0; ro < set->num_connectors; ro++) {
8136
if (set->connectors[ro] == &connector->base) {
8137
connector->new_encoder = connector->encoder;
8142
/* If we disable the crtc, disable all its connectors. Also, if
8143
* the connector is on the changing crtc but not on the new
8144
* connector list, disable it. */
8145
if ((!set->fb || ro == set->num_connectors) &&
8146
connector->base.encoder &&
8147
connector->base.encoder->crtc == set->crtc) {
8148
connector->new_encoder = NULL;
8150
DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8151
connector->base.base.id,
8152
drm_get_connector_name(&connector->base));
8156
if (&connector->new_encoder->base != connector->base.encoder) {
8157
DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8158
config->mode_changed = true;
8161
/* Disable all disconnected encoders. */
8162
if (connector->base.status == connector_status_disconnected)
8163
connector->new_encoder = NULL;
8165
/* connector->new_encoder is now updated for all connectors. */
8167
/* Update crtc of enabled connectors. */
8169
list_for_each_entry(connector, &dev->mode_config.connector_list,
8171
if (!connector->new_encoder)
8174
new_crtc = connector->new_encoder->base.crtc;
8176
for (ro = 0; ro < set->num_connectors; ro++) {
8177
if (set->connectors[ro] == &connector->base)
8178
new_crtc = set->crtc;
8181
/* Make sure the new CRTC will work with the encoder */
8182
if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8186
connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8188
DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8189
connector->base.base.id,
8190
drm_get_connector_name(&connector->base),
8194
/* Check for any encoders that needs to be disabled. */
8195
list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8197
list_for_each_entry(connector,
8198
&dev->mode_config.connector_list,
8200
if (connector->new_encoder == encoder) {
8201
WARN_ON(!connector->new_encoder->new_crtc);
8206
encoder->new_crtc = NULL;
8208
/* Only now check for crtc changes so we don't miss encoders
8209
* that will be disabled. */
8210
if (&encoder->new_crtc->base != encoder->base.crtc) {
8211
DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8212
config->mode_changed = true;
8215
/* Now we've also updated encoder->new_crtc for all encoders. */
8220
static int intel_crtc_set_config(struct drm_mode_set *set)
8222
struct drm_device *dev;
8223
struct drm_mode_set save_set;
8224
struct intel_set_config *config;
8229
BUG_ON(!set->crtc->helper_private);
8234
/* The fb helper likes to play gross jokes with ->mode_set_config.
8235
* Unfortunately the crtc helper doesn't do much at all for this case,
8236
* so we have to cope with this madness until the fb helper is fixed up. */
8237
if (set->fb && set->num_connectors == 0)
8241
DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8242
set->crtc->base.id, set->fb->base.id,
8243
(int)set->num_connectors, set->x, set->y);
8245
DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8248
dev = set->crtc->dev;
8251
config = kzalloc(sizeof(*config), GFP_KERNEL);
8255
ret = intel_set_config_save_state(dev, config);
8259
save_set.crtc = set->crtc;
8260
save_set.mode = &set->crtc->mode;
8261
save_set.x = set->crtc->x;
8262
save_set.y = set->crtc->y;
8263
save_set.fb = set->crtc->fb;
8265
/* Compute whether we need a full modeset, only an fb base update or no
8266
* change at all. In the future we might also check whether only the
8267
* mode changed, e.g. for LVDS where we only change the panel fitter in
8269
intel_set_config_compute_mode_changes(set, config);
8271
ret = intel_modeset_stage_output_state(dev, set, config);
8275
if (config->mode_changed) {
8277
DRM_DEBUG_KMS("attempting to set mode from"
8279
drm_mode_debug_printmodeline(set->mode);
8282
if (!intel_set_mode(set->crtc, set->mode,
8283
set->x, set->y, set->fb)) {
8284
DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8285
set->crtc->base.id);
8289
} else if (config->fb_changed) {
8290
ret = intel_pipe_set_base(set->crtc,
8291
set->x, set->y, set->fb);
8294
intel_set_config_free(config);
8299
intel_set_config_restore_state(dev, config);
8301
/* Try to restore the config */
8302
if (config->mode_changed &&
8303
!intel_set_mode(save_set.crtc, save_set.mode,
8304
save_set.x, save_set.y, save_set.fb))
8305
DRM_ERROR("failed to restore config after modeset failure\n");
8308
intel_set_config_free(config);
8312
static const struct drm_crtc_funcs intel_crtc_funcs = {
8313
.cursor_set = intel_crtc_cursor_set,
8314
.cursor_move = intel_crtc_cursor_move,
8315
.gamma_set = intel_crtc_gamma_set,
8316
.set_config = intel_crtc_set_config,
8317
.destroy = intel_crtc_destroy,
8318
.page_flip = intel_crtc_page_flip,
8321
static void intel_cpu_pll_init(struct drm_device *dev)
8323
if (IS_HASWELL(dev))
8324
intel_ddi_pll_init(dev);
8327
static void intel_pch_pll_init(struct drm_device *dev)
8329
drm_i915_private_t *dev_priv = dev->dev_private;
8332
if (dev_priv->num_pch_pll == 0) {
8333
DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8337
for (i = 0; i < dev_priv->num_pch_pll; i++) {
8338
dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8339
dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8340
dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8344
static void intel_crtc_init(struct drm_device *dev, int pipe)
8346
drm_i915_private_t *dev_priv = dev->dev_private;
8347
struct intel_crtc *intel_crtc;
8350
intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8351
if (intel_crtc == NULL)
8354
drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8356
drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8357
for (i = 0; i < 256; i++) {
8358
intel_crtc->lut_r[i] = i;
8359
intel_crtc->lut_g[i] = i;
8360
intel_crtc->lut_b[i] = i;
8363
/* Swap pipes & planes for FBC on pre-965 */
8364
intel_crtc->pipe = pipe;
8365
intel_crtc->plane = pipe;
8366
intel_crtc->cpu_transcoder = pipe;
8367
if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8368
DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8369
intel_crtc->plane = !pipe;
8372
BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8373
dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8374
dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8375
dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8377
intel_crtc->bpp = 24; /* default for pre-Ironlake */
8379
drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8382
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8383
struct drm_file *file)
8385
struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8386
struct drm_mode_object *drmmode_obj;
8387
struct intel_crtc *crtc;
8389
if (!drm_core_check_feature(dev, DRIVER_MODESET))
8392
drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8393
DRM_MODE_OBJECT_CRTC);
8396
DRM_ERROR("no such CRTC id\n");
8400
crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8401
pipe_from_crtc_id->pipe = crtc->pipe;
8406
static int intel_encoder_clones(struct intel_encoder *encoder)
8408
struct drm_device *dev = encoder->base.dev;
8409
struct intel_encoder *source_encoder;
8413
list_for_each_entry(source_encoder,
8414
&dev->mode_config.encoder_list, base.head) {
8416
if (encoder == source_encoder)
8417
index_mask |= (1 << entry);
8419
/* Intel hw has only one MUX where enocoders could be cloned. */
8420
if (encoder->cloneable && source_encoder->cloneable)
8421
index_mask |= (1 << entry);
8429
static bool has_edp_a(struct drm_device *dev)
8431
struct drm_i915_private *dev_priv = dev->dev_private;
8433
if (!IS_MOBILE(dev))
8436
if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8440
(I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8446
static void intel_setup_outputs(struct drm_device *dev)
8448
struct drm_i915_private *dev_priv = dev->dev_private;
8449
struct intel_encoder *encoder;
8450
bool dpd_is_edp = false;
8453
has_lvds = intel_lvds_init(dev);
8454
if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8455
/* disable the panel fitter on everything but LVDS */
8456
I915_WRITE(PFIT_CONTROL, 0);
8459
if (!(IS_HASWELL(dev) &&
8460
(I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8461
intel_crt_init(dev);
8463
if (IS_HASWELL(dev)) {
8466
/* Haswell uses DDI functions to detect digital outputs */
8467
found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8468
/* DDI A only supports eDP */
8470
intel_ddi_init(dev, PORT_A);
8472
/* DDI B, C and D detection is indicated by the SFUSE_STRAP
8474
found = I915_READ(SFUSE_STRAP);
8476
if (found & SFUSE_STRAP_DDIB_DETECTED)
8477
intel_ddi_init(dev, PORT_B);
8478
if (found & SFUSE_STRAP_DDIC_DETECTED)
8479
intel_ddi_init(dev, PORT_C);
8480
if (found & SFUSE_STRAP_DDID_DETECTED)
8481
intel_ddi_init(dev, PORT_D);
8482
} else if (HAS_PCH_SPLIT(dev)) {
8484
dpd_is_edp = intel_dpd_is_edp(dev);
8487
intel_dp_init(dev, DP_A, PORT_A);
8489
if (I915_READ(HDMIB) & PORT_DETECTED) {
8490
/* PCH SDVOB multiplex with HDMIB */
8491
found = intel_sdvo_init(dev, PCH_SDVOB, true);
8493
intel_hdmi_init(dev, HDMIB, PORT_B);
8494
if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8495
intel_dp_init(dev, PCH_DP_B, PORT_B);
8498
if (I915_READ(HDMIC) & PORT_DETECTED)
8499
intel_hdmi_init(dev, HDMIC, PORT_C);
8501
if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8502
intel_hdmi_init(dev, HDMID, PORT_D);
8504
if (I915_READ(PCH_DP_C) & DP_DETECTED)
8505
intel_dp_init(dev, PCH_DP_C, PORT_C);
8507
if (I915_READ(PCH_DP_D) & DP_DETECTED)
8508
intel_dp_init(dev, PCH_DP_D, PORT_D);
8509
} else if (IS_VALLEYVIEW(dev)) {
8512
/* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8513
if (I915_READ(DP_C) & DP_DETECTED)
8514
intel_dp_init(dev, DP_C, PORT_C);
8516
if (I915_READ(SDVOB) & PORT_DETECTED) {
8517
/* SDVOB multiplex with HDMIB */
8518
found = intel_sdvo_init(dev, SDVOB, true);
8520
intel_hdmi_init(dev, SDVOB, PORT_B);
8521
if (!found && (I915_READ(DP_B) & DP_DETECTED))
8522
intel_dp_init(dev, DP_B, PORT_B);
8525
if (I915_READ(SDVOC) & PORT_DETECTED)
8526
intel_hdmi_init(dev, SDVOC, PORT_C);
8528
} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8531
if (I915_READ(SDVOB) & SDVO_DETECTED) {
8532
DRM_DEBUG_KMS("probing SDVOB\n");
8533
found = intel_sdvo_init(dev, SDVOB, true);
8534
if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8535
DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8536
intel_hdmi_init(dev, SDVOB, PORT_B);
8539
if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8540
DRM_DEBUG_KMS("probing DP_B\n");
8541
intel_dp_init(dev, DP_B, PORT_B);
8545
/* Before G4X SDVOC doesn't have its own detect register */
8547
if (I915_READ(SDVOB) & SDVO_DETECTED) {
8548
DRM_DEBUG_KMS("probing SDVOC\n");
8549
found = intel_sdvo_init(dev, SDVOC, false);
8552
if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8554
if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8555
DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8556
intel_hdmi_init(dev, SDVOC, PORT_C);
8558
if (SUPPORTS_INTEGRATED_DP(dev)) {
8559
DRM_DEBUG_KMS("probing DP_C\n");
8560
intel_dp_init(dev, DP_C, PORT_C);
8564
if (SUPPORTS_INTEGRATED_DP(dev) &&
8565
(I915_READ(DP_D) & DP_DETECTED)) {
8566
DRM_DEBUG_KMS("probing DP_D\n");
8567
intel_dp_init(dev, DP_D, PORT_D);
8569
} else if (IS_GEN2(dev))
8570
intel_dvo_init(dev);
8572
if (SUPPORTS_TV(dev))
8575
list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8576
encoder->base.possible_crtcs = encoder->crtc_mask;
8577
encoder->base.possible_clones =
8578
intel_encoder_clones(encoder);
8581
intel_init_pch_refclk(dev);
8583
drm_helper_move_panel_connectors_to_head(dev);
8586
static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8588
struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8590
drm_framebuffer_cleanup(fb);
8591
drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8596
static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8597
struct drm_file *file,
8598
unsigned int *handle)
8600
struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8601
struct drm_i915_gem_object *obj = intel_fb->obj;
8603
return drm_gem_handle_create(file, &obj->base, handle);
8606
static const struct drm_framebuffer_funcs intel_fb_funcs = {
8607
.destroy = intel_user_framebuffer_destroy,
8608
.create_handle = intel_user_framebuffer_create_handle,
8611
int intel_framebuffer_init(struct drm_device *dev,
8612
struct intel_framebuffer *intel_fb,
8613
struct drm_mode_fb_cmd2 *mode_cmd,
8614
struct drm_i915_gem_object *obj)
8618
if (obj->tiling_mode == I915_TILING_Y)
8621
if (mode_cmd->pitches[0] & 63)
8624
/* FIXME <= Gen4 stride limits are bit unclear */
8625
if (mode_cmd->pitches[0] > 32768)
8628
if (obj->tiling_mode != I915_TILING_NONE &&
8629
mode_cmd->pitches[0] != obj->stride)
8632
/* Reject formats not supported by any plane early. */
8633
switch (mode_cmd->pixel_format) {
8635
case DRM_FORMAT_RGB565:
8636
case DRM_FORMAT_XRGB8888:
8637
case DRM_FORMAT_ARGB8888:
8639
case DRM_FORMAT_XRGB1555:
8640
case DRM_FORMAT_ARGB1555:
8641
if (INTEL_INFO(dev)->gen > 3)
8644
case DRM_FORMAT_XBGR8888:
8645
case DRM_FORMAT_ABGR8888:
8646
case DRM_FORMAT_XRGB2101010:
8647
case DRM_FORMAT_ARGB2101010:
8648
case DRM_FORMAT_XBGR2101010:
8649
case DRM_FORMAT_ABGR2101010:
8650
if (INTEL_INFO(dev)->gen < 4)
8653
case DRM_FORMAT_YUYV:
8654
case DRM_FORMAT_UYVY:
8655
case DRM_FORMAT_YVYU:
8656
case DRM_FORMAT_VYUY:
8657
if (INTEL_INFO(dev)->gen < 6)
8661
DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8665
/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8666
if (mode_cmd->offsets[0] != 0)
8669
ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8671
DRM_ERROR("framebuffer init failed %d\n", ret);
8675
drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8676
intel_fb->obj = obj;
8680
static struct drm_framebuffer *
8681
intel_user_framebuffer_create(struct drm_device *dev,
8682
struct drm_file *filp,
8683
struct drm_mode_fb_cmd2 *mode_cmd)
8685
struct drm_i915_gem_object *obj;
8687
obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8688
mode_cmd->handles[0]));
8689
if (&obj->base == NULL)
8690
return ERR_PTR(-ENOENT);
8692
return intel_framebuffer_create(dev, mode_cmd, obj);
8695
static const struct drm_mode_config_funcs intel_mode_funcs = {
8696
.fb_create = intel_user_framebuffer_create,
8697
.output_poll_changed = intel_fb_output_poll_changed,
8700
/* Set up chip specific display functions */
8701
static void intel_init_display(struct drm_device *dev)
8703
struct drm_i915_private *dev_priv = dev->dev_private;
8705
/* We always want a DPMS function */
8706
if (IS_HASWELL(dev)) {
8707
dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8708
dev_priv->display.crtc_enable = haswell_crtc_enable;
8709
dev_priv->display.crtc_disable = haswell_crtc_disable;
8710
dev_priv->display.off = haswell_crtc_off;
8711
dev_priv->display.update_plane = ironlake_update_plane;
8712
} else if (HAS_PCH_SPLIT(dev)) {
8713
dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8714
dev_priv->display.crtc_enable = ironlake_crtc_enable;
8715
dev_priv->display.crtc_disable = ironlake_crtc_disable;
8716
dev_priv->display.off = ironlake_crtc_off;
8717
dev_priv->display.update_plane = ironlake_update_plane;
8719
dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8720
dev_priv->display.crtc_enable = i9xx_crtc_enable;
8721
dev_priv->display.crtc_disable = i9xx_crtc_disable;
8722
dev_priv->display.off = i9xx_crtc_off;
8723
dev_priv->display.update_plane = i9xx_update_plane;
8726
/* Returns the core display clock speed */
8727
if (IS_VALLEYVIEW(dev))
8728
dev_priv->display.get_display_clock_speed =
8729
valleyview_get_display_clock_speed;
8730
else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8731
dev_priv->display.get_display_clock_speed =
8732
i945_get_display_clock_speed;
8733
else if (IS_I915G(dev))
8734
dev_priv->display.get_display_clock_speed =
8735
i915_get_display_clock_speed;
8736
else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8737
dev_priv->display.get_display_clock_speed =
8738
i9xx_misc_get_display_clock_speed;
8739
else if (IS_I915GM(dev))
8740
dev_priv->display.get_display_clock_speed =
8741
i915gm_get_display_clock_speed;
8742
else if (IS_I865G(dev))
8743
dev_priv->display.get_display_clock_speed =
8744
i865_get_display_clock_speed;
8745
else if (IS_I85X(dev))
8746
dev_priv->display.get_display_clock_speed =
8747
i855_get_display_clock_speed;
8749
dev_priv->display.get_display_clock_speed =
8750
i830_get_display_clock_speed;
8752
if (HAS_PCH_SPLIT(dev)) {
8754
dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8755
dev_priv->display.write_eld = ironlake_write_eld;
8756
} else if (IS_GEN6(dev)) {
8757
dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8758
dev_priv->display.write_eld = ironlake_write_eld;
8759
} else if (IS_IVYBRIDGE(dev)) {
8760
/* FIXME: detect B0+ stepping and use auto training */
8761
dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8762
dev_priv->display.write_eld = ironlake_write_eld;
8763
dev_priv->display.modeset_global_resources =
8764
ivb_modeset_global_resources;
8765
} else if (IS_HASWELL(dev)) {
8766
dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8767
dev_priv->display.write_eld = haswell_write_eld;
8769
dev_priv->display.update_wm = NULL;
8770
} else if (IS_G4X(dev)) {
8771
dev_priv->display.write_eld = g4x_write_eld;
8774
/* Default just returns -ENODEV to indicate unsupported */
8775
dev_priv->display.queue_flip = intel_default_queue_flip;
8777
switch (INTEL_INFO(dev)->gen) {
8779
dev_priv->display.queue_flip = intel_gen2_queue_flip;
8783
dev_priv->display.queue_flip = intel_gen3_queue_flip;
8788
dev_priv->display.queue_flip = intel_gen4_queue_flip;
8792
dev_priv->display.queue_flip = intel_gen6_queue_flip;
8795
dev_priv->display.queue_flip = intel_gen7_queue_flip;
8801
* Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8802
* resume, or other times. This quirk makes sure that's the case for
8805
static void quirk_pipea_force(struct drm_device *dev)
8807
struct drm_i915_private *dev_priv = dev->dev_private;
8809
dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8810
DRM_INFO("applying pipe a force quirk\n");
8814
* Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8816
static void quirk_ssc_force_disable(struct drm_device *dev)
8818
struct drm_i915_private *dev_priv = dev->dev_private;
8819
dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8820
DRM_INFO("applying lvds SSC disable quirk\n");
8824
* A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8827
static void quirk_invert_brightness(struct drm_device *dev)
8829
struct drm_i915_private *dev_priv = dev->dev_private;
8830
dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8831
DRM_INFO("applying inverted panel brightness quirk\n");
8834
struct intel_quirk {
8836
int subsystem_vendor;
8837
int subsystem_device;
8838
void (*hook)(struct drm_device *dev);
8841
/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8842
struct intel_dmi_quirk {
8843
void (*hook)(struct drm_device *dev);
8844
const struct dmi_system_id (*dmi_id_list)[];
8847
static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8849
DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8853
static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8855
.dmi_id_list = &(const struct dmi_system_id[]) {
8857
.callback = intel_dmi_reverse_brightness,
8858
.ident = "NCR Corporation",
8859
.matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8860
DMI_MATCH(DMI_PRODUCT_NAME, ""),
8863
{ } /* terminating entry */
8865
.hook = quirk_invert_brightness,
8869
static struct intel_quirk intel_quirks[] = {
8870
/* HP Mini needs pipe A force quirk (LP: #322104) */
8871
{ 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8873
/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8874
{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8876
/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8877
{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8879
/* 830/845 need to leave pipe A & dpll A up */
8880
{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8881
{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8883
/* Lenovo U160 cannot use SSC on LVDS */
8884
{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8886
/* Sony Vaio Y cannot use SSC on LVDS */
8887
{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8889
/* Acer Aspire 5734Z must invert backlight brightness */
8890
{ 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8893
static void intel_init_quirks(struct drm_device *dev)
8895
struct pci_dev *d = dev->pdev;
8898
for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8899
struct intel_quirk *q = &intel_quirks[i];
8901
if (d->device == q->device &&
8902
(d->subsystem_vendor == q->subsystem_vendor ||
8903
q->subsystem_vendor == PCI_ANY_ID) &&
8904
(d->subsystem_device == q->subsystem_device ||
8905
q->subsystem_device == PCI_ANY_ID))
8908
for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8909
if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8910
intel_dmi_quirks[i].hook(dev);
8914
/* Disable the VGA plane that we never use */
8915
static void i915_disable_vga(struct drm_device *dev)
8917
struct drm_i915_private *dev_priv = dev->dev_private;
8921
if (HAS_PCH_SPLIT(dev))
8922
vga_reg = CPU_VGACNTRL;
8926
vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8927
outb(SR01, VGA_SR_INDEX);
8928
sr1 = inb(VGA_SR_DATA);
8929
outb(sr1 | 1<<5, VGA_SR_DATA);
8930
vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8933
I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8934
POSTING_READ(vga_reg);
8937
void intel_modeset_init_hw(struct drm_device *dev)
8939
/* We attempt to init the necessary power wells early in the initialization
8940
* time, so the subsystems that expect power to be enabled can work.
8942
intel_init_power_wells(dev);
8944
intel_prepare_ddi(dev);
8946
intel_init_clock_gating(dev);
8948
mutex_lock(&dev->struct_mutex);
8949
intel_enable_gt_powersave(dev);
8950
mutex_unlock(&dev->struct_mutex);
8953
void intel_modeset_init(struct drm_device *dev)
8955
struct drm_i915_private *dev_priv = dev->dev_private;
8958
drm_mode_config_init(dev);
8960
dev->mode_config.min_width = 0;
8961
dev->mode_config.min_height = 0;
8963
dev->mode_config.preferred_depth = 24;
8964
dev->mode_config.prefer_shadow = 1;
8966
dev->mode_config.funcs = &intel_mode_funcs;
8968
intel_init_quirks(dev);
8972
intel_init_display(dev);
8975
dev->mode_config.max_width = 2048;
8976
dev->mode_config.max_height = 2048;
8977
} else if (IS_GEN3(dev)) {
8978
dev->mode_config.max_width = 4096;
8979
dev->mode_config.max_height = 4096;
8981
dev->mode_config.max_width = 8192;
8982
dev->mode_config.max_height = 8192;
8984
dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8986
DRM_DEBUG_KMS("%d display pipe%s available.\n",
8987
dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8989
for (i = 0; i < dev_priv->num_pipe; i++) {
8990
intel_crtc_init(dev, i);
8991
ret = intel_plane_init(dev, i);
8993
DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8996
intel_cpu_pll_init(dev);
8997
intel_pch_pll_init(dev);
8999
/* Just disable it once at startup */
9000
i915_disable_vga(dev);
9001
intel_setup_outputs(dev);
9005
intel_connector_break_all_links(struct intel_connector *connector)
9007
connector->base.dpms = DRM_MODE_DPMS_OFF;
9008
connector->base.encoder = NULL;
9009
connector->encoder->connectors_active = false;
9010
connector->encoder->base.crtc = NULL;
9013
static void intel_enable_pipe_a(struct drm_device *dev)
9015
struct intel_connector *connector;
9016
struct drm_connector *crt = NULL;
9017
struct intel_load_detect_pipe load_detect_temp;
9019
/* We can't just switch on the pipe A, we need to set things up with a
9020
* proper mode and output configuration. As a gross hack, enable pipe A
9021
* by enabling the load detect pipe once. */
9022
list_for_each_entry(connector,
9023
&dev->mode_config.connector_list,
9025
if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9026
crt = &connector->base;
9034
if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9035
intel_release_load_detect_pipe(crt, &load_detect_temp);
9041
intel_check_plane_mapping(struct intel_crtc *crtc)
9043
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
9046
if (dev_priv->num_pipe == 1)
9049
reg = DSPCNTR(!crtc->plane);
9050
val = I915_READ(reg);
9052
if ((val & DISPLAY_PLANE_ENABLE) &&
9053
(!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9059
static void intel_sanitize_crtc(struct intel_crtc *crtc)
9061
struct drm_device *dev = crtc->base.dev;
9062
struct drm_i915_private *dev_priv = dev->dev_private;
9065
/* Clear any frame start delays used for debugging left by the BIOS */
9066
reg = PIPECONF(crtc->cpu_transcoder);
9067
I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9069
/* We need to sanitize the plane -> pipe mapping first because this will
9070
* disable the crtc (and hence change the state) if it is wrong. Note
9071
* that gen4+ has a fixed plane -> pipe mapping. */
9072
if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9073
struct intel_connector *connector;
9076
DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9077
crtc->base.base.id);
9079
/* Pipe has the wrong plane attached and the plane is active.
9080
* Temporarily change the plane mapping and disable everything
9082
plane = crtc->plane;
9083
crtc->plane = !plane;
9084
dev_priv->display.crtc_disable(&crtc->base);
9085
crtc->plane = plane;
9087
/* ... and break all links. */
9088
list_for_each_entry(connector, &dev->mode_config.connector_list,
9090
if (connector->encoder->base.crtc != &crtc->base)
9093
intel_connector_break_all_links(connector);
9096
WARN_ON(crtc->active);
9097
crtc->base.enabled = false;
9100
if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9101
crtc->pipe == PIPE_A && !crtc->active) {
9102
/* BIOS forgot to enable pipe A, this mostly happens after
9103
* resume. Force-enable the pipe to fix this, the update_dpms
9104
* call below we restore the pipe to the right state, but leave
9105
* the required bits on. */
9106
intel_enable_pipe_a(dev);
9109
/* Adjust the state of the output pipe according to whether we
9110
* have active connectors/encoders. */
9111
intel_crtc_update_dpms(&crtc->base);
9113
if (crtc->active != crtc->base.enabled) {
9114
struct intel_encoder *encoder;
9116
/* This can happen either due to bugs in the get_hw_state
9117
* functions or because the pipe is force-enabled due to the
9119
DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9121
crtc->base.enabled ? "enabled" : "disabled",
9122
crtc->active ? "enabled" : "disabled");
9124
crtc->base.enabled = crtc->active;
9126
/* Because we only establish the connector -> encoder ->
9127
* crtc links if something is active, this means the
9128
* crtc is now deactivated. Break the links. connector
9129
* -> encoder links are only establish when things are
9130
* actually up, hence no need to break them. */
9131
WARN_ON(crtc->active);
9133
for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9134
WARN_ON(encoder->connectors_active);
9135
encoder->base.crtc = NULL;
9140
static void intel_sanitize_encoder(struct intel_encoder *encoder)
9142
struct intel_connector *connector;
9143
struct drm_device *dev = encoder->base.dev;
9145
/* We need to check both for a crtc link (meaning that the
9146
* encoder is active and trying to read from a pipe) and the
9147
* pipe itself being active. */
9148
bool has_active_crtc = encoder->base.crtc &&
9149
to_intel_crtc(encoder->base.crtc)->active;
9151
if (encoder->connectors_active && !has_active_crtc) {
9152
DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9153
encoder->base.base.id,
9154
drm_get_encoder_name(&encoder->base));
9156
/* Connector is active, but has no active pipe. This is
9157
* fallout from our resume register restoring. Disable
9158
* the encoder manually again. */
9159
if (encoder->base.crtc) {
9160
DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9161
encoder->base.base.id,
9162
drm_get_encoder_name(&encoder->base));
9163
encoder->disable(encoder);
9166
/* Inconsistent output/port/pipe state happens presumably due to
9167
* a bug in one of the get_hw_state functions. Or someplace else
9168
* in our code, like the register restore mess on resume. Clamp
9169
* things to off as a safer default. */
9170
list_for_each_entry(connector,
9171
&dev->mode_config.connector_list,
9173
if (connector->encoder != encoder)
9176
intel_connector_break_all_links(connector);
9179
/* Enabled encoders without active connectors will be fixed in
9180
* the crtc fixup. */
9183
/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9184
* and i915 state tracking structures. */
9185
void intel_modeset_setup_hw_state(struct drm_device *dev)
9187
struct drm_i915_private *dev_priv = dev->dev_private;
9190
struct intel_crtc *crtc;
9191
struct intel_encoder *encoder;
9192
struct intel_connector *connector;
9194
if (IS_HASWELL(dev)) {
9195
tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9197
if (tmp & TRANS_DDI_FUNC_ENABLE) {
9198
switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9199
case TRANS_DDI_EDP_INPUT_A_ON:
9200
case TRANS_DDI_EDP_INPUT_A_ONOFF:
9203
case TRANS_DDI_EDP_INPUT_B_ONOFF:
9206
case TRANS_DDI_EDP_INPUT_C_ONOFF:
9211
crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9212
crtc->cpu_transcoder = TRANSCODER_EDP;
9214
DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9219
for_each_pipe(pipe) {
9220
crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9222
tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9223
if (tmp & PIPECONF_ENABLE)
9224
crtc->active = true;
9226
crtc->active = false;
9228
crtc->base.enabled = crtc->active;
9230
DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9232
crtc->active ? "enabled" : "disabled");
9235
if (IS_HASWELL(dev))
9236
intel_ddi_setup_hw_pll_state(dev);
9238
list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9242
if (encoder->get_hw_state(encoder, &pipe)) {
9243
encoder->base.crtc =
9244
dev_priv->pipe_to_crtc_mapping[pipe];
9246
encoder->base.crtc = NULL;
9249
encoder->connectors_active = false;
9250
DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9251
encoder->base.base.id,
9252
drm_get_encoder_name(&encoder->base),
9253
encoder->base.crtc ? "enabled" : "disabled",
9257
list_for_each_entry(connector, &dev->mode_config.connector_list,
9259
if (connector->get_hw_state(connector)) {
9260
connector->base.dpms = DRM_MODE_DPMS_ON;
9261
connector->encoder->connectors_active = true;
9262
connector->base.encoder = &connector->encoder->base;
9264
connector->base.dpms = DRM_MODE_DPMS_OFF;
9265
connector->base.encoder = NULL;
9267
DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9268
connector->base.base.id,
9269
drm_get_connector_name(&connector->base),
9270
connector->base.encoder ? "enabled" : "disabled");
9273
/* HW state is read out, now we need to sanitize this mess. */
9274
list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9276
intel_sanitize_encoder(encoder);
9279
for_each_pipe(pipe) {
9280
crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9281
intel_sanitize_crtc(crtc);
9284
intel_modeset_update_staged_output_state(dev);
9286
intel_modeset_check_state(dev);
9288
drm_mode_config_reset(dev);
9291
void intel_modeset_gem_init(struct drm_device *dev)
9293
intel_modeset_init_hw(dev);
9295
intel_setup_overlay(dev);
9297
intel_modeset_setup_hw_state(dev);
9300
void intel_modeset_cleanup(struct drm_device *dev)
9302
struct drm_i915_private *dev_priv = dev->dev_private;
9303
struct drm_crtc *crtc;
9304
struct intel_crtc *intel_crtc;
9306
drm_kms_helper_poll_fini(dev);
9307
mutex_lock(&dev->struct_mutex);
9309
intel_unregister_dsm_handler();
9312
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9313
/* Skip inactive CRTCs */
9317
intel_crtc = to_intel_crtc(crtc);
9318
intel_increase_pllclock(crtc);
9321
intel_disable_fbc(dev);
9323
intel_disable_gt_powersave(dev);
9325
ironlake_teardown_rc6(dev);
9327
if (IS_VALLEYVIEW(dev))
9330
mutex_unlock(&dev->struct_mutex);
9332
/* Disable the irq before mode object teardown, for the irq might
9333
* enqueue unpin/hotplug work. */
9334
drm_irq_uninstall(dev);
9335
cancel_work_sync(&dev_priv->hotplug_work);
9336
cancel_work_sync(&dev_priv->rps.work);
9338
/* flush any delayed tasks or pending work */
9339
flush_scheduled_work();
9341
drm_mode_config_cleanup(dev);
9345
* Return which encoder is currently attached for connector.
9347
struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9349
return &intel_attached_encoder(connector)->base;
9352
void intel_connector_attach_encoder(struct intel_connector *connector,
9353
struct intel_encoder *encoder)
9355
connector->encoder = encoder;
9356
drm_mode_connector_attach_encoder(&connector->base,
9361
* set vga decode state - true == enable VGA decode
9363
int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9365
struct drm_i915_private *dev_priv = dev->dev_private;
9368
pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9370
gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9372
gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9373
pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9377
#ifdef CONFIG_DEBUG_FS
9378
#include <linux/seq_file.h>
9380
struct intel_display_error_state {
9381
struct intel_cursor_error_state {
9386
} cursor[I915_MAX_PIPES];
9388
struct intel_pipe_error_state {
9398
} pipe[I915_MAX_PIPES];
9400
struct intel_plane_error_state {
9408
} plane[I915_MAX_PIPES];
9411
struct intel_display_error_state *
9412
intel_display_capture_error_state(struct drm_device *dev)
9414
drm_i915_private_t *dev_priv = dev->dev_private;
9415
struct intel_display_error_state *error;
9416
enum transcoder cpu_transcoder;
9419
error = kmalloc(sizeof(*error), GFP_ATOMIC);
9424
cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9426
error->cursor[i].control = I915_READ(CURCNTR(i));
9427
error->cursor[i].position = I915_READ(CURPOS(i));
9428
error->cursor[i].base = I915_READ(CURBASE(i));
9430
error->plane[i].control = I915_READ(DSPCNTR(i));
9431
error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9432
error->plane[i].size = I915_READ(DSPSIZE(i));
9433
error->plane[i].pos = I915_READ(DSPPOS(i));
9434
error->plane[i].addr = I915_READ(DSPADDR(i));
9435
if (INTEL_INFO(dev)->gen >= 4) {
9436
error->plane[i].surface = I915_READ(DSPSURF(i));
9437
error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9440
error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9441
error->pipe[i].source = I915_READ(PIPESRC(i));
9442
error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9443
error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9444
error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9445
error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9446
error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9447
error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9454
intel_display_print_error_state(struct seq_file *m,
9455
struct drm_device *dev,
9456
struct intel_display_error_state *error)
9458
drm_i915_private_t *dev_priv = dev->dev_private;
9461
seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9463
seq_printf(m, "Pipe [%d]:\n", i);
9464
seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9465
seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9466
seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9467
seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9468
seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9469
seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9470
seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9471
seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9473
seq_printf(m, "Plane [%d]:\n", i);
9474
seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9475
seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9476
seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9477
seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9478
seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9479
if (INTEL_INFO(dev)->gen >= 4) {
9480
seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9481
seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9484
seq_printf(m, "Cursor [%d]:\n", i);
9485
seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9486
seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9487
seq_printf(m, " BASE: %08x\n", error->cursor[i].base);