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Viewing changes to ports/sysdeps/unix/sysv/linux/arm/nptl/bits/atomic.h

  • Committer: Package Import Robot
  • Author(s): Adam Conrad
  • Date: 2013-01-10 18:39:35 UTC
  • mfrom: (1.5.2) (4.4.24 experimental)
  • Revision ID: package-import@ubuntu.com-20130110183935-afsgfxkmg7wk5eaj
Tags: 2.17-0ubuntu1
https://launchpad.net/bugs/1085342
https://launchpad.net/bugs/613662
* Merge with Debian, bringing in a new upstream and many small fixes:
  - patches/any/cvs-malloc-deadlock.diff: Dropped, merged upstream.
  - patches/ubuntu/lddebug-scopes.diff: Rebase for upstream changes.
  - patches/ubuntu/local-CVE-2012-3406.diff: Rebased against upstream.
  - patches/ubuntu/no-asm-mtune-i686.diff: Fixed in recent binutils.
* This upstream merge fixes a nasty hang in pulseaudio (LP: #1085342)
* Bump MIN_KERNEL_SUPPORTED to 2.6.32 on ARM, now that we no longer
  have to support shonky 2.6.31 kernels on imx51 babbage builders.
* Drop patches/ubuntu/local-disable-nscd-host-caching.diff, as these
  issues were apparently resolved upstream a while ago (LP: #613662)
* Fix the compiled-in bug URL to point to launchpad.net, not Debian.

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ports/sysdeps/unix/sysv/linux/arm/nptl/bits/atomic.h
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/* Copyright (C) 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
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   This file is part of the GNU C Library.
3
 
 
4
 
   The GNU C Library is free software; you can redistribute it and/or
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   modify it under the terms of the GNU Lesser General Public
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   License as published by the Free Software Foundation; either
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   version 2.1 of the License, or (at your option) any later version.
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   The GNU C Library is distributed in the hope that it will be useful,
10
 
   but WITHOUT ANY WARRANTY; without even the implied warranty of
11
 
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12
 
   Lesser General Public License for more details.
13
 
 
14
 
   You should have received a copy of the GNU Lesser General Public
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   License along with the GNU C Library.  If not, see
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   <http://www.gnu.org/licenses/>.  */
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#include <stdint.h>
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21
 
typedef int8_t atomic8_t;
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typedef uint8_t uatomic8_t;
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typedef int_fast8_t atomic_fast8_t;
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typedef uint_fast8_t uatomic_fast8_t;
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typedef int32_t atomic32_t;
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typedef uint32_t uatomic32_t;
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typedef int_fast32_t atomic_fast32_t;
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typedef uint_fast32_t uatomic_fast32_t;
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typedef intptr_t atomicptr_t;
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typedef uintptr_t uatomicptr_t;
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typedef intmax_t atomic_max_t;
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typedef uintmax_t uatomic_max_t;
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void __arm_link_error (void);
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/* Use the atomic builtins provided by GCC in case the backend provides
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   a pattern to do this efficiently.  */
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#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
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#define atomic_full_barrier() __sync_synchronize ()
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#elif defined __thumb2__
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#define atomic_full_barrier() \
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     __asm__ __volatile__                                                     \
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             ("movw\tip, #0x0fa0\n\t"                                         \
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              "movt\tip, #0xffff\n\t"                                         \
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              "blx\tip"                                                       \
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              : : : "ip", "lr", "cc", "memory");
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#else
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#define atomic_full_barrier() \
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     __asm__ __volatile__                                                     \
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             ("mov\tip, #0xffff0fff\n\t"                                      \
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              "mov\tlr, pc\n\t"                                               \
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              "add\tpc, ip, #(0xffff0fa0 - 0xffff0fff)"                       \
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              : : : "ip", "lr", "cc", "memory");
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#endif
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/* Atomic compare and exchange.  This sequence relies on the kernel to
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   provide a compare and exchange operation which is atomic on the
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   current architecture, either via cleverness on pre-ARMv6 or via
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   ldrex / strex on ARMv6.  */
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#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
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  ({ __arm_link_error (); oldval; })
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#define __arch_compare_and_exchange_val_16_acq(mem, newval, oldval) \
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  ({ __arm_link_error (); oldval; })
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#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
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#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
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  __sync_val_compare_and_swap ((mem), (oldval), (newval))
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/* It doesn't matter what register is used for a_oldval2, but we must
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   specify one to work around GCC PR rtl-optimization/21223.  Otherwise
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   it may cause a_oldval or a_tmp to be moved to a different register.  */
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#elif defined __thumb2__
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/* Thumb-2 has ldrex/strex.  However it does not have barrier instructions,
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   so we still need to use the kernel helper.  */
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#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
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  ({ register __typeof (oldval) a_oldval asm ("r0");                          \
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     register __typeof (oldval) a_newval asm ("r1") = (newval);               \
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     register __typeof (mem) a_ptr asm ("r2") = (mem);                        \
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     register __typeof (oldval) a_tmp asm ("r3");                             \
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     register __typeof (oldval) a_oldval2 asm ("r4") = (oldval);              \
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     __asm__ __volatile__                                                     \
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             ("0:\tldr\t%[tmp],[%[ptr]]\n\t"                                  \
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              "cmp\t%[tmp], %[old2]\n\t"                                      \
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              "bne\t1f\n\t"                                                   \
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              "mov\t%[old], %[old2]\n\t"                                      \
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              "movw\t%[tmp], #0x0fc0\n\t"                                     \
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              "movt\t%[tmp], #0xffff\n\t"                                     \
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              "blx\t%[tmp]\n\t"                                               \
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              "bcc\t0b\n\t"                                                   \
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              "mov\t%[tmp], %[old2]\n\t"                                      \
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              "1:"                                                            \
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              : [old] "=&r" (a_oldval), [tmp] "=&r" (a_tmp)                   \
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              : [new] "r" (a_newval), [ptr] "r" (a_ptr),                      \
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                [old2] "r" (a_oldval2)                                        \
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              : "ip", "lr", "cc", "memory");                                  \
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     a_tmp; })
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#else
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#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
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  ({ register __typeof (oldval) a_oldval asm ("r0");                          \
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     register __typeof (oldval) a_newval asm ("r1") = (newval);               \
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     register __typeof (mem) a_ptr asm ("r2") = (mem);                        \
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     register __typeof (oldval) a_tmp asm ("r3");                             \
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     register __typeof (oldval) a_oldval2 asm ("r4") = (oldval);              \
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     __asm__ __volatile__                                                     \
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             ("0:\tldr\t%[tmp],[%[ptr]]\n\t"                                  \
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              "cmp\t%[tmp], %[old2]\n\t"                                      \
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              "bne\t1f\n\t"                                                   \
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              "mov\t%[old], %[old2]\n\t"                                      \
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              "mov\t%[tmp], #0xffff0fff\n\t"                                  \
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              "mov\tlr, pc\n\t"                                               \
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              "add\tpc, %[tmp], #(0xffff0fc0 - 0xffff0fff)\n\t"               \
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              "bcc\t0b\n\t"                                                   \
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              "mov\t%[tmp], %[old2]\n\t"                                      \
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              "1:"                                                            \
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              : [old] "=&r" (a_oldval), [tmp] "=&r" (a_tmp)                   \
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              : [new] "r" (a_newval), [ptr] "r" (a_ptr),                      \
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                [old2] "r" (a_oldval2)                                        \
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              : "ip", "lr", "cc", "memory");                                  \
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     a_tmp; })
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#endif
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#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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  ({ __arm_link_error (); oldval; })