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  • Committer: Package Import Robot
  • Author(s): Enrique Hernández Bello
  • Date: 2012-11-11 21:38:56 UTC
  • mfrom: (1.1.5)
  • Revision ID: package-import@ubuntu.com-20121111213856-0825ywdrtdcshl91
Tags: 0.7.10b-1
http://bugs.debian.org/661495
http://bugs.debian.org/692998
* New upstream version. Closes: #661495, #692998
* Removed useless patches.
* Removed SetupAPI.lib from sourceless files.
* Skip dfsg tarball creation if there are no sourceless files.
* Added libqt4-sql-sqlite to dependencies. Thanks to Tom Hummel <tom@bluespice.org>.

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parts/core/SMD_Vreg_7805.fzp
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<?xml version="1.0" encoding="UTF-8"?><module fritzingVersion="0.1.1255" moduleId="1238DBdfgDC00-vofdghfhjaer">
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 <version>4</version>
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 <author>Mr.T</author>
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 <title>Voltage Regulator - 5V</title>
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 <label>U</label>
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 <date>2011-01-18</date>
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 <tags>
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  <tag>transistor</tag>
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  <tag>7805</tag>
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  <tag>power</tag>
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  <tag>aplifier</tag>
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  <tag>fritzing core</tag>
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 <tag>SMD</tag></tags>
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 <properties>
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  <property name="package">DPak [SMD]</property>
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  <property name="voltage">5V</property>
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  <property name="family">Voltage Regulator</property>
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 </properties>
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 <description>5V DC Voltage Regulator</description>
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 <views>
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  <iconView>
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   <layers image="icon/voltage_regulator_vreg_icon.svg">
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    <layer layerId="icon"/>
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   </layers>
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  </iconView>
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  <breadboardView>
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   <layers image="breadboard/voltage_regulator_vreg.svg">
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    <layer layerId="breadboard"/>
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   </layers>
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  </breadboardView>
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  <schematicView>
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   <layers image="schematic/voltage_regulator_5v.svg">
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    <layer layerId="schematic"/>
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   </layers>
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  </schematicView>
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  <pcbView>
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   <layers image="pcb/SMD_DPak.svg">
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    <layer layerId="silkscreen"/>
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   <layer layerId="copper1"/></layers>
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  </pcbView>
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 </views>
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 <connectors>
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  <connector id="connector0" name="input voltage" type="male">
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   <description>input</description>
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   <views>
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    <breadboardView>
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     <p layer="breadboard" svgId="connector0pin"  legId="connector0leg"/>
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    </breadboardView>
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    <schematicView>
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     <p layer="schematic" svgId="connector0pin" terminalId="connector0terminal"/>
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    </schematicView>
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    <pcbView>
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    <p layer="copper1" svgId="connector0pad"/></pcbView>
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   </views>
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  </connector>
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  <connector id="connector1" name="GND" type="male">
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   <description>ground</description>
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   <views>
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    <breadboardView>
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     <p layer="breadboard" svgId="connector1pin" legId="connector1leg"/>
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    </breadboardView>
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    <schematicView>
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     <p layer="schematic" svgId="connector1pin" terminalId="connector1terminal"/>
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    </schematicView>
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    <pcbView>
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    <p layer="copper1" svgId="connector1pad"/></pcbView>
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   </views>
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  </connector>
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  <connector id="connector2" name="output voltage" type="male">
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   <description>output voltage</description>
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   <views>
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    <breadboardView>
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     <p layer="breadboard" svgId="connector2pin" legId="connector2leg" />
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    </breadboardView>
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    <schematicView>
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     <p layer="schematic" svgId="connector2pin" terminalId="connector2terminal"/>
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    </schematicView>
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    <pcbView>
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    <p layer="copper1" svgId="connector2pad"/></pcbView>
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   </views>
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  </connector>
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 </connectors>
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</module>
 
 
b'\\ No newline at end of file'