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<?xml version="1.0" encoding="UTF-8"?><module fritzingVersion="0.3.6b.08.14.3340" moduleId="a7b011d4-01c1-4879-bb6a-93483b7c211c4">
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<title>74HC595 SMD</title>
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<date>2010-09-24</date>
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<tag>Shift Register</tag>
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<property name="family">Logic IC</property>
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<property name="logic family">74xx</property>
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<property name="package">SO16 [SMD]</property>
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<description>8-bit parallel-load shift registers</description>
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<layers image="icon/74HC595.svg">
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<layer layerId="icon"/>
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<layers image="breadboard/74HC595.svg">
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<layer layerId="breadboard"/>
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<layers image="pcb/SMD_SO16_DT.svg">
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<layer layerId="silkscreen"/>
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<layer layerId="copper1"/></layers>
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<layers image="schematic/74HC595.svg">
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<layer layerId="schematic"/>
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<connector id="connector15" name="VCC" type="male">
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<description>Positive supply voltage</description>
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<p layer="breadboard" svgId="connector15pin" terminalId="connector15terminal"/>
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<p layer="schematic" svgId="connector15pin" terminalId="connector15terminal"/>
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<p layer="copper1" svgId="connector15pin"/></pcbView>
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<connector id="connector3" name="Q4" type="male">
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<description>Output Pin</description>
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<p layer="breadboard" svgId="connector3pin" terminalId="connector3terminal"/>
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<p layer="schematic" svgId="connector3pin" terminalId="connector3terminal"/>
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<p layer="copper1" svgId="connector3pin"/></pcbView>
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<connector id="connector4" name="Q5" type="male">
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<description>Output Pin</description>
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<p layer="breadboard" svgId="connector4pin" terminalId="connector4terminal"/>
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<p layer="schematic" svgId="connector4pin" terminalId="connector4terminal"/>
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<p layer="copper1" svgId="connector4pin"/></pcbView>
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<connector id="connector5" name="Q6" type="male">
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<description>Output Pin</description>
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<p layer="breadboard" svgId="connector5pin" terminalId="connector5terminal"/>
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<p layer="schematic" svgId="connector5pin" terminalId="connector5terminal"/>
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<p layer="copper1" svgId="connector5pin"/></pcbView>
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<connector id="connector6" name="Q7" type="male">
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<description>Output Pin</description>
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<p layer="breadboard" svgId="connector6pin" terminalId="connector6terminal"/>
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<p layer="schematic" svgId="connector6pin" terminalId="connector6terminal"/>
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<p layer="copper1" svgId="connector6pin"/></pcbView>
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<connector id="connector7" name="GND" type="male">
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<description>Ground</description>
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<p layer="breadboard" svgId="connector7pin" terminalId="connector7terminal"/>
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<p layer="schematic" svgId="connector7pin" terminalId="connector7terminal"/>
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<p layer="copper1" svgId="connector7pin"/></pcbView>
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<connector id="connector8" name="Q7'" type="male">
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<description>Serial Out</description>
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<p layer="breadboard" svgId="connector8pin" terminalId="connector8terminal"/>
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<p layer="schematic" svgId="connector8pin" terminalId="connector8terminal"/>
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<p layer="copper1" svgId="connector8pin"/></pcbView>
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<connector id="connector9" name="MR" type="male">
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<description>Master Reclear, active low</description>
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<p layer="breadboard" svgId="connector9pin" terminalId="connector9terminal"/>
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<p layer="schematic" svgId="connector9pin" terminalId="connector9terminal"/>
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<p layer="copper1" svgId="connector9pin"/></pcbView>
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<connector id="connector10" name="SH_CP" type="male">
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<description>Shift register clock pin</description>
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<p layer="breadboard" svgId="connector10pin" terminalId="connector10terminal"/>
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<p layer="schematic" svgId="connector10pin" terminalId="connector10terminal"/>
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<p layer="copper1" svgId="connector10pin"/></pcbView>
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<connector id="connector11" name="ST_CP" type="male">
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<description>Storage register clock pin (latch pin)</description>
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<p layer="breadboard" svgId="connector11pin" terminalId="connector11terminal"/>
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<p layer="schematic" svgId="connector11pin" terminalId="connector11terminal"/>
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<p layer="copper1" svgId="connector11pin"/></pcbView>
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<connector id="connector12" name="OE" type="male">
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<description>Output enable, active low</description>
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<p layer="breadboard" svgId="connector12pin" terminalId="connector12terminal"/>
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<p layer="schematic" svgId="connector12pin" terminalId="connector12terminal"/>
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<p layer="copper1" svgId="connector12pin"/></pcbView>
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<connector id="connector0" name="Q1" type="male">
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<description>Output Pin</description>
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<p layer="breadboard" svgId="connector0pin" terminalId="connector0terminal"/>
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<p layer="schematic" svgId="connector0pin" terminalId="connector0terminal"/>
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<p layer="copper1" svgId="connector0pin"/></pcbView>
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<connector id="connector1" name="Q2" type="male">
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<description>Output Pin</description>
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<p layer="breadboard" svgId="connector1pin" terminalId="connector1terminal"/>
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<p layer="schematic" svgId="connector1pin" terminalId="connector1terminal"/>
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<p layer="copper1" svgId="connector1pin"/></pcbView>
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<connector id="connector13" name="DS" type="male">
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<description>Serial data input</description>
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<p layer="breadboard" svgId="connector13pin" terminalId="connector13terminal"/>
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<p layer="schematic" svgId="connector13pin" terminalId="connector13terminal"/>
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<p layer="copper1" svgId="connector13pin"/></pcbView>
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<connector id="connector14" name="Q0" type="male">
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<description>Output Pin</description>
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<p layer="breadboard" svgId="connector14pin" terminalId="connector14terminal"/>
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<p layer="schematic" svgId="connector14pin" terminalId="connector14terminal"/>
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<p layer="copper1" svgId="connector14pin"/></pcbView>
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<connector id="connector2" name="Q3" type="male">
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<description>Output Pin</description>
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<p layer="breadboard" svgId="connector2pin" terminalId="connector2terminal"/>
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<p layer="schematic" svgId="connector2pin" terminalId="connector2terminal"/>
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<p layer="copper1" svgId="connector2pin"/></pcbView>
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