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  • Committer: Package Import Robot
  • Author(s): Enrique Hernández Bello
  • Date: 2012-11-11 21:38:56 UTC
  • mfrom: (1.1.5)
  • Revision ID: package-import@ubuntu.com-20121111213856-0825ywdrtdcshl91
Tags: 0.7.10b-1
http://bugs.debian.org/661495
http://bugs.debian.org/692998
* New upstream version. Closes: #661495, #692998
* Removed useless patches.
* Removed SetupAPI.lib from sourceless files.
* Skip dfsg tarball creation if there are no sourceless files.
* Added libqt4-sql-sqlite to dependencies. Thanks to Tom Hummel <tom@bluespice.org>.

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parts/obsolete/capacitor_tantalum_100uF.fzp
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<?xml version="1.0" encoding="UTF-8"?><module fritzingVersion="0.3.18" moduleId="f9asdf12ce2b49029499a70593456637">
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    <version replacedby="100milTantalumCapacitorModuleID">4</version>
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    <author>Don Roberts (blog.gogozer.net)</author>
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    <title>Tantalum Capacitor</title>
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    <label>C</label>
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    <date>2009-09-25</date>
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    <tags>
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        <tag>capacitor tantalum</tag>
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        <tag>capacitor</tag>
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        <tag>fritzing core</tag>
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    </tags>
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    <properties>
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  <property name="family">Capacitor</property>
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  <property name="Capacitance">100&#181;F</property>
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  <property name="Capacitor Type">Tantalum</property>
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  <property name="Rated Voltage">35V</property>
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    <property name="package">THT</property></properties>
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    <description>Tantalum capacitor.  Plus lead is usually marked and is usually the longer lead.</description>
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    <views>
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        <iconView>
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            <layers image="icon/capacitor_tantalum.svg">
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                <layer layerId="icon"/>
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            </layers>
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        </iconView>
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        <breadboardView>
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            <layers image="breadboard/capacitor_tantalum.svg">
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                <layer layerId="breadboard"/>
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            </layers>
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        </breadboardView>
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        <schematicView>
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            <layers image="schematic/capacitor_polar.svg">
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                <layer layerId="schematic"/>
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            </layers>
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        </schematicView>
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        <pcbView>
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            <layers image="pcb/radial_can_200mil.svg">
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                <layer layerId="copper0"/>
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              <layer layerId="silkscreen"/>
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            <layer layerId="copper1"/></layers>
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        </pcbView>
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    </views>
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    <connectors>
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        <connector id="connector0" name="-" type="male">
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            <description>negative side</description>
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            <views>
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                <breadboardView>
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                    <p layer="breadboard" svgId="connector0pin" terminalId="connector0terminal"/>
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                </breadboardView>
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                <schematicView>
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                    <p layer="schematic" svgId="connector0pin" terminalId="connector0terminal"/>
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                </schematicView>
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                <pcbView>
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                    <p layer="copper0" svgId="connector0pin"/>
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                <p layer="copper1" svgId="connector0pin"/></pcbView>
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            </views>
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        </connector>
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        <connector id="connector1" name="+" type="male">
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            <description>positive side</description>
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            <views>
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                <breadboardView>
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                    <p layer="breadboard" svgId="connector1pin" terminalId="connector1terminal"/>
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                </breadboardView>
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                <schematicView>
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                    <p layer="schematic" svgId="connector1pin" terminalId="connector1terminal"/>
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                </schematicView>
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                <pcbView>
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                    <p layer="copper0" svgId="connector1pin"/>
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                <p layer="copper1" svgId="connector1pin"/></pcbView>
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            </views>
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        </connector>
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    </connectors>
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</module>
 
 
b'\\ No newline at end of file'