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// SPDX-License-Identifier: GPL-2.0-only
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* HD-audio stream operations
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/clocksource.h>
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#include <dkms/sound/core.h>
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#include <dkms/sound/pcm.h>
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#include <dkms/sound/hdaudio.h>
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#include <dkms/sound/hda_register.h>
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* snd_hdac_get_stream_stripe_ctl - get stripe control value
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* @bus: HD-audio core bus
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* @substream: PCM substream
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int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
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struct snd_pcm_substream *substream)
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struct snd_pcm_runtime *runtime = substream->runtime;
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unsigned int channels = runtime->channels,
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bits_per_sample = runtime->sample_bits,
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max_sdo_lines, value, sdo_line;
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/* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
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max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
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/* following is from HD audio spec */
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for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
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value = (channels * bits_per_sample *
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(rate / 48000)) / sdo_line;
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value = (channels * bits_per_sample) / sdo_line;
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/* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
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EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
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* snd_hdac_stream_init - initialize each stream (aka device)
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* @bus: HD-audio core bus
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* @azx_dev: HD-audio core stream object to initialize
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* @idx: stream index number
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* @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
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* @tag: the tag id to assign
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* Assign the starting bdl address to each stream (device) and initialize.
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void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
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int idx, int direction, int tag)
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/* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
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azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
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/* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
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azx_dev->sd_int_sta_mask = 1 << idx;
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azx_dev->direction = direction;
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azx_dev->stream_tag = tag;
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snd_hdac_dsp_lock_init(azx_dev);
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list_add_tail(&azx_dev->list, &bus->stream_list);
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EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
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* snd_hdac_stream_start - start a stream
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* @azx_dev: HD-audio core stream to start
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* @fresh_start: false = wallclock timestamp relative to period wallclock
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* Start a stream, set start_wallclk and set the running flag.
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void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
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struct hdac_bus *bus = azx_dev->bus;
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trace_snd_hdac_stream_start(bus, azx_dev);
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azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
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azx_dev->start_wallclk -= azx_dev->period_wallclk;
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snd_hdac_chip_updatel(bus, INTCTL,
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/* set stripe control */
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if (azx_dev->substream)
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stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
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snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
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/* set DMA start and interrupt mask */
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snd_hdac_stream_updateb(azx_dev, SD_CTL,
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0, SD_CTL_DMA_START | SD_INT_MASK);
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azx_dev->running = true;
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EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
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* snd_hdac_stream_clear - stop a stream DMA
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* @azx_dev: HD-audio core stream to stop
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void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
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snd_hdac_stream_updateb(azx_dev, SD_CTL,
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SD_CTL_DMA_START | SD_INT_MASK, 0);
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snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
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snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
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azx_dev->running = false;
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EXPORT_SYMBOL_GPL(snd_hdac_stream_clear);
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* snd_hdac_stream_stop - stop a stream
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* @azx_dev: HD-audio core stream to stop
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* Stop a stream DMA and disable stream interrupt
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void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
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trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
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snd_hdac_stream_clear(azx_dev);
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snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
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EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
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* snd_hdac_stream_reset - reset a stream
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* @azx_dev: HD-audio core stream to reset
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void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
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snd_hdac_stream_clear(azx_dev);
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snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
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val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
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val &= ~SD_CTL_STREAM_RESET;
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snd_hdac_stream_writeb(azx_dev, SD_CTL, val);
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/* waiting for hardware to report that the stream is out of reset */
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val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
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/* reset first position - may not be synced with hw at this time */
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*azx_dev->posbuf = 0;
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EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
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* snd_hdac_stream_setup - set up the SD for streaming
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* @azx_dev: HD-audio core stream to set up
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int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
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struct hdac_bus *bus = azx_dev->bus;
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struct snd_pcm_runtime *runtime;
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if (azx_dev->substream)
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runtime = azx_dev->substream->runtime;
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/* make sure the run bit is zero for SD */
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snd_hdac_stream_clear(azx_dev);
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/* program the stream_tag */
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val = snd_hdac_stream_readl(azx_dev, SD_CTL);
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val = (val & ~SD_CTL_STREAM_TAG_MASK) |
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(azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
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val |= SD_CTL_TRAFFIC_PRIO;
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snd_hdac_stream_writel(azx_dev, SD_CTL, val);
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/* program the length of samples in cyclic buffer */
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snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
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/* program the stream format */
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/* this value needs to be the same as the one programmed */
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snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
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/* program the stream LVI (last valid index) of the BDL */
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snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
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/* program the BDL address */
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/* lower BDL address */
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snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
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/* upper BDL address */
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snd_hdac_stream_writel(azx_dev, SD_BDLPU,
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upper_32_bits(azx_dev->bdl.addr));
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/* enable the position buffer */
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if (bus->use_posbuf && bus->posbuf.addr) {
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if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
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snd_hdac_chip_writel(bus, DPLBASE,
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(u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
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/* set the interrupt enable bits in the descriptor control register */
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snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
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azx_dev->fifo_size = snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
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/* when LPIB delay correction gives a small negative value,
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* we ignore it; currently set the threshold statically to
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if (runtime && runtime->period_size > 64)
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azx_dev->delay_negative_threshold =
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-frames_to_bytes(runtime, 64);
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azx_dev->delay_negative_threshold = 0;
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/* wallclk has 24Mhz clock source */
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azx_dev->period_wallclk = (((runtime->period_size * 24000) /
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runtime->rate) * 1000);
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EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
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* snd_hdac_stream_cleanup - cleanup a stream
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* @azx_dev: HD-audio core stream to clean up
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void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
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snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
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snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
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snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
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azx_dev->bufsize = 0;
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azx_dev->period_bytes = 0;
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azx_dev->format_val = 0;
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EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
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* snd_hdac_stream_assign - assign a stream for the PCM
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* @bus: HD-audio core bus
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* @substream: PCM substream to assign
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* Look for an unused stream for the given PCM substream, assign it
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* and return the stream object. If no stream is free, returns NULL.
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* The function tries to keep using the same stream object when it's used
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* beforehand. Also, when bus->reverse_assign flag is set, the last free
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* or matching entry is returned. This is needed for some strange codecs.
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struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
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struct snd_pcm_substream *substream)
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struct hdac_stream *azx_dev;
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struct hdac_stream *res = NULL;
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/* make a non-zero unique key for the substream */
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int key = (substream->pcm->device << 16) | (substream->number << 2) |
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(substream->stream + 1);
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list_for_each_entry(azx_dev, &bus->stream_list, list) {
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if (azx_dev->direction != substream->stream)
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if (azx_dev->assigned_key == key) {
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if (!res || bus->reverse_assign)
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spin_lock_irq(&bus->reg_lock);
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res->assigned_key = key;
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res->substream = substream;
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spin_unlock_irq(&bus->reg_lock);
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EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
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* snd_hdac_stream_release - release the assigned stream
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* @azx_dev: HD-audio core stream to release
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* Release the stream that has been assigned by snd_hdac_stream_assign().
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void snd_hdac_stream_release(struct hdac_stream *azx_dev)
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struct hdac_bus *bus = azx_dev->bus;
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spin_lock_irq(&bus->reg_lock);
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azx_dev->running = 0;
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azx_dev->substream = NULL;
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spin_unlock_irq(&bus->reg_lock);
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EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
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* snd_hdac_get_stream - return hdac_stream based on stream_tag and
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* @bus: HD-audio core bus
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* @dir: direction for the stream to be found
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* @stream_tag: stream tag for stream to be found
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struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
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int dir, int stream_tag)
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struct hdac_stream *s;
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list_for_each_entry(s, &bus->stream_list, list) {
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if (s->direction == dir && s->stream_tag == stream_tag)
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EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
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static int setup_bdle(struct hdac_bus *bus,
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struct snd_dma_buffer *dmab,
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struct hdac_stream *azx_dev, __le32 **bdlp,
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int ofs, int size, int with_ioc)
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if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
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addr = snd_sgbuf_get_addr(dmab, ofs);
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/* program the address field of the BDL entry */
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bdl[0] = cpu_to_le32((u32)addr);
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bdl[1] = cpu_to_le32(upper_32_bits(addr));
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/* program the size field of the BDL entry */
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chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
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/* one BDLE cannot cross 4K boundary on CTHDA chips */
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if (bus->align_bdle_4k) {
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u32 remain = 0x1000 - (ofs & 0xfff);
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bdl[2] = cpu_to_le32(chunk);
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/* program the IOC to enable interrupt
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* only when the whole fragment is processed
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bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
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* snd_hdac_stream_setup_periods - set up BDL entries
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* @azx_dev: HD-audio core stream to set up
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* Set up the buffer descriptor table of the given stream based on the
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* period and buffer sizes of the assigned PCM substream.
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int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
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struct hdac_bus *bus = azx_dev->bus;
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struct snd_pcm_substream *substream = azx_dev->substream;
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struct snd_pcm_runtime *runtime = substream->runtime;
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int i, ofs, periods, period_bytes;
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int pos_adj, pos_align;
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/* reset BDL address */
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snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
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snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
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period_bytes = azx_dev->period_bytes;
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periods = azx_dev->bufsize / period_bytes;
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/* program the initial BDL entries */
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bdl = (__le32 *)azx_dev->bdl.area;
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pos_adj = bus->bdl_pos_adj;
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if (!azx_dev->no_period_wakeup && pos_adj > 0) {
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pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
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pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
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pos_adj = frames_to_bytes(runtime, pos_adj);
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if (pos_adj >= period_bytes) {
436
dev_warn(bus->dev, "Too big adjustment %d\n",
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ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
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&bdl, ofs, pos_adj, true);
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for (i = 0; i < periods; i++) {
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if (i == periods - 1 && pos_adj)
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ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
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period_bytes - pos_adj, 0);
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ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
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!azx_dev->no_period_wakeup);
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dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
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azx_dev->bufsize, period_bytes);
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EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
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* snd_hdac_stream_set_params - set stream parameters
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* @azx_dev: HD-audio core stream for which parameters are to be set
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* @format_val: format value parameter
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* Setup the HD-audio core stream parameters from substream of the stream
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* and passed format value
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int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
480
unsigned int format_val)
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unsigned int bufsize, period_bytes;
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struct snd_pcm_substream *substream = azx_dev->substream;
485
struct snd_pcm_runtime *runtime;
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runtime = substream->runtime;
491
bufsize = snd_pcm_lib_buffer_bytes(substream);
492
period_bytes = snd_pcm_lib_period_bytes(substream);
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if (bufsize != azx_dev->bufsize ||
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period_bytes != azx_dev->period_bytes ||
496
format_val != azx_dev->format_val ||
497
runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
498
azx_dev->bufsize = bufsize;
499
azx_dev->period_bytes = period_bytes;
500
azx_dev->format_val = format_val;
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azx_dev->no_period_wakeup = runtime->no_period_wakeup;
502
err = snd_hdac_stream_setup_periods(azx_dev);
508
EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
510
static u64 azx_cc_read(const struct cyclecounter *cc)
512
struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
514
return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
517
static void azx_timecounter_init(struct hdac_stream *azx_dev,
518
bool force, u64 last)
520
struct timecounter *tc = &azx_dev->tc;
521
struct cyclecounter *cc = &azx_dev->cc;
524
cc->read = azx_cc_read;
525
cc->mask = CLOCKSOURCE_MASK(32);
528
* Converting from 24 MHz to ns means applying a 125/3 factor.
529
* To avoid any saturation issues in intermediate operations,
530
* the 125 factor is applied first. The division is applied
531
* last after reading the timecounter value.
532
* Applying the 1/3 factor as part of the multiplication
533
* requires at least 20 bits for a decent precision, however
534
* overflows occur after about 4 hours or less, not a option.
537
cc->mult = 125; /* saturation after 195 years */
540
nsec = 0; /* audio time is elapsed time since trigger */
541
timecounter_init(tc, cc, nsec);
544
* force timecounter to use predefined value,
545
* used for synchronized starts
547
tc->cycle_last = last;
552
* snd_hdac_stream_timecounter_init - initialize time counter
553
* @azx_dev: HD-audio core stream (master stream)
554
* @streams: bit flags of streams to set up
556
* Initializes the time counter of streams marked by the bit flags (each
557
* bit corresponds to the stream index).
558
* The trigger timestamp of PCM substream assigned to the given stream is
559
* updated accordingly, too.
561
void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
562
unsigned int streams)
564
struct hdac_bus *bus = azx_dev->bus;
565
struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
566
struct hdac_stream *s;
571
list_for_each_entry(s, &bus->stream_list, list) {
572
if (streams & (1 << i)) {
573
azx_timecounter_init(s, inited, cycle_last);
576
cycle_last = s->tc.cycle_last;
582
snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
583
runtime->trigger_tstamp_latched = true;
585
EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
588
* snd_hdac_stream_sync_trigger - turn on/off stream sync register
589
* @azx_dev: HD-audio core stream (master stream)
590
* @streams: bit flags of streams to sync
592
void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
593
unsigned int streams, unsigned int reg)
595
struct hdac_bus *bus = azx_dev->bus;
600
val = _snd_hdac_chip_readl(bus, reg);
605
_snd_hdac_chip_writel(bus, reg, val);
607
EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
610
* snd_hdac_stream_sync - sync with start/strop trigger operation
611
* @azx_dev: HD-audio core stream (master stream)
612
* @start: true = start, false = stop
613
* @streams: bit flags of streams to sync
615
* For @start = true, wait until all FIFOs get ready.
616
* For @start = false, wait until all RUN bits are cleared.
618
void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
619
unsigned int streams)
621
struct hdac_bus *bus = azx_dev->bus;
622
int i, nwait, timeout;
623
struct hdac_stream *s;
625
for (timeout = 5000; timeout; timeout--) {
628
list_for_each_entry(s, &bus->stream_list, list) {
629
if (streams & (1 << i)) {
631
/* check FIFO gets ready */
632
if (!(snd_hdac_stream_readb(s, SD_STS) &
636
/* check RUN bit is cleared */
637
if (snd_hdac_stream_readb(s, SD_CTL) &
649
EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
651
#ifdef CONFIG_SND_HDA_DSP_LOADER
653
* snd_hdac_dsp_prepare - prepare for DSP loading
654
* @azx_dev: HD-audio core stream used for DSP loading
655
* @format: HD-audio stream format
656
* @byte_size: data chunk byte size
657
* @bufp: allocated buffer
659
* Allocate the buffer for the given size and set up the given stream for
660
* DSP loading. Returns the stream tag (>= 0), or a negative error code.
662
int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
663
unsigned int byte_size, struct snd_dma_buffer *bufp)
665
struct hdac_bus *bus = azx_dev->bus;
669
snd_hdac_dsp_lock(azx_dev);
670
spin_lock_irq(&bus->reg_lock);
671
if (azx_dev->running || azx_dev->locked) {
672
spin_unlock_irq(&bus->reg_lock);
676
azx_dev->locked = true;
677
spin_unlock_irq(&bus->reg_lock);
679
err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev,
684
azx_dev->substream = NULL;
685
azx_dev->bufsize = byte_size;
686
azx_dev->period_bytes = byte_size;
687
azx_dev->format_val = format;
689
snd_hdac_stream_reset(azx_dev);
691
/* reset BDL address */
692
snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
693
snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
696
bdl = (__le32 *)azx_dev->bdl.area;
697
err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
701
snd_hdac_stream_setup(azx_dev);
702
snd_hdac_dsp_unlock(azx_dev);
703
return azx_dev->stream_tag;
706
snd_dma_free_pages(bufp);
708
spin_lock_irq(&bus->reg_lock);
709
azx_dev->locked = false;
710
spin_unlock_irq(&bus->reg_lock);
712
snd_hdac_dsp_unlock(azx_dev);
715
EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
718
* snd_hdac_dsp_trigger - start / stop DSP loading
719
* @azx_dev: HD-audio core stream used for DSP loading
720
* @start: trigger start or stop
722
void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
725
snd_hdac_stream_start(azx_dev, true);
727
snd_hdac_stream_stop(azx_dev);
729
EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
732
* snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
733
* @azx_dev: HD-audio core stream used for DSP loading
734
* @dmab: buffer used by DSP loading
736
void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
737
struct snd_dma_buffer *dmab)
739
struct hdac_bus *bus = azx_dev->bus;
741
if (!dmab->area || !azx_dev->locked)
744
snd_hdac_dsp_lock(azx_dev);
745
/* reset BDL address */
746
snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
747
snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
748
snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
749
azx_dev->bufsize = 0;
750
azx_dev->period_bytes = 0;
751
azx_dev->format_val = 0;
753
snd_dma_free_pages(dmab);
756
spin_lock_irq(&bus->reg_lock);
757
azx_dev->locked = false;
758
spin_unlock_irq(&bus->reg_lock);
759
snd_hdac_dsp_unlock(azx_dev);
761
EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
762
#endif /* CONFIG_SND_HDA_DSP_LOADER */