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// SPDX-License-Identifier: GPL-2.0-only
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* max98090.c -- MAX98090 ALSA SoC Audio driver
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* Copyright 2011-2012 Maxim Integrated Products
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/acpi.h>
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#include <linux/clk.h>
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#include <sound/jack.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/tlv.h>
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#include <sound/max98090.h>
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/* Allows for sparsely populated register maps */
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static const struct reg_default max98090_reg[] = {
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{ 0x00, 0x00 }, /* 00 Software Reset */
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{ 0x03, 0x04 }, /* 03 Interrupt Masks */
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{ 0x04, 0x00 }, /* 04 System Clock Quick */
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{ 0x05, 0x00 }, /* 05 Sample Rate Quick */
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{ 0x06, 0x00 }, /* 06 DAI Interface Quick */
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{ 0x07, 0x00 }, /* 07 DAC Path Quick */
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{ 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
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{ 0x09, 0x00 }, /* 09 Line to ADC Quick */
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{ 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
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{ 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
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{ 0x0C, 0x00 }, /* 0C Reserved */
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{ 0x0D, 0x00 }, /* 0D Input Config */
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{ 0x0E, 0x1B }, /* 0E Line Input Level */
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{ 0x0F, 0x00 }, /* 0F Line Config */
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{ 0x10, 0x14 }, /* 10 Mic1 Input Level */
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{ 0x11, 0x14 }, /* 11 Mic2 Input Level */
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{ 0x12, 0x00 }, /* 12 Mic Bias Voltage */
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{ 0x13, 0x00 }, /* 13 Digital Mic Config */
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{ 0x14, 0x00 }, /* 14 Digital Mic Mode */
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{ 0x15, 0x00 }, /* 15 Left ADC Mixer */
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{ 0x16, 0x00 }, /* 16 Right ADC Mixer */
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{ 0x17, 0x03 }, /* 17 Left ADC Level */
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{ 0x18, 0x03 }, /* 18 Right ADC Level */
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{ 0x19, 0x00 }, /* 19 ADC Biquad Level */
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{ 0x1A, 0x00 }, /* 1A ADC Sidetone */
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{ 0x1B, 0x00 }, /* 1B System Clock */
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{ 0x1C, 0x00 }, /* 1C Clock Mode */
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{ 0x1D, 0x00 }, /* 1D Any Clock 1 */
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{ 0x1E, 0x00 }, /* 1E Any Clock 2 */
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{ 0x1F, 0x00 }, /* 1F Any Clock 3 */
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{ 0x20, 0x00 }, /* 20 Any Clock 4 */
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{ 0x21, 0x00 }, /* 21 Master Mode */
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{ 0x22, 0x00 }, /* 22 Interface Format */
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{ 0x23, 0x00 }, /* 23 TDM Format 1*/
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{ 0x24, 0x00 }, /* 24 TDM Format 2*/
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{ 0x25, 0x00 }, /* 25 I/O Configuration */
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{ 0x26, 0x80 }, /* 26 Filter Config */
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{ 0x27, 0x00 }, /* 27 DAI Playback Level */
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{ 0x28, 0x00 }, /* 28 EQ Playback Level */
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{ 0x29, 0x00 }, /* 29 Left HP Mixer */
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{ 0x2A, 0x00 }, /* 2A Right HP Mixer */
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{ 0x2B, 0x00 }, /* 2B HP Control */
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{ 0x2C, 0x1A }, /* 2C Left HP Volume */
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{ 0x2D, 0x1A }, /* 2D Right HP Volume */
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{ 0x2E, 0x00 }, /* 2E Left Spk Mixer */
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{ 0x2F, 0x00 }, /* 2F Right Spk Mixer */
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{ 0x30, 0x00 }, /* 30 Spk Control */
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{ 0x31, 0x2C }, /* 31 Left Spk Volume */
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{ 0x32, 0x2C }, /* 32 Right Spk Volume */
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{ 0x33, 0x00 }, /* 33 ALC Timing */
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{ 0x34, 0x00 }, /* 34 ALC Compressor */
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{ 0x35, 0x00 }, /* 35 ALC Expander */
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{ 0x36, 0x00 }, /* 36 ALC Gain */
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{ 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
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{ 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
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{ 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
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{ 0x3A, 0x00 }, /* 3A Line OutR Mixer */
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{ 0x3B, 0x00 }, /* 3B Line OutR Control */
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{ 0x3C, 0x15 }, /* 3C Line OutR Volume */
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{ 0x3D, 0x00 }, /* 3D Jack Detect */
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{ 0x3E, 0x00 }, /* 3E Input Enable */
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{ 0x3F, 0x00 }, /* 3F Output Enable */
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{ 0x40, 0x00 }, /* 40 Level Control */
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{ 0x41, 0x00 }, /* 41 DSP Filter Enable */
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{ 0x42, 0x00 }, /* 42 Bias Control */
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{ 0x43, 0x00 }, /* 43 DAC Control */
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{ 0x44, 0x06 }, /* 44 ADC Control */
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{ 0x45, 0x00 }, /* 45 Device Shutdown */
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{ 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
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{ 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
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{ 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
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{ 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
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{ 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
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{ 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
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{ 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
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{ 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
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{ 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
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{ 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
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{ 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
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{ 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
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{ 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
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{ 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
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{ 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
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{ 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
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{ 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
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{ 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
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{ 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
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{ 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
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{ 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
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{ 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
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{ 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
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{ 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
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{ 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
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{ 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
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{ 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
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{ 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
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{ 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
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{ 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
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{ 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
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{ 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
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{ 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
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{ 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
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{ 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
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{ 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
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{ 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
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{ 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
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{ 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
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{ 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
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{ 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
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{ 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
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{ 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
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{ 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
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{ 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
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{ 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
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{ 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
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{ 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
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{ 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
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{ 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
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{ 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
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{ 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
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{ 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
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{ 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
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{ 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
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{ 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
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{ 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
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{ 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
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{ 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
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{ 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
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{ 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
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{ 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
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{ 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
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{ 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
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{ 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
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{ 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
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{ 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
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{ 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
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{ 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
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{ 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
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{ 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
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{ 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
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{ 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
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{ 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
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{ 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
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{ 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
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{ 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
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{ 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
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{ 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
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{ 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
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{ 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
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{ 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
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{ 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
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{ 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
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{ 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
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{ 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
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{ 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
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{ 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
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{ 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
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{ 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
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{ 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
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{ 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
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{ 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
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{ 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
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{ 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
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{ 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
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{ 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
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{ 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
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{ 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
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{ 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
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{ 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
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{ 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
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{ 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
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{ 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
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{ 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
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{ 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
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{ 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
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{ 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
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{ 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
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{ 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
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{ 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
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{ 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
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{ 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
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{ 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
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{ 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
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{ 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
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{ 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
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{ 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
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{ 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
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{ 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
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{ 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
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{ 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
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{ 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
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{ 0xC1, 0x00 }, /* C1 Record TDM Slot */
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{ 0xC2, 0x00 }, /* C2 Sample Rate */
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{ 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
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{ 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
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{ 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
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{ 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
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{ 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
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{ 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
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{ 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
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{ 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
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{ 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
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{ 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
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{ 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
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{ 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
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{ 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
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{ 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
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{ 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
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static bool max98090_volatile_register(struct device *dev, unsigned int reg)
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case M98090_REG_SOFTWARE_RESET:
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case M98090_REG_DEVICE_STATUS:
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case M98090_REG_JACK_STATUS:
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case M98090_REG_REVISION_ID:
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static bool max98090_readable_register(struct device *dev, unsigned int reg)
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case M98090_REG_DEVICE_STATUS ... M98090_REG_INTERRUPT_S:
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case M98090_REG_LINE_INPUT_CONFIG ... 0xD1:
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case M98090_REG_REVISION_ID:
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static int max98090_reset(struct max98090_priv *max98090)
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/* Reset the codec by writing to this write-only reset register */
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ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET,
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M98090_SWRESET_MASK);
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dev_err(max98090->component->dev,
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"Failed to reset codec: %d\n", ret);
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static const DECLARE_TLV_DB_RANGE(max98090_micboost_tlv,
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0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
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2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
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static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0);
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static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv,
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static const DECLARE_TLV_DB_RANGE(max98090_line_tlv,
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0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
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4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0)
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static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0);
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static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
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static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0);
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static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
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static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0);
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static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
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static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
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static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv, 50, 200, 0);
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static const DECLARE_TLV_DB_RANGE(max98090_mixout_tlv,
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0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
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2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0)
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static const DECLARE_TLV_DB_RANGE(max98090_hp_tlv,
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0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
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7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
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15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
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22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
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28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
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static const DECLARE_TLV_DB_RANGE(max98090_spk_tlv,
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0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
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5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
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11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
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15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
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30, 39, TLV_DB_SCALE_ITEM(950, 50, 0)
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static const DECLARE_TLV_DB_RANGE(max98090_rcv_lout_tlv,
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0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
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7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
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15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
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22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
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28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
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static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
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struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
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struct soc_mixer_control *mc =
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(struct soc_mixer_control *)kcontrol->private_value;
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unsigned int mask = (1 << fls(mc->max)) - 1;
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unsigned int val = snd_soc_component_read32(component, mc->reg);
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unsigned int *select;
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case M98090_REG_MIC1_INPUT_LEVEL:
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select = &(max98090->pa1en);
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case M98090_REG_MIC2_INPUT_LEVEL:
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select = &(max98090->pa2en);
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case M98090_REG_ADC_SIDETONE:
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select = &(max98090->sidetone);
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val = (val >> mc->shift) & mask;
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/* If on, return the volume */
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/* If off, return last stored value */
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ucontrol->value.integer.value[0] = val;
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static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
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struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
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struct soc_mixer_control *mc =
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(struct soc_mixer_control *)kcontrol->private_value;
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unsigned int mask = (1 << fls(mc->max)) - 1;
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unsigned int sel = ucontrol->value.integer.value[0];
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unsigned int val = snd_soc_component_read32(component, mc->reg);
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unsigned int *select;
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case M98090_REG_MIC1_INPUT_LEVEL:
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select = &(max98090->pa1en);
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case M98090_REG_MIC2_INPUT_LEVEL:
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select = &(max98090->pa2en);
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case M98090_REG_ADC_SIDETONE:
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select = &(max98090->sidetone);
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val = (val >> mc->shift) & mask;
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/* Setting a volume is only valid if it is already On */
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/* Write what was already there */
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snd_soc_component_update_bits(component, mc->reg,
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static const char *max98090_perf_pwr_text[] =
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{ "High Performance", "Low Power" };
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static const char *max98090_pwr_perf_text[] =
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{ "Low Power", "High Performance" };
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static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum,
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M98090_REG_BIAS_CONTROL,
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M98090_VCM_MODE_SHIFT,
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max98090_pwr_perf_text);
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static const char *max98090_osr128_text[] = { "64*fs", "128*fs" };
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static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum,
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M98090_REG_ADC_CONTROL,
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max98090_osr128_text);
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static const char *max98090_mode_text[] = { "Voice", "Music" };
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static SOC_ENUM_SINGLE_DECL(max98090_mode_enum,
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M98090_REG_FILTER_CONFIG,
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static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum,
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M98090_REG_FILTER_CONFIG,
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M98090_FLT_DMIC34MODE_SHIFT,
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static const char *max98090_drcatk_text[] =
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{ "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
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static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum,
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M98090_REG_DRC_TIMING,
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max98090_drcatk_text);
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static const char *max98090_drcrls_text[] =
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{ "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
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static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum,
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M98090_REG_DRC_TIMING,
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max98090_drcrls_text);
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static const char *max98090_alccmp_text[] =
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{ "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
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static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum,
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M98090_REG_DRC_COMPRESSOR,
484
max98090_alccmp_text);
486
static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" };
488
static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum,
489
M98090_REG_DRC_EXPANDER,
491
max98090_drcexp_text);
493
static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum,
494
M98090_REG_DAC_CONTROL,
495
M98090_PERFMODE_SHIFT,
496
max98090_perf_pwr_text);
498
static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum,
499
M98090_REG_DAC_CONTROL,
501
max98090_pwr_perf_text);
503
static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum,
504
M98090_REG_ADC_CONTROL,
506
max98090_pwr_perf_text);
508
static const struct snd_kcontrol_new max98090_snd_controls[] = {
509
SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum),
511
SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG,
512
M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
514
SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
515
M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
516
M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
517
max98090_put_enab_tlv, max98090_micboost_tlv),
519
SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
520
M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
521
M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
522
max98090_put_enab_tlv, max98090_micboost_tlv),
524
SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL,
525
M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
528
SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL,
529
M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
532
SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
533
M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0,
534
M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
536
SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
537
M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0,
538
M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
540
SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL,
541
M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
544
SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL,
545
M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
548
SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
549
M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
550
SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
551
M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
553
SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL,
554
M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
556
SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL,
557
M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
560
SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
561
M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
563
SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
564
M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
567
SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum),
568
SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
569
M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
570
SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum),
572
SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
573
M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
574
SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION,
575
M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
576
SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
577
M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
578
SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
579
M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
580
SOC_ENUM("Filter Mode", max98090_mode_enum),
581
SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
582
M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
583
SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
584
M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
585
SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
586
M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
587
SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
588
M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
589
M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
590
max98090_put_enab_tlv, max98090_sdg_tlv),
591
SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
592
M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
594
SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
595
M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
597
SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105),
598
SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
599
M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
600
SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
601
M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
602
SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
603
M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
604
SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
605
M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
607
SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
608
M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
611
SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING,
612
M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
613
SOC_ENUM("ALC Attack Time", max98090_drcatk_enum),
614
SOC_ENUM("ALC Release Time", max98090_drcrls_enum),
615
SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
616
M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
617
max98090_alcmakeup_tlv),
618
SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum),
619
SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum),
620
SOC_SINGLE_TLV("ALC Compression Threshold Volume",
621
M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
622
M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
623
SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
624
M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
625
M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
627
SOC_ENUM("DAC HP Playback Performance Mode",
628
max98090_dac_perfmode_enum),
629
SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum),
631
SOC_SINGLE_TLV("Headphone Left Mixer Volume",
632
M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
633
M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
634
SOC_SINGLE_TLV("Headphone Right Mixer Volume",
635
M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
636
M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
638
SOC_SINGLE_TLV("Speaker Left Mixer Volume",
639
M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT,
640
M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
641
SOC_SINGLE_TLV("Speaker Right Mixer Volume",
642
M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT,
643
M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
645
SOC_SINGLE_TLV("Receiver Left Mixer Volume",
646
M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT,
647
M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
648
SOC_SINGLE_TLV("Receiver Right Mixer Volume",
649
M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT,
650
M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
652
SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME,
653
M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT,
654
M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
656
SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
657
M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME,
658
M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
659
0, max98090_spk_tlv),
661
SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME,
662
M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT,
663
M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
665
SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
666
M98090_HPLM_SHIFT, 1, 1),
667
SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
668
M98090_HPRM_SHIFT, 1, 1),
670
SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
671
M98090_SPLM_SHIFT, 1, 1),
672
SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
673
M98090_SPRM_SHIFT, 1, 1),
675
SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
676
M98090_RCVLM_SHIFT, 1, 1),
677
SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
678
M98090_RCVRM_SHIFT, 1, 1),
680
SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
681
M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
682
SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
683
M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
684
SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
685
M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
687
SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15),
688
SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
689
M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
692
static const struct snd_kcontrol_new max98091_snd_controls[] = {
694
SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
695
M98090_DMIC34_ZEROPAD_SHIFT,
696
M98090_DMIC34_ZEROPAD_NUM - 1, 0),
698
SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum),
699
SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
700
M98090_FLT_DMIC34HPF_SHIFT,
701
M98090_FLT_DMIC34HPF_NUM - 1, 0),
703
SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
704
M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
706
SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
707
M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
710
SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
711
M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
713
SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
714
M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
717
SND_SOC_BYTES("DMIC34 Biquad Coefficients",
718
M98090_REG_DMIC34_BIQUAD_BASE, 15),
719
SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
720
M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
722
SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
723
M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
724
M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
727
static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
728
struct snd_kcontrol *kcontrol, int event)
730
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
731
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
733
unsigned int val = snd_soc_component_read32(component, w->reg);
735
if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
736
val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT;
738
val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT;
741
if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) {
742
max98090->pa1en = val - 1; /* Update for volatile */
744
max98090->pa2en = val - 1; /* Update for volatile */
749
case SND_SOC_DAPM_POST_PMU:
750
/* If turning on, set to most recently selected volume */
751
if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
752
val = max98090->pa1en + 1;
754
val = max98090->pa2en + 1;
756
case SND_SOC_DAPM_POST_PMD:
757
/* If turning off, turn off */
764
if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
765
snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA1EN_MASK,
766
val << M98090_MIC_PA1EN_SHIFT);
768
snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK,
769
val << M98090_MIC_PA2EN_SHIFT);
774
static int max98090_shdn_event(struct snd_soc_dapm_widget *w,
775
struct snd_kcontrol *kcontrol, int event)
777
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
778
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
780
if (event & SND_SOC_DAPM_POST_PMU)
781
max98090->shdn_pending = true;
787
static const char *mic1_mux_text[] = { "IN12", "IN56" };
789
static SOC_ENUM_SINGLE_DECL(mic1_mux_enum,
790
M98090_REG_INPUT_MODE,
791
M98090_EXTMIC1_SHIFT,
794
static const struct snd_kcontrol_new max98090_mic1_mux =
795
SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum);
797
static const char *mic2_mux_text[] = { "IN34", "IN56" };
799
static SOC_ENUM_SINGLE_DECL(mic2_mux_enum,
800
M98090_REG_INPUT_MODE,
801
M98090_EXTMIC2_SHIFT,
804
static const struct snd_kcontrol_new max98090_mic2_mux =
805
SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum);
807
static const char *dmic_mux_text[] = { "ADC", "DMIC" };
809
static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text);
811
static const struct snd_kcontrol_new max98090_dmic_mux =
812
SOC_DAPM_ENUM("DMIC Mux", dmic_mux_enum);
814
/* LINEA mixer switch */
815
static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = {
816
SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
817
M98090_IN1SEEN_SHIFT, 1, 0),
818
SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
819
M98090_IN3SEEN_SHIFT, 1, 0),
820
SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
821
M98090_IN5SEEN_SHIFT, 1, 0),
822
SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
823
M98090_IN34DIFF_SHIFT, 1, 0),
826
/* LINEB mixer switch */
827
static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = {
828
SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
829
M98090_IN2SEEN_SHIFT, 1, 0),
830
SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
831
M98090_IN4SEEN_SHIFT, 1, 0),
832
SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
833
M98090_IN6SEEN_SHIFT, 1, 0),
834
SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
835
M98090_IN56DIFF_SHIFT, 1, 0),
838
/* Left ADC mixer switch */
839
static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = {
840
SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
841
M98090_MIXADL_IN12DIFF_SHIFT, 1, 0),
842
SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
843
M98090_MIXADL_IN34DIFF_SHIFT, 1, 0),
844
SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
845
M98090_MIXADL_IN65DIFF_SHIFT, 1, 0),
846
SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
847
M98090_MIXADL_LINEA_SHIFT, 1, 0),
848
SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
849
M98090_MIXADL_LINEB_SHIFT, 1, 0),
850
SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
851
M98090_MIXADL_MIC1_SHIFT, 1, 0),
852
SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
853
M98090_MIXADL_MIC2_SHIFT, 1, 0),
856
/* Right ADC mixer switch */
857
static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = {
858
SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
859
M98090_MIXADR_IN12DIFF_SHIFT, 1, 0),
860
SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
861
M98090_MIXADR_IN34DIFF_SHIFT, 1, 0),
862
SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
863
M98090_MIXADR_IN65DIFF_SHIFT, 1, 0),
864
SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
865
M98090_MIXADR_LINEA_SHIFT, 1, 0),
866
SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
867
M98090_MIXADR_LINEB_SHIFT, 1, 0),
868
SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
869
M98090_MIXADR_MIC1_SHIFT, 1, 0),
870
SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
871
M98090_MIXADR_MIC2_SHIFT, 1, 0),
874
static const char *lten_mux_text[] = { "Normal", "Loopthrough" };
876
static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum,
877
M98090_REG_IO_CONFIGURATION,
881
static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum,
882
M98090_REG_IO_CONFIGURATION,
886
static const struct snd_kcontrol_new max98090_ltenl_mux =
887
SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum);
889
static const struct snd_kcontrol_new max98090_ltenr_mux =
890
SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum);
892
static const char *lben_mux_text[] = { "Normal", "Loopback" };
894
static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum,
895
M98090_REG_IO_CONFIGURATION,
899
static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum,
900
M98090_REG_IO_CONFIGURATION,
904
static const struct snd_kcontrol_new max98090_lbenl_mux =
905
SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum);
907
static const struct snd_kcontrol_new max98090_lbenr_mux =
908
SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum);
910
static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
912
static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
914
static SOC_ENUM_SINGLE_DECL(stenl_mux_enum,
915
M98090_REG_ADC_SIDETONE,
919
static SOC_ENUM_SINGLE_DECL(stenr_mux_enum,
920
M98090_REG_ADC_SIDETONE,
924
static const struct snd_kcontrol_new max98090_stenl_mux =
925
SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum);
927
static const struct snd_kcontrol_new max98090_stenr_mux =
928
SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum);
930
/* Left speaker mixer switch */
932
snd_kcontrol_new max98090_left_speaker_mixer_controls[] = {
933
SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
934
M98090_MIXSPL_DACL_SHIFT, 1, 0),
935
SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
936
M98090_MIXSPL_DACR_SHIFT, 1, 0),
937
SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
938
M98090_MIXSPL_LINEA_SHIFT, 1, 0),
939
SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
940
M98090_MIXSPL_LINEB_SHIFT, 1, 0),
941
SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
942
M98090_MIXSPL_MIC1_SHIFT, 1, 0),
943
SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
944
M98090_MIXSPL_MIC2_SHIFT, 1, 0),
947
/* Right speaker mixer switch */
949
snd_kcontrol_new max98090_right_speaker_mixer_controls[] = {
950
SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
951
M98090_MIXSPR_DACL_SHIFT, 1, 0),
952
SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
953
M98090_MIXSPR_DACR_SHIFT, 1, 0),
954
SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
955
M98090_MIXSPR_LINEA_SHIFT, 1, 0),
956
SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
957
M98090_MIXSPR_LINEB_SHIFT, 1, 0),
958
SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
959
M98090_MIXSPR_MIC1_SHIFT, 1, 0),
960
SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
961
M98090_MIXSPR_MIC2_SHIFT, 1, 0),
964
/* Left headphone mixer switch */
965
static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = {
966
SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
967
M98090_MIXHPL_DACL_SHIFT, 1, 0),
968
SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
969
M98090_MIXHPL_DACR_SHIFT, 1, 0),
970
SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
971
M98090_MIXHPL_LINEA_SHIFT, 1, 0),
972
SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
973
M98090_MIXHPL_LINEB_SHIFT, 1, 0),
974
SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
975
M98090_MIXHPL_MIC1_SHIFT, 1, 0),
976
SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
977
M98090_MIXHPL_MIC2_SHIFT, 1, 0),
980
/* Right headphone mixer switch */
981
static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = {
982
SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
983
M98090_MIXHPR_DACL_SHIFT, 1, 0),
984
SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
985
M98090_MIXHPR_DACR_SHIFT, 1, 0),
986
SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
987
M98090_MIXHPR_LINEA_SHIFT, 1, 0),
988
SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
989
M98090_MIXHPR_LINEB_SHIFT, 1, 0),
990
SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
991
M98090_MIXHPR_MIC1_SHIFT, 1, 0),
992
SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
993
M98090_MIXHPR_MIC2_SHIFT, 1, 0),
996
/* Left receiver mixer switch */
997
static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = {
998
SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
999
M98090_MIXRCVL_DACL_SHIFT, 1, 0),
1000
SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1001
M98090_MIXRCVL_DACR_SHIFT, 1, 0),
1002
SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
1003
M98090_MIXRCVL_LINEA_SHIFT, 1, 0),
1004
SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
1005
M98090_MIXRCVL_LINEB_SHIFT, 1, 0),
1006
SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
1007
M98090_MIXRCVL_MIC1_SHIFT, 1, 0),
1008
SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
1009
M98090_MIXRCVL_MIC2_SHIFT, 1, 0),
1012
/* Right receiver mixer switch */
1013
static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = {
1014
SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
1015
M98090_MIXRCVR_DACL_SHIFT, 1, 0),
1016
SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
1017
M98090_MIXRCVR_DACR_SHIFT, 1, 0),
1018
SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
1019
M98090_MIXRCVR_LINEA_SHIFT, 1, 0),
1020
SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
1021
M98090_MIXRCVR_LINEB_SHIFT, 1, 0),
1022
SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
1023
M98090_MIXRCVR_MIC1_SHIFT, 1, 0),
1024
SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
1025
M98090_MIXRCVR_MIC2_SHIFT, 1, 0),
1028
static const char *linmod_mux_text[] = { "Left Only", "Left and Right" };
1030
static SOC_ENUM_SINGLE_DECL(linmod_mux_enum,
1031
M98090_REG_LOUTR_MIXER,
1032
M98090_LINMOD_SHIFT,
1035
static const struct snd_kcontrol_new max98090_linmod_mux =
1036
SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum);
1038
static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" };
1041
* This is a mux as it selects the HP output, but to DAPM it is a Mixer enable
1043
static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum,
1044
M98090_REG_HP_CONTROL,
1045
M98090_MIXHPLSEL_SHIFT,
1048
static const struct snd_kcontrol_new max98090_mixhplsel_mux =
1049
SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum);
1051
static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum,
1052
M98090_REG_HP_CONTROL,
1053
M98090_MIXHPRSEL_SHIFT,
1056
static const struct snd_kcontrol_new max98090_mixhprsel_mux =
1057
SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum);
1059
static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = {
1060
SND_SOC_DAPM_INPUT("MIC1"),
1061
SND_SOC_DAPM_INPUT("MIC2"),
1062
SND_SOC_DAPM_INPUT("DMICL"),
1063
SND_SOC_DAPM_INPUT("DMICR"),
1064
SND_SOC_DAPM_INPUT("IN1"),
1065
SND_SOC_DAPM_INPUT("IN2"),
1066
SND_SOC_DAPM_INPUT("IN3"),
1067
SND_SOC_DAPM_INPUT("IN4"),
1068
SND_SOC_DAPM_INPUT("IN5"),
1069
SND_SOC_DAPM_INPUT("IN6"),
1070
SND_SOC_DAPM_INPUT("IN12"),
1071
SND_SOC_DAPM_INPUT("IN34"),
1072
SND_SOC_DAPM_INPUT("IN56"),
1074
SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE,
1075
M98090_MBEN_SHIFT, 0, NULL, 0),
1076
SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN,
1077
M98090_SHDNN_SHIFT, 0, NULL, 0),
1078
SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION,
1079
M98090_SDIEN_SHIFT, 0, NULL, 0),
1080
SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION,
1081
M98090_SDOEN_SHIFT, 0, NULL, 0),
1082
SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1083
M98090_DIGMICL_SHIFT, 0, max98090_shdn_event,
1084
SND_SOC_DAPM_POST_PMU),
1085
SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1086
M98090_DIGMICR_SHIFT, 0, max98090_shdn_event,
1087
SND_SOC_DAPM_POST_PMU),
1088
SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG,
1089
M98090_AHPF_SHIFT, 0, NULL, 0),
1092
* Note: Sysclk and misc power supplies are taken care of by SHDN
1095
SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM,
1096
0, 0, &max98090_mic1_mux),
1098
SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM,
1099
0, 0, &max98090_mic2_mux),
1101
SND_SOC_DAPM_MUX("DMIC Mux", SND_SOC_NOPM, 0, 0, &max98090_dmic_mux),
1103
SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL,
1104
M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1105
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1107
SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL,
1108
M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1109
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1111
SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0,
1112
&max98090_linea_mixer_controls[0],
1113
ARRAY_SIZE(max98090_linea_mixer_controls)),
1115
SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0,
1116
&max98090_lineb_mixer_controls[0],
1117
ARRAY_SIZE(max98090_lineb_mixer_controls)),
1119
SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE,
1120
M98090_LINEAEN_SHIFT, 0, NULL, 0),
1121
SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE,
1122
M98090_LINEBEN_SHIFT, 0, NULL, 0),
1124
SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1125
&max98090_left_adc_mixer_controls[0],
1126
ARRAY_SIZE(max98090_left_adc_mixer_controls)),
1128
SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1129
&max98090_right_adc_mixer_controls[0],
1130
ARRAY_SIZE(max98090_right_adc_mixer_controls)),
1132
SND_SOC_DAPM_ADC_E("ADCL", NULL, M98090_REG_INPUT_ENABLE,
1133
M98090_ADLEN_SHIFT, 0, max98090_shdn_event,
1134
SND_SOC_DAPM_POST_PMU),
1135
SND_SOC_DAPM_ADC_E("ADCR", NULL, M98090_REG_INPUT_ENABLE,
1136
M98090_ADREN_SHIFT, 0, max98090_shdn_event,
1137
SND_SOC_DAPM_POST_PMU),
1139
SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
1140
SND_SOC_NOPM, 0, 0),
1141
SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
1142
SND_SOC_NOPM, 0, 0),
1144
SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM,
1145
0, 0, &max98090_lbenl_mux),
1147
SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM,
1148
0, 0, &max98090_lbenr_mux),
1150
SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM,
1151
0, 0, &max98090_ltenl_mux),
1153
SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM,
1154
0, 0, &max98090_ltenr_mux),
1156
SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM,
1157
0, 0, &max98090_stenl_mux),
1159
SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM,
1160
0, 0, &max98090_stenr_mux),
1162
SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
1163
SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
1165
SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE,
1166
M98090_DALEN_SHIFT, 0),
1167
SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE,
1168
M98090_DAREN_SHIFT, 0),
1170
SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1171
&max98090_left_hp_mixer_controls[0],
1172
ARRAY_SIZE(max98090_left_hp_mixer_controls)),
1174
SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1175
&max98090_right_hp_mixer_controls[0],
1176
ARRAY_SIZE(max98090_right_hp_mixer_controls)),
1178
SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1179
&max98090_left_speaker_mixer_controls[0],
1180
ARRAY_SIZE(max98090_left_speaker_mixer_controls)),
1182
SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1183
&max98090_right_speaker_mixer_controls[0],
1184
ARRAY_SIZE(max98090_right_speaker_mixer_controls)),
1186
SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0,
1187
&max98090_left_rcv_mixer_controls[0],
1188
ARRAY_SIZE(max98090_left_rcv_mixer_controls)),
1190
SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0,
1191
&max98090_right_rcv_mixer_controls[0],
1192
ARRAY_SIZE(max98090_right_rcv_mixer_controls)),
1194
SND_SOC_DAPM_MUX("LINMOD Mux", SND_SOC_NOPM, 0, 0,
1195
&max98090_linmod_mux),
1197
SND_SOC_DAPM_MUX("MIXHPLSEL Mux", SND_SOC_NOPM, 0, 0,
1198
&max98090_mixhplsel_mux),
1200
SND_SOC_DAPM_MUX("MIXHPRSEL Mux", SND_SOC_NOPM, 0, 0,
1201
&max98090_mixhprsel_mux),
1203
SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE,
1204
M98090_HPLEN_SHIFT, 0, NULL, 0),
1205
SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE,
1206
M98090_HPREN_SHIFT, 0, NULL, 0),
1208
SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
1209
M98090_SPLEN_SHIFT, 0, NULL, 0),
1210
SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
1211
M98090_SPREN_SHIFT, 0, NULL, 0),
1213
SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
1214
M98090_RCVLEN_SHIFT, 0, NULL, 0),
1215
SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
1216
M98090_RCVREN_SHIFT, 0, NULL, 0),
1218
SND_SOC_DAPM_OUTPUT("HPL"),
1219
SND_SOC_DAPM_OUTPUT("HPR"),
1220
SND_SOC_DAPM_OUTPUT("SPKL"),
1221
SND_SOC_DAPM_OUTPUT("SPKR"),
1222
SND_SOC_DAPM_OUTPUT("RCVL"),
1223
SND_SOC_DAPM_OUTPUT("RCVR"),
1226
static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = {
1227
SND_SOC_DAPM_INPUT("DMIC3"),
1228
SND_SOC_DAPM_INPUT("DMIC4"),
1230
SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1231
M98090_DIGMIC3_SHIFT, 0, NULL, 0),
1232
SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1233
M98090_DIGMIC4_SHIFT, 0, NULL, 0),
1236
static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
1237
{"MIC1 Input", NULL, "MIC1"},
1238
{"MIC2 Input", NULL, "MIC2"},
1240
{"DMICL", NULL, "DMICL_ENA"},
1241
{"DMICL", NULL, "DMICR_ENA"},
1242
{"DMICR", NULL, "DMICL_ENA"},
1243
{"DMICR", NULL, "DMICR_ENA"},
1244
{"DMICL", NULL, "AHPF"},
1245
{"DMICR", NULL, "AHPF"},
1247
/* MIC1 input mux */
1248
{"MIC1 Mux", "IN12", "IN12"},
1249
{"MIC1 Mux", "IN56", "IN56"},
1251
/* MIC2 input mux */
1252
{"MIC2 Mux", "IN34", "IN34"},
1253
{"MIC2 Mux", "IN56", "IN56"},
1255
{"MIC1 Input", NULL, "MIC1 Mux"},
1256
{"MIC2 Input", NULL, "MIC2 Mux"},
1258
/* Left ADC input mixer */
1259
{"Left ADC Mixer", "IN12 Switch", "IN12"},
1260
{"Left ADC Mixer", "IN34 Switch", "IN34"},
1261
{"Left ADC Mixer", "IN56 Switch", "IN56"},
1262
{"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1263
{"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1264
{"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1265
{"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1267
/* Right ADC input mixer */
1268
{"Right ADC Mixer", "IN12 Switch", "IN12"},
1269
{"Right ADC Mixer", "IN34 Switch", "IN34"},
1270
{"Right ADC Mixer", "IN56 Switch", "IN56"},
1271
{"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1272
{"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1273
{"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1274
{"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1276
/* Line A input mixer */
1277
{"LINEA Mixer", "IN1 Switch", "IN1"},
1278
{"LINEA Mixer", "IN3 Switch", "IN3"},
1279
{"LINEA Mixer", "IN5 Switch", "IN5"},
1280
{"LINEA Mixer", "IN34 Switch", "IN34"},
1282
/* Line B input mixer */
1283
{"LINEB Mixer", "IN2 Switch", "IN2"},
1284
{"LINEB Mixer", "IN4 Switch", "IN4"},
1285
{"LINEB Mixer", "IN6 Switch", "IN6"},
1286
{"LINEB Mixer", "IN56 Switch", "IN56"},
1288
{"LINEA Input", NULL, "LINEA Mixer"},
1289
{"LINEB Input", NULL, "LINEB Mixer"},
1292
{"ADCL", NULL, "Left ADC Mixer"},
1293
{"ADCR", NULL, "Right ADC Mixer"},
1294
{"ADCL", NULL, "SHDN"},
1295
{"ADCR", NULL, "SHDN"},
1297
{"DMIC Mux", "ADC", "ADCL"},
1298
{"DMIC Mux", "ADC", "ADCR"},
1299
{"DMIC Mux", "DMIC", "DMICL"},
1300
{"DMIC Mux", "DMIC", "DMICR"},
1302
{"LBENL Mux", "Normal", "DMIC Mux"},
1303
{"LBENL Mux", "Loopback", "LTENL Mux"},
1304
{"LBENR Mux", "Normal", "DMIC Mux"},
1305
{"LBENR Mux", "Loopback", "LTENR Mux"},
1307
{"AIFOUTL", NULL, "LBENL Mux"},
1308
{"AIFOUTR", NULL, "LBENR Mux"},
1309
{"AIFOUTL", NULL, "SHDN"},
1310
{"AIFOUTR", NULL, "SHDN"},
1311
{"AIFOUTL", NULL, "SDOEN"},
1312
{"AIFOUTR", NULL, "SDOEN"},
1314
{"LTENL Mux", "Normal", "AIFINL"},
1315
{"LTENL Mux", "Loopthrough", "LBENL Mux"},
1316
{"LTENR Mux", "Normal", "AIFINR"},
1317
{"LTENR Mux", "Loopthrough", "LBENR Mux"},
1319
{"DACL", NULL, "LTENL Mux"},
1320
{"DACR", NULL, "LTENR Mux"},
1322
{"STENL Mux", "Sidetone Left", "ADCL"},
1323
{"STENL Mux", "Sidetone Left", "DMICL"},
1324
{"STENR Mux", "Sidetone Right", "ADCR"},
1325
{"STENR Mux", "Sidetone Right", "DMICR"},
1326
{"DACL", NULL, "STENL Mux"},
1327
{"DACR", NULL, "STENR Mux"},
1329
{"AIFINL", NULL, "SHDN"},
1330
{"AIFINR", NULL, "SHDN"},
1331
{"AIFINL", NULL, "SDIEN"},
1332
{"AIFINR", NULL, "SDIEN"},
1333
{"DACL", NULL, "SHDN"},
1334
{"DACR", NULL, "SHDN"},
1336
/* Left headphone output mixer */
1337
{"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1338
{"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1339
{"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1340
{"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1341
{"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1342
{"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1344
/* Right headphone output mixer */
1345
{"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1346
{"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1347
{"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1348
{"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1349
{"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1350
{"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1352
/* Left speaker output mixer */
1353
{"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1354
{"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1355
{"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1356
{"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1357
{"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1358
{"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1360
/* Right speaker output mixer */
1361
{"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1362
{"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1363
{"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1364
{"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1365
{"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1366
{"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1368
/* Left Receiver output mixer */
1369
{"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1370
{"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1371
{"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1372
{"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1373
{"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1374
{"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1376
/* Right Receiver output mixer */
1377
{"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1378
{"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1379
{"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1380
{"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1381
{"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1382
{"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1384
{"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"},
1387
* Disable this for lowest power if bypassing
1388
* the DAC with an analog signal
1390
{"HP Left Out", NULL, "DACL"},
1391
{"HP Left Out", NULL, "MIXHPLSEL Mux"},
1393
{"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"},
1396
* Disable this for lowest power if bypassing
1397
* the DAC with an analog signal
1399
{"HP Right Out", NULL, "DACR"},
1400
{"HP Right Out", NULL, "MIXHPRSEL Mux"},
1402
{"SPK Left Out", NULL, "Left Speaker Mixer"},
1403
{"SPK Right Out", NULL, "Right Speaker Mixer"},
1404
{"RCV Left Out", NULL, "Left Receiver Mixer"},
1406
{"LINMOD Mux", "Left and Right", "Right Receiver Mixer"},
1407
{"LINMOD Mux", "Left Only", "Left Receiver Mixer"},
1408
{"RCV Right Out", NULL, "LINMOD Mux"},
1410
{"HPL", NULL, "HP Left Out"},
1411
{"HPR", NULL, "HP Right Out"},
1412
{"SPKL", NULL, "SPK Left Out"},
1413
{"SPKR", NULL, "SPK Right Out"},
1414
{"RCVL", NULL, "RCV Left Out"},
1415
{"RCVR", NULL, "RCV Right Out"},
1418
static const struct snd_soc_dapm_route max98091_dapm_routes[] = {
1420
{"DMIC3", NULL, "DMIC3_ENA"},
1421
{"DMIC4", NULL, "DMIC4_ENA"},
1422
{"DMIC3", NULL, "AHPF"},
1423
{"DMIC4", NULL, "AHPF"},
1426
static int max98090_add_widgets(struct snd_soc_component *component)
1428
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1429
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1431
snd_soc_add_component_controls(component, max98090_snd_controls,
1432
ARRAY_SIZE(max98090_snd_controls));
1434
if (max98090->devtype == MAX98091) {
1435
snd_soc_add_component_controls(component, max98091_snd_controls,
1436
ARRAY_SIZE(max98091_snd_controls));
1439
snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets,
1440
ARRAY_SIZE(max98090_dapm_widgets));
1442
snd_soc_dapm_add_routes(dapm, max98090_dapm_routes,
1443
ARRAY_SIZE(max98090_dapm_routes));
1445
if (max98090->devtype == MAX98091) {
1446
snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets,
1447
ARRAY_SIZE(max98091_dapm_widgets));
1449
snd_soc_dapm_add_routes(dapm, max98091_dapm_routes,
1450
ARRAY_SIZE(max98091_dapm_routes));
1456
static const int pclk_rates[] = {
1457
12000000, 12000000, 13000000, 13000000,
1458
16000000, 16000000, 19200000, 19200000
1461
static const int lrclk_rates[] = {
1462
8000, 16000, 8000, 16000,
1463
8000, 16000, 8000, 16000
1466
static const int user_pclk_rates[] = {
1467
13000000, 13000000, 19200000, 19200000,
1470
static const int user_lrclk_rates[] = {
1471
44100, 48000, 44100, 48000,
1474
static const unsigned long long ni_value[] = {
1478
static const unsigned long long mi_value[] = {
1479
8125, 1625, 1500, 25
1482
static void max98090_configure_bclk(struct snd_soc_component *component)
1484
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1485
unsigned long long ni;
1488
if (!max98090->sysclk) {
1489
dev_err(component->dev, "No SYSCLK configured\n");
1493
if (!max98090->bclk || !max98090->lrclk) {
1494
dev_err(component->dev, "No audio clocks configured\n");
1498
/* Skip configuration when operating as slave */
1499
if (!(snd_soc_component_read32(component, M98090_REG_MASTER_MODE) &
1504
/* Check for supported PCLK to LRCLK ratios */
1505
for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) {
1506
if ((pclk_rates[i] == max98090->sysclk) &&
1507
(lrclk_rates[i] == max98090->lrclk)) {
1508
dev_dbg(component->dev,
1509
"Found supported PCLK to LRCLK rates 0x%x\n",
1512
snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1514
(i + 0x8) << M98090_FREQ_SHIFT);
1515
snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1516
M98090_USE_M1_MASK, 0);
1521
/* Check for user calculated MI and NI ratios */
1522
for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) {
1523
if ((user_pclk_rates[i] == max98090->sysclk) &&
1524
(user_lrclk_rates[i] == max98090->lrclk)) {
1525
dev_dbg(component->dev,
1526
"Found user supported PCLK to LRCLK rates\n");
1527
dev_dbg(component->dev, "i %d ni %lld mi %lld\n",
1528
i, ni_value[i], mi_value[i]);
1530
snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1531
M98090_FREQ_MASK, 0);
1532
snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1534
1 << M98090_USE_M1_SHIFT);
1536
snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB,
1537
(ni_value[i] >> 8) & 0x7F);
1538
snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB,
1539
ni_value[i] & 0xFF);
1540
snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_MSB,
1541
(mi_value[i] >> 8) & 0x7F);
1542
snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_LSB,
1543
mi_value[i] & 0xFF);
1550
* Calculate based on MI = 65536 (not as good as either method above)
1552
snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1553
M98090_FREQ_MASK, 0);
1554
snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1555
M98090_USE_M1_MASK, 0);
1558
* Configure NI when operating as master
1559
* Note: There is a small, but significant audio quality improvement
1560
* by calculating ni and mi.
1562
ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL)
1563
* (unsigned long long int)max98090->lrclk;
1564
do_div(ni, (unsigned long long int)max98090->sysclk);
1565
dev_info(component->dev, "No better method found\n");
1566
dev_info(component->dev, "Calculating ni %lld with mi 65536\n", ni);
1567
snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB,
1569
snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF);
1572
static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai,
1575
struct snd_soc_component *component = codec_dai->component;
1576
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1577
struct max98090_cdata *cdata;
1580
max98090->dai_fmt = fmt;
1581
cdata = &max98090->dai[0];
1583
if (fmt != cdata->fmt) {
1587
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1588
case SND_SOC_DAIFMT_CBS_CFS:
1589
/* Set to slave mode PLL - MAS mode off */
1590
snd_soc_component_write(component,
1591
M98090_REG_CLOCK_RATIO_NI_MSB, 0x00);
1592
snd_soc_component_write(component,
1593
M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
1594
snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1595
M98090_USE_M1_MASK, 0);
1596
max98090->master = false;
1598
case SND_SOC_DAIFMT_CBM_CFM:
1599
/* Set to master mode */
1600
if (max98090->tdm_slots == 4) {
1602
regval |= M98090_MAS_MASK |
1604
} else if (max98090->tdm_slots == 3) {
1606
regval |= M98090_MAS_MASK |
1609
/* Few TDM slots, or No TDM */
1610
regval |= M98090_MAS_MASK |
1613
max98090->master = true;
1615
case SND_SOC_DAIFMT_CBS_CFM:
1616
case SND_SOC_DAIFMT_CBM_CFS:
1618
dev_err(component->dev, "DAI clock mode unsupported");
1621
snd_soc_component_write(component, M98090_REG_MASTER_MODE, regval);
1624
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1625
case SND_SOC_DAIFMT_I2S:
1626
regval |= M98090_DLY_MASK;
1628
case SND_SOC_DAIFMT_LEFT_J:
1630
case SND_SOC_DAIFMT_RIGHT_J:
1631
regval |= M98090_RJ_MASK;
1633
case SND_SOC_DAIFMT_DSP_A:
1634
/* Not supported mode */
1636
dev_err(component->dev, "DAI format unsupported");
1640
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1641
case SND_SOC_DAIFMT_NB_NF:
1643
case SND_SOC_DAIFMT_NB_IF:
1644
regval |= M98090_WCI_MASK;
1646
case SND_SOC_DAIFMT_IB_NF:
1647
regval |= M98090_BCI_MASK;
1649
case SND_SOC_DAIFMT_IB_IF:
1650
regval |= M98090_BCI_MASK|M98090_WCI_MASK;
1653
dev_err(component->dev, "DAI invert mode unsupported");
1658
* This accommodates an inverted logic in the MAX98090 chip
1659
* for Bit Clock Invert (BCI). The inverted logic is only
1660
* seen for the case of TDM mode. The remaining cases have
1663
if (max98090->tdm_slots > 1)
1664
regval ^= M98090_BCI_MASK;
1666
snd_soc_component_write(component,
1667
M98090_REG_INTERFACE_FORMAT, regval);
1673
static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai,
1674
unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1676
struct snd_soc_component *component = codec_dai->component;
1677
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1678
struct max98090_cdata *cdata;
1679
cdata = &max98090->dai[0];
1681
if (slots < 0 || slots > 4)
1684
max98090->tdm_slots = slots;
1685
max98090->tdm_width = slot_width;
1687
if (max98090->tdm_slots > 1) {
1688
/* SLOTL SLOTR SLOTDLY */
1689
snd_soc_component_write(component, M98090_REG_TDM_FORMAT,
1690
0 << M98090_TDM_SLOTL_SHIFT |
1691
1 << M98090_TDM_SLOTR_SHIFT |
1692
0 << M98090_TDM_SLOTDLY_SHIFT);
1695
snd_soc_component_update_bits(component, M98090_REG_TDM_CONTROL,
1701
* Normally advisable to set TDM first, but this permits either order
1704
max98090_dai_set_fmt(codec_dai, max98090->dai_fmt);
1709
static int max98090_set_bias_level(struct snd_soc_component *component,
1710
enum snd_soc_bias_level level)
1712
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1716
case SND_SOC_BIAS_ON:
1719
case SND_SOC_BIAS_PREPARE:
1721
* SND_SOC_BIAS_PREPARE is called while preparing for a
1722
* transition to ON or away from ON. If current bias_level
1723
* is SND_SOC_BIAS_ON, then it is preparing for a transition
1724
* away from ON. Disable the clock in that case, otherwise
1727
if (IS_ERR(max98090->mclk))
1730
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
1731
clk_disable_unprepare(max98090->mclk);
1733
ret = clk_prepare_enable(max98090->mclk);
1739
case SND_SOC_BIAS_STANDBY:
1740
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1741
ret = regcache_sync(max98090->regmap);
1743
dev_err(component->dev,
1744
"Failed to sync cache: %d\n", ret);
1750
case SND_SOC_BIAS_OFF:
1751
/* Set internal pull-up to lowest power mode */
1752
snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT,
1753
M98090_JDWK_MASK, M98090_JDWK_MASK);
1754
regcache_mark_dirty(max98090->regmap);
1760
static const int dmic_divisors[] = { 2, 3, 4, 5, 6, 8 };
1762
static const int comp_lrclk_rates[] = {
1763
8000, 16000, 32000, 44100, 48000, 96000
1770
int comp[6]; /* One each for 8, 16, 32, 44.1, 48, and 96 kHz */
1771
} settings[6]; /* One for each dmic divisor. */
1774
static const struct dmic_table dmic_table[] = { /* One for each pclk freq. */
1778
{ .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1779
{ .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1780
{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1781
{ .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1782
{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1783
{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1789
{ .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1790
{ .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1791
{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1792
{ .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1793
{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1794
{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1800
{ .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1801
{ .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1802
{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1803
{ .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1804
{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1805
{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1811
{ .freq = 2, .comp = { 7, 8, 1, 1, 1, 1 } },
1812
{ .freq = 1, .comp = { 7, 8, 0, 0, 0, 0 } },
1813
{ .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1814
{ .freq = 0, .comp = { 7, 8, 4, 4, 5, 5 } },
1815
{ .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1816
{ .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1822
{ .freq = 2, .comp = { 0, 0, 0, 0, 0, 0 } },
1823
{ .freq = 1, .comp = { 7, 8, 1, 1, 1, 1 } },
1824
{ .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1825
{ .freq = 0, .comp = { 7, 8, 2, 2, 3, 3 } },
1826
{ .freq = 0, .comp = { 7, 8, 1, 1, 2, 2 } },
1827
{ .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1832
static int max98090_find_divisor(int target_freq, int pclk)
1834
int current_diff = INT_MAX;
1835
int test_diff = INT_MAX;
1836
int divisor_index = 0;
1839
for (i = 0; i < ARRAY_SIZE(dmic_divisors); i++) {
1840
test_diff = abs(target_freq - (pclk / dmic_divisors[i]));
1841
if (test_diff < current_diff) {
1842
current_diff = test_diff;
1847
return divisor_index;
1850
static int max98090_find_closest_pclk(int pclk)
1856
for (i = 0; i < ARRAY_SIZE(dmic_table); i++) {
1857
if (pclk == dmic_table[i].pclk)
1859
if (pclk < dmic_table[i].pclk) {
1862
m1 = pclk - dmic_table[i-1].pclk;
1863
m2 = dmic_table[i].pclk - pclk;
1874
static int max98090_configure_dmic(struct max98090_priv *max98090,
1875
int target_dmic_clk, int pclk, int fs)
1883
pclk_index = max98090_find_closest_pclk(pclk);
1887
micclk_index = max98090_find_divisor(target_dmic_clk, pclk);
1889
for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
1890
if (fs <= (comp_lrclk_rates[i] + comp_lrclk_rates[i+1]) / 2)
1894
dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq;
1895
dmic_comp = dmic_table[pclk_index].settings[micclk_index].comp[i];
1897
regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE,
1899
micclk_index << M98090_MICCLK_SHIFT);
1901
regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG,
1902
M98090_DMIC_COMP_MASK | M98090_DMIC_FREQ_MASK,
1903
dmic_comp << M98090_DMIC_COMP_SHIFT |
1904
dmic_freq << M98090_DMIC_FREQ_SHIFT);
1909
static int max98090_dai_startup(struct snd_pcm_substream *substream,
1910
struct snd_soc_dai *dai)
1912
struct snd_soc_component *component = dai->component;
1913
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1914
unsigned int fmt = max98090->dai_fmt;
1916
/* Remove 24-bit format support if it is not in right justified mode. */
1917
if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_RIGHT_J) {
1918
substream->runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE;
1919
snd_pcm_hw_constraint_msbits(substream->runtime, 0, 16, 16);
1924
static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
1925
struct snd_pcm_hw_params *params,
1926
struct snd_soc_dai *dai)
1928
struct snd_soc_component *component = dai->component;
1929
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1930
struct max98090_cdata *cdata;
1932
cdata = &max98090->dai[0];
1933
max98090->bclk = snd_soc_params_to_bclk(params);
1934
if (params_channels(params) == 1)
1935
max98090->bclk *= 2;
1937
max98090->lrclk = params_rate(params);
1939
switch (params_width(params)) {
1941
snd_soc_component_update_bits(component, M98090_REG_INTERFACE_FORMAT,
1948
if (max98090->master)
1949
max98090_configure_bclk(component);
1951
cdata->rate = max98090->lrclk;
1953
/* Update filter mode */
1954
if (max98090->lrclk < 24000)
1955
snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
1956
M98090_MODE_MASK, 0);
1958
snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
1959
M98090_MODE_MASK, M98090_MODE_MASK);
1961
/* Update sample rate mode */
1962
if (max98090->lrclk < 50000)
1963
snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
1964
M98090_DHF_MASK, 0);
1966
snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
1967
M98090_DHF_MASK, M98090_DHF_MASK);
1969
max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk,
1978
static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
1979
int clk_id, unsigned int freq, int dir)
1981
struct snd_soc_component *component = dai->component;
1982
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1984
/* Requested clock frequency is already setup */
1985
if (freq == max98090->sysclk)
1988
if (!IS_ERR(max98090->mclk)) {
1989
freq = clk_round_rate(max98090->mclk, freq);
1990
clk_set_rate(max98090->mclk, freq);
1993
/* Setup clocks for slave mode, and using the PLL
1994
* PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1995
* 0x02 (when master clk is 20MHz to 40MHz)..
1996
* 0x03 (when master clk is 40MHz to 60MHz)..
1998
if ((freq >= 10000000) && (freq <= 20000000)) {
1999
snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
2001
max98090->pclk = freq;
2002
} else if ((freq > 20000000) && (freq <= 40000000)) {
2003
snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
2005
max98090->pclk = freq >> 1;
2006
} else if ((freq > 40000000) && (freq <= 60000000)) {
2007
snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
2009
max98090->pclk = freq >> 2;
2011
dev_err(component->dev, "Invalid master clock frequency\n");
2015
max98090->sysclk = freq;
2020
static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute)
2022
struct snd_soc_component *component = codec_dai->component;
2025
regval = mute ? M98090_DVM_MASK : 0;
2026
snd_soc_component_update_bits(component, M98090_REG_DAI_PLAYBACK_LEVEL,
2027
M98090_DVM_MASK, regval);
2032
static int max98090_dai_trigger(struct snd_pcm_substream *substream, int cmd,
2033
struct snd_soc_dai *dai)
2035
struct snd_soc_component *component = dai->component;
2036
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2039
case SNDRV_PCM_TRIGGER_START:
2040
case SNDRV_PCM_TRIGGER_RESUME:
2041
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2042
if (!max98090->master && dai->active == 1)
2043
queue_delayed_work(system_power_efficient_wq,
2044
&max98090->pll_det_enable_work,
2045
msecs_to_jiffies(10));
2047
case SNDRV_PCM_TRIGGER_STOP:
2048
case SNDRV_PCM_TRIGGER_SUSPEND:
2049
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2050
if (!max98090->master && dai->active == 1)
2051
schedule_work(&max98090->pll_det_disable_work);
2060
static void max98090_pll_det_enable_work(struct work_struct *work)
2062
struct max98090_priv *max98090 =
2063
container_of(work, struct max98090_priv,
2064
pll_det_enable_work.work);
2065
struct snd_soc_component *component = max98090->component;
2066
unsigned int status, mask;
2069
* Clear status register in order to clear possibly already occurred
2070
* PLL unlock. If PLL hasn't still locked, the status will be set
2071
* again and PLL unlock interrupt will occur.
2072
* Note this will clear all status bits
2074
regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2077
* Queue jack work in case jack state has just changed but handler
2080
regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2082
if (status & M98090_JDET_MASK)
2083
queue_delayed_work(system_power_efficient_wq,
2084
&max98090->jack_work,
2085
msecs_to_jiffies(100));
2087
/* Enable PLL unlock interrupt */
2088
snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
2090
1 << M98090_IULK_SHIFT);
2093
static void max98090_pll_det_disable_work(struct work_struct *work)
2095
struct max98090_priv *max98090 =
2096
container_of(work, struct max98090_priv, pll_det_disable_work);
2097
struct snd_soc_component *component = max98090->component;
2099
cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2101
/* Disable PLL unlock interrupt */
2102
snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
2103
M98090_IULK_MASK, 0);
2106
static void max98090_pll_work(struct work_struct *work)
2108
struct max98090_priv *max98090 =
2109
container_of(work, struct max98090_priv, pll_work);
2110
struct snd_soc_component *component = max98090->component;
2112
if (!snd_soc_component_is_active(component))
2115
dev_info_ratelimited(component->dev, "PLL unlocked\n");
2117
/* Toggle shutdown OFF then ON */
2118
snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2119
M98090_SHDNN_MASK, 0);
2121
snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2122
M98090_SHDNN_MASK, M98090_SHDNN_MASK);
2124
/* Give PLL time to lock */
2128
static void max98090_jack_work(struct work_struct *work)
2130
struct max98090_priv *max98090 = container_of(work,
2131
struct max98090_priv,
2133
struct snd_soc_component *component = max98090->component;
2137
/* Read a second time */
2138
if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) {
2140
/* Strong pull up allows mic detection */
2141
snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT,
2142
M98090_JDWK_MASK, 0);
2146
reg = snd_soc_component_read32(component, M98090_REG_JACK_STATUS);
2148
/* Weak pull up allows only insertion detection */
2149
snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT,
2150
M98090_JDWK_MASK, M98090_JDWK_MASK);
2152
reg = snd_soc_component_read32(component, M98090_REG_JACK_STATUS);
2155
reg = snd_soc_component_read32(component, M98090_REG_JACK_STATUS);
2157
switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) {
2158
case M98090_LSNS_MASK | M98090_JKSNS_MASK:
2159
dev_dbg(component->dev, "No Headset Detected\n");
2161
max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2168
if (max98090->jack_state ==
2169
M98090_JACK_STATE_HEADSET) {
2171
dev_dbg(component->dev,
2172
"Headset Button Down Detected\n");
2175
* max98090_headset_button_event(codec)
2176
* could be defined, then called here.
2179
status |= SND_JACK_HEADSET;
2180
status |= SND_JACK_BTN_0;
2185
/* Line is reported as Headphone */
2186
/* Nokia Headset is reported as Headphone */
2187
/* Mono Headphone is reported as Headphone */
2188
dev_dbg(component->dev, "Headphone Detected\n");
2190
max98090->jack_state = M98090_JACK_STATE_HEADPHONE;
2192
status |= SND_JACK_HEADPHONE;
2196
case M98090_JKSNS_MASK:
2197
dev_dbg(component->dev, "Headset Detected\n");
2199
max98090->jack_state = M98090_JACK_STATE_HEADSET;
2201
status |= SND_JACK_HEADSET;
2206
dev_dbg(component->dev, "Unrecognized Jack Status\n");
2210
snd_soc_jack_report(max98090->jack, status,
2211
SND_JACK_HEADSET | SND_JACK_BTN_0);
2214
static irqreturn_t max98090_interrupt(int irq, void *data)
2216
struct max98090_priv *max98090 = data;
2217
struct snd_soc_component *component = max98090->component;
2220
unsigned int active;
2222
/* Treat interrupt before codec is initialized as spurious */
2223
if (component == NULL)
2226
dev_dbg(component->dev, "***** max98090_interrupt *****\n");
2228
ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2231
dev_err(component->dev,
2232
"failed to read M98090_REG_INTERRUPT_S: %d\n",
2237
ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active);
2240
dev_err(component->dev,
2241
"failed to read M98090_REG_DEVICE_STATUS: %d\n",
2246
dev_dbg(component->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
2247
active, mask, active & mask);
2254
if (active & M98090_CLD_MASK)
2255
dev_err(component->dev, "M98090_CLD_MASK\n");
2257
if (active & M98090_SLD_MASK)
2258
dev_dbg(component->dev, "M98090_SLD_MASK\n");
2260
if (active & M98090_ULK_MASK) {
2261
dev_dbg(component->dev, "M98090_ULK_MASK\n");
2262
schedule_work(&max98090->pll_work);
2265
if (active & M98090_JDET_MASK) {
2266
dev_dbg(component->dev, "M98090_JDET_MASK\n");
2268
pm_wakeup_event(component->dev, 100);
2270
queue_delayed_work(system_power_efficient_wq,
2271
&max98090->jack_work,
2272
msecs_to_jiffies(100));
2275
if (active & M98090_DRCACT_MASK)
2276
dev_dbg(component->dev, "M98090_DRCACT_MASK\n");
2278
if (active & M98090_DRCCLP_MASK)
2279
dev_err(component->dev, "M98090_DRCCLP_MASK\n");
2285
* max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2287
* @component: MAX98090 component
2288
* @jack: jack to report detection events on
2290
* Enable microphone detection via IRQ on the MAX98090. If GPIOs are
2291
* being used to bring out signals to the processor then only platform
2292
* data configuration is needed for MAX98090 and processor GPIOs should
2293
* be configured using snd_soc_jack_add_gpios() instead.
2295
* If no jack is supplied detection will be disabled.
2297
int max98090_mic_detect(struct snd_soc_component *component,
2298
struct snd_soc_jack *jack)
2300
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2302
dev_dbg(component->dev, "max98090_mic_detect\n");
2304
max98090->jack = jack;
2306
snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
2308
1 << M98090_IJDET_SHIFT);
2310
snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
2315
/* Send an initial empty report */
2316
snd_soc_jack_report(max98090->jack, 0,
2317
SND_JACK_HEADSET | SND_JACK_BTN_0);
2319
queue_delayed_work(system_power_efficient_wq,
2320
&max98090->jack_work,
2321
msecs_to_jiffies(100));
2325
EXPORT_SYMBOL_GPL(max98090_mic_detect);
2327
#define MAX98090_RATES SNDRV_PCM_RATE_8000_96000
2328
#define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
2330
static const struct snd_soc_dai_ops max98090_dai_ops = {
2331
.startup = max98090_dai_startup,
2332
.set_sysclk = max98090_dai_set_sysclk,
2333
.set_fmt = max98090_dai_set_fmt,
2334
.set_tdm_slot = max98090_set_tdm_slot,
2335
.hw_params = max98090_dai_hw_params,
2336
.digital_mute = max98090_dai_digital_mute,
2337
.trigger = max98090_dai_trigger,
2340
static struct snd_soc_dai_driver max98090_dai[] = {
2344
.stream_name = "HiFi Playback",
2347
.rates = MAX98090_RATES,
2348
.formats = MAX98090_FORMATS,
2351
.stream_name = "HiFi Capture",
2354
.rates = MAX98090_RATES,
2355
.formats = MAX98090_FORMATS,
2357
.ops = &max98090_dai_ops,
2361
static int max98090_probe(struct snd_soc_component *component)
2363
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2364
struct max98090_cdata *cdata;
2365
enum max98090_type devtype;
2368
unsigned int micbias;
2370
dev_dbg(component->dev, "max98090_probe\n");
2372
max98090->mclk = devm_clk_get(component->dev, "mclk");
2373
if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER)
2374
return -EPROBE_DEFER;
2376
max98090->component = component;
2378
/* Reset the codec, the DSP core, and disable all interrupts */
2379
max98090_reset(max98090);
2381
/* Initialize private data */
2383
max98090->sysclk = (unsigned)-1;
2384
max98090->pclk = (unsigned)-1;
2385
max98090->master = false;
2387
cdata = &max98090->dai[0];
2388
cdata->rate = (unsigned)-1;
2389
cdata->fmt = (unsigned)-1;
2391
max98090->lin_state = 0;
2392
max98090->pa1en = 0;
2393
max98090->pa2en = 0;
2395
ret = snd_soc_component_read32(component, M98090_REG_REVISION_ID);
2397
dev_err(component->dev, "Failed to read device revision: %d\n",
2402
if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) {
2404
dev_info(component->dev, "MAX98090 REVID=0x%02x\n", ret);
2405
} else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) {
2407
dev_info(component->dev, "MAX98091 REVID=0x%02x\n", ret);
2410
dev_err(component->dev, "Unrecognized revision 0x%02x\n", ret);
2413
if (max98090->devtype != devtype) {
2414
dev_warn(component->dev, "Mismatch in DT specified CODEC type.\n");
2415
max98090->devtype = devtype;
2418
max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2420
INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work);
2421
INIT_DELAYED_WORK(&max98090->pll_det_enable_work,
2422
max98090_pll_det_enable_work);
2423
INIT_WORK(&max98090->pll_det_disable_work,
2424
max98090_pll_det_disable_work);
2425
INIT_WORK(&max98090->pll_work, max98090_pll_work);
2427
/* Enable jack detection */
2428
snd_soc_component_write(component, M98090_REG_JACK_DETECT,
2429
M98090_JDETEN_MASK | M98090_JDEB_25MS);
2432
* Clear any old interrupts.
2433
* An old interrupt ocurring prior to installing the ISR
2434
* can keep a new interrupt from generating a trigger.
2436
snd_soc_component_read32(component, M98090_REG_DEVICE_STATUS);
2438
/* High Performance is default */
2439
snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL,
2441
1 << M98090_DACHP_SHIFT);
2442
snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL,
2443
M98090_PERFMODE_MASK,
2444
0 << M98090_PERFMODE_SHIFT);
2445
snd_soc_component_update_bits(component, M98090_REG_ADC_CONTROL,
2447
1 << M98090_ADCHP_SHIFT);
2449
/* Turn on VCM bandgap reference */
2450
snd_soc_component_write(component, M98090_REG_BIAS_CONTROL,
2451
M98090_VCM_MODE_MASK);
2453
err = device_property_read_u32(component->dev, "maxim,micbias", &micbias);
2455
micbias = M98090_MBVSEL_2V8;
2456
dev_info(component->dev, "use default 2.8v micbias\n");
2457
} else if (micbias > M98090_MBVSEL_2V8) {
2458
dev_err(component->dev, "micbias out of range 0x%x\n", micbias);
2459
micbias = M98090_MBVSEL_2V8;
2462
snd_soc_component_update_bits(component, M98090_REG_MIC_BIAS_VOLTAGE,
2463
M98090_MBVSEL_MASK, micbias);
2465
max98090_add_widgets(component);
2471
static void max98090_remove(struct snd_soc_component *component)
2473
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2475
cancel_delayed_work_sync(&max98090->jack_work);
2476
cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2477
cancel_work_sync(&max98090->pll_det_disable_work);
2478
cancel_work_sync(&max98090->pll_work);
2479
max98090->component = NULL;
2482
static void max98090_seq_notifier(struct snd_soc_component *component,
2483
enum snd_soc_dapm_type event, int subseq)
2485
struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2487
if (max98090->shdn_pending) {
2488
snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2489
M98090_SHDNN_MASK, 0);
2491
snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2492
M98090_SHDNN_MASK, M98090_SHDNN_MASK);
2493
max98090->shdn_pending = false;
2497
static const struct snd_soc_component_driver soc_component_dev_max98090 = {
2498
.probe = max98090_probe,
2499
.remove = max98090_remove,
2500
.seq_notifier = max98090_seq_notifier,
2501
.set_bias_level = max98090_set_bias_level,
2503
.use_pmdown_time = 1,
2505
.non_legacy_dai_naming = 1,
2508
static const struct regmap_config max98090_regmap = {
2512
.max_register = MAX98090_MAX_REGISTER,
2513
.reg_defaults = max98090_reg,
2514
.num_reg_defaults = ARRAY_SIZE(max98090_reg),
2515
.volatile_reg = max98090_volatile_register,
2516
.readable_reg = max98090_readable_register,
2517
.cache_type = REGCACHE_RBTREE,
2520
static int max98090_i2c_probe(struct i2c_client *i2c,
2521
const struct i2c_device_id *i2c_id)
2523
struct max98090_priv *max98090;
2524
const struct acpi_device_id *acpi_id;
2525
kernel_ulong_t driver_data = 0;
2528
pr_debug("max98090_i2c_probe\n");
2530
max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv),
2532
if (max98090 == NULL)
2535
if (ACPI_HANDLE(&i2c->dev)) {
2536
acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table,
2539
dev_err(&i2c->dev, "No driver data\n");
2542
driver_data = acpi_id->driver_data;
2543
} else if (i2c_id) {
2544
driver_data = i2c_id->driver_data;
2547
max98090->devtype = driver_data;
2548
i2c_set_clientdata(i2c, max98090);
2549
max98090->pdata = i2c->dev.platform_data;
2551
ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq",
2552
&max98090->dmic_freq);
2554
max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ;
2556
max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap);
2557
if (IS_ERR(max98090->regmap)) {
2558
ret = PTR_ERR(max98090->regmap);
2559
dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2563
ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2564
max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2565
"max98090_interrupt", max98090);
2567
dev_err(&i2c->dev, "request_irq failed: %d\n",
2572
ret = devm_snd_soc_register_component(&i2c->dev,
2573
&soc_component_dev_max98090, max98090_dai,
2574
ARRAY_SIZE(max98090_dai));
2579
static void max98090_i2c_shutdown(struct i2c_client *i2c)
2581
struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev);
2584
* Enable volume smoothing, disable zero cross. This will cause
2585
* a quick 40ms ramp to mute on shutdown.
2587
regmap_write(max98090->regmap,
2588
M98090_REG_LEVEL_CONTROL, M98090_VSENN_MASK);
2589
regmap_write(max98090->regmap,
2590
M98090_REG_DEVICE_SHUTDOWN, 0x00);
2594
static int max98090_i2c_remove(struct i2c_client *client)
2596
max98090_i2c_shutdown(client);
2602
static int max98090_runtime_resume(struct device *dev)
2604
struct max98090_priv *max98090 = dev_get_drvdata(dev);
2606
regcache_cache_only(max98090->regmap, false);
2608
max98090_reset(max98090);
2610
regcache_sync(max98090->regmap);
2615
static int max98090_runtime_suspend(struct device *dev)
2617
struct max98090_priv *max98090 = dev_get_drvdata(dev);
2619
regcache_cache_only(max98090->regmap, true);
2625
#ifdef CONFIG_PM_SLEEP
2626
static int max98090_resume(struct device *dev)
2628
struct max98090_priv *max98090 = dev_get_drvdata(dev);
2629
unsigned int status;
2631
regcache_mark_dirty(max98090->regmap);
2633
max98090_reset(max98090);
2635
/* clear IRQ status */
2636
regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2638
regcache_sync(max98090->regmap);
2643
static int max98090_suspend(struct device *dev)
2649
static const struct dev_pm_ops max98090_pm = {
2650
SET_RUNTIME_PM_OPS(max98090_runtime_suspend,
2651
max98090_runtime_resume, NULL)
2652
SET_SYSTEM_SLEEP_PM_OPS(max98090_suspend, max98090_resume)
2655
static const struct i2c_device_id max98090_i2c_id[] = {
2656
{ "max98090", MAX98090 },
2657
{ "max98091", MAX98091 },
2660
MODULE_DEVICE_TABLE(i2c, max98090_i2c_id);
2662
static const struct of_device_id max98090_of_match[] = {
2663
{ .compatible = "maxim,max98090", },
2664
{ .compatible = "maxim,max98091", },
2667
MODULE_DEVICE_TABLE(of, max98090_of_match);
2670
static const struct acpi_device_id max98090_acpi_match[] = {
2671
{ "193C9890", MAX98090 },
2674
MODULE_DEVICE_TABLE(acpi, max98090_acpi_match);
2677
static struct i2c_driver max98090_i2c_driver = {
2681
.of_match_table = of_match_ptr(max98090_of_match),
2682
.acpi_match_table = ACPI_PTR(max98090_acpi_match),
2684
.probe = max98090_i2c_probe,
2685
.shutdown = max98090_i2c_shutdown,
2686
.remove = max98090_i2c_remove,
2687
.id_table = max98090_i2c_id,
2690
module_i2c_driver(max98090_i2c_driver);
2692
MODULE_DESCRIPTION("ALSA SoC MAX98090 driver");
2693
MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong");
2694
MODULE_LICENSE("GPL");
added
removed
buildroot/src/oem-audiosdw-lp1836324-1ubuntu1.3/soc/codecs/max98090.c
